A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier
|
|
- Sharlene York
- 5 years ago
- Views:
Transcription
1 A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan
2 Outline Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 2
3 Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 3
4 Background To realize high order modulation, high performance ADC is required (Bit Error Rate) BER ) D N F rate s QPSK 16QAM 64QAM 256QAM D rate : Data rate N: ADC s resolution F s : Sampling frequency [1] A. Matsuzawa, AVIC, 2012 SNR (db) 4
5 Interpolated Pipeline ADC 10-bit, 320 MS/s with low-gain amplifier No calibration for MDAC stage Pipeline Stage Pipeline Stage [2] M. Miyahara, et al., VLSI Circuits,
6 45-dB gain op-amp (with feedback) Amplifier s Linearity Issue Open-Loop SD-amp is not enough for 12-bit ENOB ENOB [bit] N 1 2 log a 2.9 a 3 1 V 2 FS 2 Calculation Simulation N a 3 /a 1 2 N 1st a 3 /a 1 : Amplifier s non-linearity N: ADC resolution (12) N 1st : 1 st stage resolution (4) V FS : full-scale reference range (+/- 75 mv) Source Degeneration (SD) amplifier (Open-loop) 6
7 Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 7
8 Conventional Amplifier Topologies Folded Cascode Telescopic Power High (4I) Low (2I) Swing Range Wide (V DD -4V ds ) Narrow (V DD -5V ds ) 8
9 Body Voltage Controlled Amplifier V INP V BP V BN Output Commonmode Feedback V OUTN M 1 I V COM φ 1,2 M 3 M 4 M 9 V BIASP C 1 C 2 I M 10 M 7 M 5 M 6 M 8 V BIASN C FB M 2 V OUTP V INN Only 2I flows No tail current source M 1 ~M 4 : Input M 5 ~M 6 : Current mirroring M 7 ~M 10 : Gain enhancement V BC Bias Current Feedback φ 1,2 V COM 9
10 Current Biasing Method W 1 : αw 2 = i : αi Current mirroring Current biasing by NMOS body bias control 10
11 Amplifier for Current Biasing Current variation transferred via C 1 C 2 for generating DC voltage for feedback 11
12 Current Biasing Range Current biasing range : 5.5 ~ 10.5 ma g mb is maintained higher than 8.5 ms 12
13 Amplifier for CMFB Outputs are averaged in C 3 Averaged voltage is transferred via C 4 φ 2 V OUTP V COM 200fF C φ 1 1 V OUTN 100fF φ 2 C 3 4pF φ 1 C 4 100fF C 2 A P V DD V OUT (V BIASP ) 13
14 Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 14
15 ADC Architecture 5 stages (1-bit redundancy in 1 st ~ 4 th ) 1 st stage utilizes closed-loop topology 15
16 Amplifier s Offset Calibration Amplifier s offset is cancelled by DAC 16
17 AC Simulation Results ENOB keeps higher than 11.5-bit until MHz input 10.8-bit of ENOB is 400 MS/s and Nyquist input All transistor model Room temperature Without transient noise and component mismatch 17
18 ADC Chip Photo 1P9M 90 nm CMOS, Core area is 0.48 mm 2 18
19 DC Measurement Results DNL: / - 1 INL : / DC characteristic is degraded by parasitic components in input and ref. nodes DNL [LSB] INL [LSB] 19
20 Measured FFT Spectrum 300 MS/s and 100 khz input 10-bit of ENOB is achieved Frequency [MHz] 20
21 Amplifier Performance Table To achieve 12-bit, 400 MS/s ADC operation, Topology Body voltage control DC Gain [db] 45 Power Consumption [mw] 15.6 ( 40 % from Folded-Cascode) Settling Time [ps] 500 Output Swing Range [mv pp ] 600 ( 12.5 % from Telescopic) 21
22 ADC Performance Table This work [3] [4] [5] Resolution [bit] F sample [MS/s] V DD [V] / / / 2.5 Power [mw] ENOB peak [bit] 9.96 (100 khz) (by SNR) FoM [pj/conv.] Technology [nm] (SiGe) Core Area [mm 2 ] Linearity Compensation No Yes Yes Yes Interleave No 4-times No 2-times [3] D. Vecchi, et al., JSSC [4] R. Payne, et al., ISSCC [5] C. Y. Chen and J. Wu, VLSI Circuits,
23 Background Body voltage controlled amplifier 12-bit, 300 MS/s interpolated pipeline ADC Simulation and measurement results Conclusion 23
24 Conclusion Body voltage controlled amplifier is proposed Low power consumption & wide swing range 12-bit, 300 MS/s interpolated pipeline ADC with proposed amplifier is demonstrated No linearity calibration ADC achieves 10-bit of ENOB with slow input Performance can be improved by elimination of input parasitic components 24
25 Acknowledgement This work was partially supported by NEDO, MIC, CREST in JST, STARC, Berkeley Design Automation for the use of the Analog Fast SPICE (AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc. and Huawei. 25
26 Thank you for your interest! Hyunui Lee, 26
27 27
A 6-bit Subranging ADC using Single CDAC Interpolation
A 6-bit Subranging ADC using Single CDAC Interpolation Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline Background Interpolation techniques 6-bit, 500 MS/s
More informationA 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers
A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada
More informationProposing. An Interpolated Pipeline ADC
Proposing An Interpolated Pipeline ADC Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Lab. Background 38GHz long range mm-wave system Role of long range mm-wave Current Optical
More informationA 9.35-ENOB, 14.8 fj/conv.-step Fully- Passive Noise-Shaping SAR ADC
A 9.35-ENOB, 14.8 fj/conv.-step Fully- Passive Noise-Shaping SAR ADC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa Tokyo Institute of Technology Symposia on VLSI Technology and Circuits Outline Background
More informationA Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs
1 A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline 2 Motivation The Calibration
More informationA Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique
1 A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan 2 Outline Motivation Design Concept
More informationA 15.5 db, Wide Signal Swing, Dynamic Amplifier Using a Common- Mode Voltage Detection Technique
A 15.5 db, Wide Signal Swing, Dynamic Amplifier Using a Common- Mode Voltage Detection Technique James Lin, Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Laḃ
More informationA stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder Zhijie Chen, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology,
More informationCHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE
CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined
More informationISSCC 2004 / SESSION 25 / HIGH-RESOLUTION NYQUIST ADCs / 25.4
ISSCC 2004 / SESSION 25 / HIGH-RESOLUTION NYQUIST ADCs / 25.4 25.4 A 1.8V 14b 10MS/s Pipelined ADC in 0.18µm CMOS with 99dB SFDR Yun Chiu, Paul R. Gray, Borivoje Nikolic University of California, Berkeley,
More informationA 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation
Y. Zu, C.- H. Chan, S.- W. Sin, S.- P. U, R.P. Martins, F. Maloberti: "A 35 fj 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self- Embedded Offset Cancellation"; IEEE Asian Solid-
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationProblem 1. Final Exam Spring 2018 (Reposted 11p.m. on April 30)
EE 435 Final Exam Spring 2018 (Reposted 11p.m. on April 30) Name Instructions: This is an open-book, open-notes exam. It is due in the office of the course instructor by 12:00 noon on Wednesday May 2.
More informationA 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC
A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC M. Åberg 2, A. Rantala 2, V. Hakkarainen 1, M. Aho 1, J. Riikonen 1, D. Gomes Martin 2, K. Halonen 1 1 Electronic Circuit Design Laboratory Helsinki University
More informationAsynchronous SAR ADC: Past, Present and Beyond. Mike Shuo-Wei Chen University of Southern California MWSCAS 2014
Asynchronous SAR ADC: Past, Present and Beyond Mike Shuo-Wei Chen University of Southern California MWSCAS 2014 1 Roles of ADCs Responsibility of ADC is increasing more BW, more dynamic range Potentially
More informationA 20GHz Class-C VCO Using Noise Sensitivity Mitigation Technique
Matsuzawa Lab. Matsuzawa & Okada Lab. Tokyo Institute of Technology A 20GHz Class-C VCO Using Noise Sensitivity Mitigation Technique Kento Kimura, Kenichi Okada and Akira Matsuzawa (WE2C-2) Matsuzawa &
More informationLow-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationA Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury
A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury Garren Boggs, Hua Chen, Sridhar Sivapurapu ECE 6414 Final Presentation Outline Motivation System Overview Analog Front
More informationScalable and Synthesizable. Analog IPs
Scalable and Synthesizable Analog IPs Akira Matsuzawa Tokyo Institute of Technology Background and Motivation 1 Issues It becomes more difficult to obtain good analog IPs Insufficient design resources
More informationIMPLEMENTING THE 10-BIT, 50MS/SEC PIPELINED ADC
98 CHAPTER 5 IMPLEMENTING THE 0-BIT, 50MS/SEC PIPELINED ADC 99 5.0 INTRODUCTION This chapter is devoted to describe the implementation of a 0-bit, 50MS/sec pipelined ADC with different stage resolutions
More informationFinal Exam Spring 2012
1 EE 435 Final Exam Spring 2012 Name Instructions: This is an open-book, open-notes, open computer exam but no collaboration either personal or electronic with anyone except the course instructor is permitted.
More informationA fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI
LETTER IEICE Electronics Express, Vol.1, No.15, 1 11 A fully synthesizable injection-locked PLL with feedback current output DAC in 8 nm FDSOI Dongsheng Yang a), Wei Deng, Aravind Tharayil Narayanan, Rui
More informationRECENTLY, low-voltage and low-power circuit design
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 4, APRIL 2008 319 A Programmable 0.8-V 10-bit 60-MS/s 19.2-mW 0.13-m CMOS ADC Operating Down to 0.5 V Hee-Cheol Choi, Young-Ju
More informationA 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS
UT Mixed-Signal/RF Integrated Circuits Seminar Series A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS Pio Balmelli April 19 th, Austin TX 2 Outline VDSL specifications Σ A/D converter features Broadband
More information620 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH /$ IEEE
620 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010 A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp Young-Ju Kim, Hee-Cheol Choi, Gil-Cho
More informationA 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California
A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1 Outline Background Chip Architecture
More informationDESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY
DESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY Neha Bakawale Departmentof Electronics & Instrumentation Engineering, Shri G. S. Institute of
More informationA 2.5 V 109 db DR ADC for Audio Application
276 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.4, DECEMBER, 2010 A 2.5 V 109 db DR ADC for Audio Application Gwangyol Noh and Gil-Cho Ahn Abstract A 2.5 V feed-forward second-order deltasigma
More informationEE247 Lecture 23. Advanced calibration techniques. Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC
EE247 Lecture 23 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Advanced calibration techniques Compensating inter-stage amplifier non-linearity Calibration via parallel
More informationA SAR-Assisted Two-Stage Pipeline ADC Chun C. Lee, Member, IEEE, and Michael P. Flynn, Senior Member, IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 4, APRIL 2011 859 A SAR-Assisted Two-Stage Pipeline ADC Chun C. Lee, Member, IEEE, and Michael P. Flynn, Senior Member, IEEE Abstract Successive approximation
More informationDESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More information2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS November 30 - December 3, 2008 Venetian Macao Resort-Hotel Macao, China IEEE Catalog Number: CFP08APC-USB ISBN: 978-1-4244-2342-2 Library of Congress:
More informationA 0.7 V-to-1.0 V 10.1 dbm-to-13.2 dbm 60-GHz Power Amplifier Using Digitally- Assisted LDO Considering HCI Issues
A 0.7 V-to-1.0 V 10.1 dbm-to-13.2 dbm 60-GHz Power Amplifier Using Digitally- Assisted LDO Considering HCI Issues Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of
More informationIntegrated Microsystems Laboratory. Franco Maloberti
University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti franco.maloberti@unipv.it OUTLINE Introduction Managing the noise power budget Challenges of State-of-the-art
More informationLow Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier
RESEARCH ARTICLE OPEN ACCESS Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier Akshay Kumar Kansal 1, Asst Prof. Gayatri Sakya 2 Electronics and Communication Department, 1,2
More informationA Rail-to-Rail Input 12b 2 MS/s 0.18 µm CMOS Cyclic ADC for Touch Screen Applications
160 HEE-CHEOL CHOI et al : A RAIL-TO-RAIL INPUT 12B 2 MS/S 0.18 µm CMOS CYCLIC ADC FOR TOUCH SCREEN APPLICATIONS A Rail-to-Rail Input 12b 2 MS/s 0.18 µm CMOS Cyclic ADC for Touch Screen Applications Hee-Cheol
More informationA Low-Voltage, Low-Power, Two-Stage Amplifier for Switched-Capacitor Applications in 90 nm CMOS Process
A Low-Voltage, Low-Power, Two-Stage Amplifier for Switched-Capacitor Applications in 90 nm CMOS Process S. H. Mirhosseini* and A. Ayatollahi* Downloaded from ijeee.iust.ac.ir at 16:45 IRDT on Tuesday April
More informationA Successive Approximation ADC based on a new Segmented DAC
A Successive Approximation ADC based on a new Segmented DAC segmented current-mode DAC successive approximation ADC bi-direction segmented current-mode DAC DAC INL 0.47 LSB DNL 0.154 LSB DAC 3V 8 2MS/s
More informationA Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications
A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa Tokyo Institute
More informationDesign of an Assembly Line Structure ADC
Design of an Assembly Line Structure ADC Chen Hu 1, Feng Xie 1,Ming Yin 1 1 Department of Electronic Engineering, Naval University of Engineering, Wuhan, China Abstract This paper presents a circuit design
More informationEFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s
EFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s B.Padmavathi, ME (VLSI Design), Anand Institute of Higher Technology, Chennai, India krishypadma@gmail.com Abstract In electronics, a comparator
More informationWideband Sampling by Decimation in Frequency
Wideband Sampling by Decimation in Frequency Martin Snelgrove http://www.kapik.com 192 Spadina Ave. Suite 218 Toronto, Ontario, M5T2C2 Canada Copyright Kapik Integration 2011 WSG: New Architectures for
More informationA 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors
LETTER IEICE Electronics Express, Vol.14, No.2, 1 12 A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors Tongxi Wang a), Min-Woong Seo
More informationLow-power Sigma-Delta AD Converters
Low-power Sigma-Delta AD Converters Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 211 Table of contents Delta-sigma modulation The switch problem The
More informationISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5 20.5 A 2.4GHz CMOS Transceiver and Baseband Processor Chipset for 802.11b Wireless LAN Application George Chien, Weishi Feng, Yungping
More informationRevision History. Contents
Revision History Ver. # Rev. Date Rev. By Comment 0.0 9/15/2012 Initial draft 1.0 9/16/2012 Remove class A part 2.0 9/17/2012 Comments and problem 2 added 3.0 10/3/2012 cmdmprobe re-simulation, add supplement
More informationA Digitally Enhanced 1.8-V 15-b 40- Msample/s CMOS Pipelined ADC
A Digitally Enhanced.8-V 5-b 4- Msample/s CMOS d ADC Eric Siragusa and Ian Galton University of California San Diego Now with Analog Devices San Diego California Outline Conventional PADC Example Digitally
More informationArchitectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters
0 Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters F. Maloberti University of Pavia - Italy franco.maloberti@unipv.it 1 Introduction Summary Sigma-Delta
More informationAnalog-to-Digital i Converters
CSE 577 Spring 2011 Analog-to-Digital i Converters Jaehyun Lim, Kyusun Choi Department t of Computer Science and Engineering i The Pennsylvania State University ADC Glossary DNL (differential nonlinearity)
More informationAn Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters
Circuits and Systems, 2011, 2, 183-189 doi:10.4236/cs.2011.23026 Published Online July 2011 (http://www.scirp.org/journal/cs) An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application
More informationA 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic Abstract P.Prasad Rao 1 and Prof.K.Lal Kishore 2, 1 Research Scholar, JNTU-Hyderabad prasadrao_hod@yahoo.co.in
More informationDesign Challenges of Analog-to-Digital Converters in Nanoscale CMOS
IEICE TRANS. ELECTRON., VOL.E90 C, NO.4 APRIL 2007 779 INVITED PAPER Special Section on Low-Power, High-Speed LSIs and Related Technologies Design Challenges of Analog-to-Digital Converters in Nanoscale
More information/$ IEEE
894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration Hee-Cheol Choi, Young-Ju Kim,
More informationOperational Amplifier with Two-Stage Gain-Boost
Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization, Lisbon, Portugal, September 22-24, 2006 482 Operational Amplifier with Two-Stage Gain-Boost FRANZ SCHLÖGL
More informationEE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.
EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:
More informationModeling and Implementation of A 6-Bit, 50MHz Pipelined ADC in CMOS
Master s Thesis Modeling and Implementation of A 6-Bit, 50MHz Pipelined ADC in CMOS Qazi Omar Farooq Department of Electrical and Information Technology, Faculty of Engineering, LTH, Lund University, 2016.
More informationDigital Calibration for Current-Steering DAC Linearity Enhancement
Digital Calibration for Current-Steering DAC Linearity Enhancement Faculty of Science and Technology, Division of Electronics & Informatics Gunma University Shaiful Nizam Mohyar, Haruo Kobayashi Gunma
More informationA Two- Bit- per- Cycle Successive- Approximation ADC with Background Offset Calibration
M. Casubolo, M. Grassi, A. Lombardi, F. Maloberti, P. Malcovati: "A Two-Bit-per- Cycle Successive-Approximation ADC with Background Calibration"; 15th IEEE Int. Conf. on Electronics, Circuits and Systems,
More informationA 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction. Andrea Panigada, Ian Galton
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction Andrea Panigada, Ian Galton University of California at San Diego, La Jolla, CA INTEGRATED SIGNAL PROCESSING
More informationDesign of Rail-to-Rail Op-Amp in 90nm Technology
IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics
More informationDesign of High-Speed Op-Amps for Signal Processing
Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS
More informationA Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 4 (Nov. - Dec. 2012), PP 42-46 A Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive
More informationA Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS
A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology
More informationFall 2004; E6316: Analog Systems in VLSI; 4 bit Flash A/D converter
Fall 2004; E6316: Analog Systems in VLSI; 4 bit Flash A/D converter Nagendra Krishnapura (nkrishna@vitesse.com) due on 21 Dec. 2004 You are required to design a 4bit Flash A/D converter at 500 MS/s. The
More informationA VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals
A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals Bongjin Kim, Somnath Kundu, Seokkyun Ko and Chris H. Kim University of Minnesota,
More informationWorkshop ESSCIRC. Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit- SAR-ADC. 17. September 2010.
Workshop ESSCIRC Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit- SAR-ADC 17. September 2010 Christof Dohmen Outline System Overview Analog-Front-End Chopper-Amplifier
More informationAnother way to implement a folding ADC
Another way to implement a folding ADC J. Van Valburg and R. van de Plassche, An 8-b 650 MHz Folding ADC, IEEE JSSC, vol 27, #12, pp. 1662-6, Dec 1992 Coupled Differential Pair J. Van Valburg and R. van
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO
More informationA 42 fj 8-bit 1.0-GS/s folding and interpolating ADC with 1 GHz signal bandwidth
LETTER IEICE Electronics Express, Vol.11, No.2, 1 9 A 42 fj 8-bit 1.0-GS/s folding and interpolating ADC with 1 GHz signal bandwidth Mingshuo Wang a), Fan Ye, Wei Li, and Junyan Ren b) State Key Laboratory
More informationArchitectures and circuits for timeinterleaved. Sandeep Gupta Teranetics, Santa Clara, CA
Architectures and circuits for timeinterleaved ADC s Sandeep Gupta Teranetics, Santa Clara, CA Outline Introduction to time-interleaved architectures. Conventional Sampling architectures and their application
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationDesign of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications
RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication
More informationWITH the recent development of communication systems
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011 2127 A 12b 50 MS/s 21.6 mw 0.18 m CMOS ADC Maximally Sharing Capacitors and Op-Amps Kyung-Hoon Lee, Student Member,
More informationSelecting and Using High-Precision Digital-to-Analog Converters
Selecting and Using High-Precision Digital-to-Analog Converters Chad Steward DAC Design Section Leader Linear Technology Corporation Many applications, including precision instrumentation, industrial automation,
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationEE247 Lecture 20. Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability
EE247 Lecture 2 ADC Converters ADC architectures (continued) Comparator architectures Latched comparators Latched comparators incorporating preamplifier Sample-data comparators Offset cancellation Comparator
More informationSTATE-OF-THE-ART read channels in high-performance
258 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 2, FEBRUARY 2007 A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers Ding-Lan Shen, Student Member, IEEE, and Tai-Cheng Lee, Member,
More informationSecond-Order Sigma-Delta Modulator in Standard CMOS Technology
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 1, No. 3, November 2004, 37-44 Second-Order Sigma-Delta Modulator in Standard CMOS Technology Dragiša Milovanović 1, Milan Savić 1, Miljan Nikolić 1 Abstract:
More informationPipelined Analog-to-Digital converter (ADC)
Analog Integr Circ Sig Process (2012) 63:495 501 DOI 10.1007/s10470-010-9453-0 MIXED SIGNAL LETTER Pipelined Analog-to-Digital converter (ADC) Mingjun Fan Junyan Ren Ning Li Fan Ye Jun Xu Abstract A set
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More informationCMOS ADC & DAC Principles
CMOS ADC & DAC Principles Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 201 Table of contents Definitions Digital-to-analog converters Resistive Capacitive
More informationModulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies
A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper
More informationAn HCI-Healing 60GHz CMOS Transceiver
An HCI-Healing 60GHz CMOS Transceiver Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationIndex terms: Analog to Digital conversion, capacitor sharing, high speed OPAMP-sharing pipelined analog to digital convertor, Low power.
Pipeline ADC using Switched Capacitor Sharing Technique with 2.5 V, 10-bit Ankit Jain Dept. of Electronics and Communication, Indore Institute of Science & Technology, Indore, India Abstract: This paper
More informationHigh Performance Zero-crossing Based Pipelined Analog-to-Digtal Converters. Yue Jack Chu
High Performance Zero-crossing Based Pipelined Analog-to-Digtal Converters by Yue Jack Chu B.S. in EECS, UC Berkeley (2006) S.M., Massachusetts Institute of Technology (2008) Submitted to the Department
More information4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter
4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter Jinrong Wang B.Sc. Ningbo University Supervisor: dr.ir. Wouter A. Serdijn Submitted to The Faculty of Electrical Engineering, Mathematics
More informationLOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS. Alireza Nilchi
LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS by Alireza Nilchi A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical
More informationFuture Directions in. December 12, 2008 Boris Murmann Murmann
Future Directions in Mixed-Signal IC Design December 12, 2008 Boris Murmann murmann@stanford.edu @t d Murmann Mixed-Signal Group Growth ~2050 Source: European Nanotechnology Roadmap 2 Business as Usual?
More informationA 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration
A b 5MS/s.mW SAR ADC with redundancy and digital background calibration The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As
More informationClass-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 1/27 Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits S. Sutula 1, M. Dei 1, L. Terés 1,2 and F. Serra-Graells
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationFigure 1 Typical block diagram of a high speed voltage comparator.
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 6, Ver. I (Nov. - Dec. 2016), PP 58-63 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Design of Low Power Efficient
More informationA low power 12-bit and 25-MS/s pipelined ADC for the ILC/Ecal integrated readout
A low power 12-bit and 25-MS/s pipelined ADC for the ILC/Ecal integrated readout F. Rarbi, D. Dzahini, L. Gallin-Martel To cite this version: F. Rarbi, D. Dzahini, L. Gallin-Martel. A low power 12-bit
More informationDESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION
DESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION SANTOSH KUMAR PATNAIK 1, DR. SWAPNA BANERJEE 2 1,2 E & ECE Department, Indian Institute of Technology, Kharagpur, Kharagpur, India Abstract-This
More informationCascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University
Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University Bruce A. Wooley - 1 - Copyright 2005, Stanford University Outline Oversampling modulators for A-to-D conversion
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationAcronyms. ADC analog-to-digital converter. BEOL back-end-of-line
Acronyms ADC analog-to-digital converter BEOL back-end-of-line CDF cumulative distribution function CMOS complementary metal-oxide-semiconductor CPU central processing unit CR charge-redistribution CS
More informationA CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging Systems
A CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging Systems Taehoon Kim, Han Yang, Sangmin Shin, Hyongmin Lee and Suhwan Kim Electrical and Computer Engineering and
More information