EE247 Lecture 20. Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability

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1 EE247 Lecture 2 ADC Converters ADC architectures (continued) Comparator architectures Latched comparators Latched comparators incorporating preamplifier Sample-data comparators Offset cancellation Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability EECS 247 Lecture 2: Data Converters 25 H.K. Page Flash Converter B-bit flash ADC: DAC generates all possible 2 B - levels 2 B - comparators compare to DAC outputs Comparator output: If V DAC < If V DAC > Comparator outputs form thermometer code Encoder converts thermometer to binary code V EF D A C 2 B - B Encoder Digital Output EECS 247 Lecture 2: Data Converters 25 H.K. Page 2

2 Flash ADC Converter Example: 3-bit Conversion V EF V EF Thermometer code Encoder B-bits Time EECS 247 Lecture 2: Data Converters 25 H.K. Page 3 Flash Converter Very fast: only clock cycle per conversion Half cycle VIN & VDAC comparison Half cycle 2 B - to B encoding High complexity: 2 B - comparators High input node /2 /2. V EF Encoder Thermometer code B-bits Digital Output EECS 247 Lecture 2: Data Converters 25 H.K. Page 4

3 Folding Converter Folding Circuit MSB ADC LSB ADC Digital Output Significantly fewer comparators than flash Fast Nonidealities in folder limit resolution to ~-bits EECS 247 Lecture 2: Data Converters 25 H.K. Page 5 Time Interleaved Converter 4 T/H ADC Extremely fast: Limited by speed of T/H Accuracy limited by mismatch in individual ADCs (timing, offset, gain, ) ADC ADC ADC + T/4 + 2T/4 + 3T/4 Serial / Parallel Conversion Digital Output EECS 247 Lecture 2: Data Converters 25 H.K. Page 6

4 esidue Type ADC Partial Digital Output coarse ADC (... 6 Bit) DAC Error T/H & Gain (optional) Quantization error output ( residuum ) enables cascading for higher resolution Great flexibility for stages: flash, oversampling ADC, Optional T/H enables parallelism (pipelining) Fast: one clock per conversion (with T/H), latency EECS 247 Lecture 2: Data Converters 25 H.K. Page 7 Pipelined ADC Stage B Bits Stage 2 B 2 Bits Stage K B k Bits Digital Correction Logic Digital output up to (B + B ) B k ) Bits Approaches speed of flash, but much lower complexity One clock per conversion, but K clocks latency Efficient digital calibration possible Versatile: from 6Bits / MS/s to 4Bits / MS/s EECS 247 Lecture 2: Data Converters 25 H.K. Page 8

5 Algorithmic ADC Start of conversion Digital Output Shift egister & Correction Logic coarse ADC DAC 2 B T/H (... 6 Bit) esidue Essentially same as pipeline, but a single stage is used for all partial conversions K clocks per conversion EECS 247 Lecture 2: Data Converters 25 H.K. Page 9 Oversampled ADC /M H(z) Digital Decimation Filter Digital Output DAC Hard to comprehend easy to build Input is oversampled (M times faster than output rate) educes Anti-Aliasing filter requirements and capacitor size Accuracy independent of component matching Very high resolution achievable (> 2 Bits) EECS 247 Lecture 2: Data Converters 25 H.K. Page

6 Throughput ate Comparison esolution [Bit] Flash, Pipeline~ to 2 Successive Approximation~B 2 nd Order -Bit Oversampled ~2 (.4B+) Serial ~2 B Clock Cycles per Conversion EECS 247 Lecture 2: Data Converters 25 H.K. Page Speed-esolution Map [ EECS 247 Lecture 2: Data Converters 25 H.K. Page 2

7 High-Speed A/D Converters Flash Converter Comparator design considerations Binary Encoder Interpolation Folding Pipelined ADCs EECS 247 Lecture 2: Data Converters 25 H.K. Page 3 Flash Converter Very fast: only clock cycle per conversion /2 V EF High complexity: 2 B - comparators. Encoder Digital Output High input capacitance /2 EECS 247 Lecture 2: Data Converters 25 H.K. Page 4

8 Flash Converter Example: 8-bits ADC V EF 8-bits 255 comparators /2 V EF =V LSB=4mV DNL</2LSB Comparator input referred offset < 2mV. Encoder Digital Output 2mV =6σ offset σ offset <.33mV /2 EECS 247 Lecture 2: Data Converters 25 H.K. Page 5 Flash ADC Converter Example: 8-bits ADC (continued) σ Offset <.33mV Let us assume in the technology used: Voffset-per-unit-sqrt(WxL)=5mV 5mV 2 V ffset = =.33mV W L= 23μ W L 2 2 Assuming: Cox = 5 ff/ μ CGS = CoxW L= 765 ff 3 Total input capacitance: = 95 pf! Issues: Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on/off- input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion ef: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp , October 989. EECS 247 Lecture 2: Data Converters 25 H.K. Page 6

9 Flash ADC Converter Example (continued) Trade-offs: Allowing larger DNL of LSB instead of.5lsb: Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 educes the input device area by a factor of 4 educes the input capacitance by a factor of 4! educing the ADC resolution by -bit Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 educes the input device area by a factor of 4 educe the input capacitance by a factor of 4 EECS 247 Lecture 2: Data Converters 25 H.K. Page 7 Flash Converter Comparator Maximum Offset versus ADC esolution Assumption: DNL=.5LSB Note: Depending on min acceptable yield, numbers associated with 2σ to 7σ offset voltage Maximum Comparator V offset [mv] 2 - V EF =2V V EF =V ADC esolution EECS 247 Lecture 2: Data Converters 25 H.K. Page 8

10 Voltage Comparators + V in V out ( Digital Output) Function: compare the instantaneous value of two analog signals Important features: Maximum clock rate settling time, slew rate, small signal bandwidth esolution gain, offset Overdrive recovery Input capacitance (and linearity of input capacitance!) Power dissipation Common-mode rejection Kickback noise EECS 247 Lecture 2: Data Converters 25 H.K. Page 9 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : Latch-only comparator Low-gain amplifier + a high-sensitivity latch Sample-data comparators T/H input Offset cancellation EECS 247 Lecture 2: Data Converters 25 H.K. Page 2

11 CMOS Latched Comparators Comparator amplification need not be linear can use a latch regeneration Amplification + positive feedback EECS 247 Lecture 2: Data Converters 25 H.K. Page 2 CMOS Latched Comparators Latch can be modeled as a single-pole amp + positive feedback EECS 247 Lecture 2: Data Converters 25 H.K. Page 22

12 CMOS Latched Comparator Delay V dv gv m = + C L dt gm dv V C gm = L dt g t2 V2 m dt dv C g t V m = L V Latch Delay: C V2 τ D = t2 t = ln g m V gml For gml >> C V2 τ D ln g m V EECS 247 Lecture 2: Data Converters 25 H.K. Page 23 Latch-Only Comparator Problem with latch-only comparator topology: High input-referred offset voltage (as high as mv!) Solution: Use preamplifier to amplify the signal and reduce overall input-referred offset EECS 247 Lecture 2: Data Converters 25 H.K. Page 24

13 Comparator Preamplifier Gain-Speed Tradeoffs Amplifier maximum Gain-Bandwidth product for a given technology, typically a function of maximum device f t fu =unity gain frequency, f = 3 db frequency & τ = settling time fu f = = Apreamp Magnitude For example: A fu GHz v f = = = MHz Apreamp f u =-2MHz τ = =.6nsec Frequency 2π f f f u Tradeoff: To reduce the effect of latch offset high preamp gain desirable Fast comparator low preamp gain EECS 247 Lecture 2: Data Converters 25 H.K. Page 25 Pre-Amplifier Tradeoffs V i+ D o+ A Latch V v i- D o- Example: Preamp Latch offset 5 to mv Preamp DC gain X Preamp input-referred latch offset 5 to mv Input-referred preamplifier offset 2 to mv Overall input-referred offset 5.5 to 4mV Overall input-referred noise reduced by ~7 to 9X ~extra 3-bit resolution! EECS 247 Lecture 2: Data Converters 25 H.K. Page 26

14 CMOS Latched Comparator Including Preamplifier Delay Latch delay found previously: C V2 τ D ln g m V Assuming gain of A for the preamplifier: v C V τ D ln Av g m V in EECS 247 Lecture 2: Data Converters 25 H.K. Page 27 Latched Comparator Including Preamplifier Example V DD M5 M3 M4 M6 Preamplifier gain: g M3 M3 ( VGS Vth ) ( ) M m v = = M 3 M M gm VGS Vth A + V in - M M2 CLK M9 - V o + Comparator delay: τ C A V D ln v gm Vin bias Preamp M7 Latch M8 EECS 247 Lecture 2: Data Converters 25 H.K. Page 28

15 Comparator Dynamic Behavior Comparator eset Comparator Decision CLK T CLK τ delay v OUT EECS 247 Lecture 2: Data Converters 25 H.K. Page 29 Comparator esolution CLK v OUT =mv mv.mv μv Δt = (g m /C).ln(V in /V in2 ) EECS 247 Lecture 2: Data Converters 25 H.K. Page 3

16 Comparator Voltage Transfer Function Non-Idealities V out ε -.5LSB.5LSB V in V Offset V Offset ε Comparator offset voltage Meta-Stable region (output ambiguous) EECS 247 Lecture 2: Data Converters 25 H.K. Page 3 Latched Comparator V i+ A v Latch D o+ V i- D o- Preamp Clock rate esolution Overload recovery Input capacitance (and linearity!) Power dissipation Common-mode rejection Kickback noise EECS 247 Lecture 2: Data Converters 25 H.K. Page 32

17 Comparators Overdrive ecovery Linear model for a single-pole amplifier: U amplification after time t a During reset amplifier settles exponentially to its zero input condition with τ =C Assume Vm maximum input normalized to /2lsb (=) Example: Worst case input/output waveforms Limit output voltage swing by. Passive clamp 2. Active restore 3. Low gain/stage EECS 247 Lecture 2: Data Converters 25 H.K. Page 33 Comparators Overdrive ecovery Limiting Output Clamp Adds parasitic capacitance Active estore After outputs are latched Activate φ & equalize output nodes EECS 247 Lecture 2: Data Converters 25 H.K. Page 34

18 CMOS Comparator Example Flash ADC: 8bits, +-/2LSB fs=5mhz (Vref=3.8V, LSB~5mV) No offset cancellation ef: A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 985, pp EECS 247 Lecture 2: Data Converters 25 H.K. Page 35 Comparator with Auto-Zero ef: I. Mehr and L. Singer, A 5-Msample/s, 6-Bit Nyquist-ate ADC for Disk-Drive ead-channel Applications, JSSC July 999, pp EECS 247 Lecture 2: Data Converters 25 H.K. Page 36

19 Auto-Zero Implementation ef:i. Mehr and L. Singer, A 55-mW, -bit, 4-Msample/s Nyquist-ate CMOS ADC, JSSC March 2, pp EECS 247 Lecture 2: Data Converters 25 H.K. Page 37 Comparator Example Variation on Yukawa latch used w/o preamp No dc power when φ high Good for low resolution ADCs M & M2 added to vary comparator threshold To st order, for W=W2 & W=W2 V th latch = W/W x V where V =V + -V - ef: T. B. Cho and P.. Gray, "A b, 2 Msample/s, 35 mw pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 3, pp , March 995 EECS 247 Lecture 2: Data Converters 25 H.K. Page 38

20 Comparator Example Used in a pipelined ADC with digital correction no offset cancellation Note differential reference M7, M8 operate in triode region Preamp gain ~ Input buffers suppress kick-back ef: S. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC,NO. 6, Dec. 987 EECS 247 Lecture 2: Data Converters 25 H.K. Page 39 Bipolar Comparator Example Used in 8bit 4Ms/s & 6bit 2Gb/s flash ADC Signal amplification during φ high, latch operates when φ low Input buffers suppress kickback & input current Separate ground and supply buses for front-end preamp kick-back noise reduction Preamp Latched Comparator ef: Y. Akazawa, et al., "A 4MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp , February 987 ef: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp , February 988 EECS 247 Lecture 2: Data Converters 25 H.K. Page 4

21 Flash Converter Sources of Error V EF /2 /2. Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 2: Data Converters 25 H.K. Page 4 Typical Flash Output Encoder Binary Output (negative) V DD b3 b2 b b Thermometer to Binary encoder OM b3 b2 b b Output Thermometer code -of-n decoding Final encoding NO OM EECS 247 Lecture 2: Data Converters 25 H.K. Page 42

22 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 b b Correct Output: Erroneous Output: EECS 247 Lecture 2: Data Converters 25 H.K. Page 43 Sparkle Tolerant Encoder Protects against a single sparkle. ef: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 2: Data Converters 25 H.K. Page 44

23 Meta-Stability X Different gates interpret metastable output X differently Correct output: Erroneous output: Solutions: Latches (high power) Gray encoding ef: C. Portmann and T. Meng, Power-Efficient Metastability Error eduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 2: Data Converters 25 H.K. Page 45 Gray Encoding Thermometer Code Gray Binary T T 2 T 3 T 4 T 5 T 6 T 7 G 3 G 2 G B 3 B 2 B G = T T + T T G G = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 2: Data Converters 25 H.K. Page 46