A Low-Power 6-b Integrating-Pipeline Hybrid Analog-to-Digital Converter

Transcription

1 A Low-Power 6-b Integrating-Pipeline Hybrid Analog-to-Digital Converter Quentin Diduck, Martin Margala * Electrical and Computer Engineering Department 526 Computer Studies Bldg., PO Box University of Rochester Rochester, NY 14627, USA {diduck, margala}@ece.rochester.edu Abstract This paper presents a novel low-power 6-bit ADC architecture for Bluetooth transceivers. It utilizes sequentially staged 3-bit integrating converters with interleaved sample and hold circuits. The characteristics of this architecture as well as areas that could lead to even more efficient devices are discussed. The device consumes 5.88mA of current, 14.7mW of power at a sampling rate of 50 MSamples/s, INL and DNL of 0.3 and 0.5LSB, SNR of 36.6dB, THD of 43.75dB, and SFDR of 47.98dB. Our architecture represents a 3.8 times improvement in power consumption or the sampling rate with higher precision compared to previously reported 6-bit implementations. An experimental prototype was simulated in 0.25µm CMOS, with a supply voltage of 2.5 volts. Keywords CMOS Data Converters, Analog-to- Digital, Mixed-Signal, Mobile Communication, Wireless, Low-Power 1. Introduction The work presented here demonstrates a novel ADC architecture for Bluetooth transceivers utilizing integrating converters. By their nature, integrating converters are slow, but tend to have a high degree of accuracy. The main factor effecting accuracy is the linearity of the Ramp signal produced by the integrator. In order to overcome the general slow speed of conversion, two 3-bit stages were pipelined producing an integrating-pipelined hybrid ADC. This device is intended for a low-power low-area mobile communication applications. With power consumption continuing to be of great concern, new architectures that achieve lower power consumption while maintaining a required level of performance are continuously under consideration [1]. It was with these constraints in mind that we developed a pipelined design that achieves the necessary operating speed. Power consumption in this design is at 14.7mW at 50 MSamples/S. This has been achieved by the reduction of analog circuitry that is necessary to resolve all the bits. This device only contains two comparators. This reduction means that there are fewer stages in this pipeline and hence is more energy-efficient [3]. In this device, we combine the best characteristics of an integrating converter, with the best characteristics of a pipelined converter, thus yielding a 6-bit ADC that has exceptionally low-power consumption, without restrictions. 2. Architecture Bit Integrating Converter Stage The integrating converter consists of a traditional integrator that is utilized to generate a sweep signal. During this sweep operation a 3-bit counter operates. When the sweep intercepts the input voltage, a comparator activates the hold line on the counter, resulting in a binary output value of the conversion. While this all seems simple, in practice, there are several challenges to be overcome. The most important thing to develop in this device, is an extremely linear integrator. The best way to achieve this is by utilizing a large capacitor; however, some compromise had to be done in order to reduce the area requirements. Also, since this device is dependent on timing, the delay of the comparator response time has to be taken into account with respect to the counter, particularly if this architecture * corresponding author

2 is operated at its maximum speed limits with the given process. The comparator (Figure 2.) in this design has a 1.2 ns delay Figure 1. Basic circuit of a 3-bit stage. between signal crossing and the activation of the hold line. To compensate for this, one can adjust both the sweep signals position, and the counter clock signal [4]. We chose to adjust the sweep. To determine the exact position the sweep needs to be based upon the comparator delay we perform the following calculations: Given the sweep time is 16ns and the operating voltage range is 0.85 and 1.65: The Sweep rate is: V2 - V Rate = 1 τ 1.65Volts Volts = 16ns = 0.05Volts/ns Knowing that we have a delay of 1.2 ns, to compensate: swee p = V1 + ( delay * rate) = (1.2*0.05) = 0.91volts Figure 2. Block diagram of 6-bit pipelinedintegrating converter. Figure 3. The comparator sets up during the end of the analog cycle, and is triggered when the Input intercepts the Sweep, note the 1.2ns delay in the response of the comparator, and the duty cycle of the analog clock. One should note that the digital circuitry and the analog circuitry are based on two separate clocks. In our implementation, the digital circuitry (the counters) runs at ten times the speed of the analog clock (integrator sweep signal). Also, the duty cycle of the analog clock is based on 4ns high 16ns low ratio, so the clock is high for 2 digital clock signals and low for the remaining 8. Thus, in our case the analog circuitry is running at 50 MHz while the digital is running at 500 MHz. The change in the duty cycle is to optimize for the lowest power consumption by minimizing the reset time of the sweep (no conversion occurs at this time). This duty cycle change however, does affect the sample and hold circuit as it can only sample during the short reset phase of the cycle. 2.2 Design Flexibility This architecture has two main features that enable wide degrees of freedom in the design. The first is the distinctly separate analog and digital nature of the device. Since the analog circuitry runs at a different clock rate than the digital, this enables a variety of bit rates/power levels possibilities during the operation of the device. The second feature is that in the event that more resolution beyond the initial design is required, one can simply add an additional pipeline stage. The nature of having circuits running at two different clock speeds has several advantages, and is the main

3 reason for the flexible nature of this architecture. This device is currently configured to resolve 3 bits per stage, however, with minimal digital circuitry this can be switched dynamically to 2 bits per stage. This would be accompanied by a clock speed reduction through the digital circuitry by a factor of 2. Thus, when only low resolution is required, one would benefit from significant power reduction as well. The ability to shift resolution, on the fly is highly desirable as many applications, such as cell phones only need high-resolution part of the time. It is important to note that only the digital circuitry is required to operate faster, in order to achieve higher resolution. The analog circuitry, which in most ADC s is the primary power consumer, does not need to be increased in speed. The limit to the resolution that is obtainable within a single stage is limited only by how fast of a digital counter can be constructed in the given process. However, the resolutions beyond 4 bits per stage become impractical very quickly as it requires 2 n clock cycles per resolved bit. Each stage of the pipeline is identical, and increasing or decreasing the resolution of this device beyond what can be done by the digital clock, can be as simple as adding another stage to the pipeline. One does have to be aware though that for each additional stage, a Digital to Analog converter has to be added for each prior conversion step. As well the device is limited to the resolution of the sweep signal. Achieving a high resolution sweep requires a larger capacitor, this implies that more power is required to achieve the higher linearity required for more bits. Other concerns such as OpAmp linearity (used for subtraction and gain stage) imply that to achieve more then 9 bits of resolution one would probably have to consider error correction mechanisms. 2.3 Interleaved Sample and Hold and Subtraction Units Since the sample time is so short, to improve accuracy we chose to interleave the two sample and hold circuits[5]. This allows the same sample to go through all the stages of the converter rather then cascading the converters. By doing this, we are increasing the hold time for each sample by a factor of two. Thus, any disturbance that was introduced during the sampling operation has a maximum amount of time to settle before reaching the final conversion stage [6]. The timing of the sample and hold circuits is shown in Figure 4. After the sample is run through a stage in the converter, a subtraction operation is performed on the signal. The value to be subtracted off is provided by a 3-bit DAC that takes the output from the previous stage as input. The subtraction operation starts on the second digital clock cycle of the analog reset time, to ensure proper output level to the sweep-comparator. This process is repeated until the last stage of the conversion is completed, at which point a new sample is taken. Thus, in the case of our device, the sample operation is done over 4ns and held for 36ns with the subtraction operation performed after 20ns. The subtraction unit in this implementation also functions as an 8x multiplier. The multiplication of the signal enables us to use the same sweep signal in both stages. Figure 4. Timing of all Sample and Hold Circuits in relation to the analog clock, note the long hold time relative to the short sampling time. 2.4 Data Pipeline and DAC At each stage of the conversion, the result is determined by a counter. This data is then latched from the counter into a data pipeline. The second stage of the pipeline buffer is responsible for providing the corresponding DAC with the correct digital value for subtraction. As each Analog clock cycle proceeds, the data is moved down the pipeline. At the second stage 3-bits of width are added to the pipeline, as more bits are resolved. Two analog clock cycles are required for the converted data to be at the end of the pipeline. The 3-bit DAC, used in our implementation, is composed of a standard resistive ladder network and utilize transmission gates to control which line is active. For 6-bits of conversion one 3-bit DAC is required for use with the subtraction unit. The timing of the data pipeline is optimized so that the data in the pipeline is advanced fast enough so that the output of the DAC can be utilized by the subtraction unit one digital cycle prior to the sweep comparison cycle. 2.5 Circuit Overview Each of the two Sample and Hold Circuits each contain a subtraction unit. The output of each of the Sample and Hold unit and the subtraction units is fed

4 into the appropriate stage in the pipeline. Signals are directed and controlled with transmission gates, so that signal values between units don t mix. Each stage of the pipeline is composed of a Comparator that takes its input from an integrator (which Figure 5. Digital output of the counter is held once the comparator is tripped, this data is then latched in a buffer circuit as shown in the next figure. Figure 6. Data Pipeline transitions (top) during the first digital clock cycle within the analog pulse. Figure 7. Layout of 6-bit ADC, note the large capacitor required for the sweep (3.5pF). The area of the device is mm 2. generates a sweep signal) and the Sample and Hold Unit or Subtraction Unit, depending on the stage. At the beginning of the sweep cycle the digital counter is started. Once the signal intercepts the sweep, the comparator trips the hold line of the counter. The value in the counter is the digital output of this conversion. This digital information is then latched into a data pipeline so that it can be accessed during the entire analog duty cycle. If this is not the last stage of the conversion, the output value is fed into a DAC, which then feeds into the subtraction unit. This subtracted output is then fed into the next stage of conversion were the entire process repeats. 3. Experimental results The Analog-to-Digital converter delivers 50 MSamples per second with the 6-bit resolution. The INL and DNL values were measured to be 0.3 LSB and 0.5 LSB respectively. The largest source of error was introduced by the DAC s, as switching between DAC outputs caused the largest DNL and INL errors. While the SNR of 36.58dB reflects the inherent accurate nature of the integrating stages. In addition, the power consumption of all building blocks has been measured and is shown in Table 2. The total power consumed by the ADC is 14.7mW. Table I. Vital Statistics Resolution 6 bit Conversion rate 50 MSamples/Sec INL 0.3 LSB DNL -0.1/0.5 LSB THD 43.75dB SFDR 47.98dB SNR 36.58dB Technology 0.25µm Power Dissipation 14.7mW Supply voltage 2.5 V Area 0.745mm x 0.10mm Table II. Current Consumption Sweep generator mA Sample-Hold-Subtract mA DAC mA Comparator 1.4mA Counter 0.31mA Controller 0.583mA Table III. Device Comparisons. Kudoh et al Sumanen et Present al Resolution 6-bit 6-bit 6-bit Conversion 13 Msps 15.36Msps 50Msps Rate INL DNL -0.26/ /0.5 SNR n/a 36dB 36.6dB Power 8.96mW 12mW 14.7mW Area[mm 2 ] 1.37 x x x 0.10 Technology 0.35µm 0.35µm 0.25µm

5 References [1] I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, IEEE J. Solid State Circuits, C-35 (3) (2000) [2] B.-L. Jeon and S.-H. Lee, A 10B 50 MHz 320 mw CMOS A/D Converter For Video Applications, IEEE Trans. on Consumer Electronics, C-45, (1) (1999) Figure 8. Sine wave generated from 250 Samples. Compared to previous implementations shown in Table 3 this design has close to four times higher sampling rate at comparable power and higher signal quality. As well, it can be observed that if mapped to same technology (apply standard scaling rules) our architecture is only 30% area of the Kudoh et al design and 55% area of the Sumanen et al design. 4. Conclusion We have proposed and implemented a novel design of a 6-bit 50Msample/s A/D converter with only 14.7mW of power consumption. This new architecture outperforms comparable designs by up to 3.8 times in performance, with higher signal quality and using significantly smaller area. We have shown that this architecture has a large degree of flexibility in design with only a minimal set of constraints. The potential ability of this design to change bit rate dynamically with only minor modifications demonstrates only some of the uniqueness of this low-power design and its suitability for mobile communication environment. [3] D. Cline and P. Gray, A power optimized 13-b 5- Msample/s pipeline analog-to-digital converter in 1.2µm CMOS, IEEE J. Solid-State Circuits, C-31 (3) (1996) [4] R. C. Taft and M. R. Tursi, A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8V down to 2.2V, IEEE J. Solid State Circuits, C-36 (3) (2001) [5] H. van der Ploeg, G. Hoogzaad, H. A. H. Termeer, M. Verregt, and L. J. Roovers, A 2.5-V 12-b 54-Msample/s 0.25-um CMOS ADC in 1-mm 2 With Mixed-Signal Chopping and Calibration, IEEE J. Solid State Circuits, C-36 (12) (2001) [6] Y.-T. Wang and B. Razavi, An 8-bit 150 MHz CMOS A/D Converter, IEEE J. Solid State Circuits, C-35 (3) (2000) [7] J. Kudoh, T. Matsuura, E. Imaizumi, A 3.2-mA 6-bit A/D converter for a Bluetooth RF transceiver, in Proceedings of ESSCIRC, (2001) [8] L. Sumanen and K. Halonen, A Single-Amplifier 6-Bit CMOS Pipeline A/D Converter for WCDMA Receivers, in Proceedings of the IEEE International Symposium on Circuits and Systems, (1) (2001)