Design and Implementation of a Low Power Successive Approximation ADC. Xin HUANG, Xiao-ning XIN, Jian REN* and Xin-lei CHEN

Transcription

1 2018 International Conference on Mechanical, Electronic and Information Technology (ICMEIT 2018) ISBN: Design and Implementation of a Low Power Successive Approximation ADC Xin HUANG, Xiao-ning XIN, Jian REN* and Xin-lei CHEN 1 Shenyang University of Technology, Shenliao West Road No. 111, Liaoning Province, China *Corresponding author Keywords: Successive approximation, A/D converter, Comparators, Low power consumption. Abstract. This paper designed a low-power successive approximation ADC based on BCD 0.35um standard CMOS technology. The overall static power consumption of the circuit and the use of passive components has been reduced by using switch dynamic comparator and the comparator of the state transition controlled by the clock signal as well as the DAC circuit uses charge redistribution structure. The sample and hold circuit is built into the ADC which further reduce the size of the chip area. The parameters of DNL, INL, SINR and SINAD were verified by MATLAB software. At the same time HSPICE tools were used to simulate the successive approximation ADC. Under the condition of VCC = 3.3V, T = 25, the overall power consumption of the circuit is 1.518mW, and the SNR of the circuit is 50.93dB. Introduction With the semiconductor industry entering the Nano-era, reducing manufacturing costs and increasing the flexibility of chip manufacture by increasing chip integration have become major trends in the development of integrated circuits. More and more higher resolution, lower power analog-digital converter is required in the electromechanical systems, wireless communications, digital audio and other fields. Due to its relative accuracy, simple structure, the circuit is easy to implement and so on, the successive approximation ADC is currently the most widely used ADC structure in several common ADC structures. It has become the mainstream of the research on how to further reduce the cost and power consumption home and abroad [1-2]. The traditional successive approximation ADC uses the structure of combination of self-bias differential amplifier and inverter in its circuit design. As the circuit is a static circuit, this feature determines its power consumption not suitable for low-power chip design [3]. In domestic research, it focuses on the optimization of capacitor array structure as well as reducing the overall layout of the chip in ADC in Qiulu-Liang's research. But it embeds a differential amplifier preamplifier circuit and two dynamic feedback latch circuit in the system, which makes the structure more complex, not easy to achieve, while increasing the overall power consumption of the circuit [4]. Hongming Chen's research focuses on the optimization of the circuit such as the internal capacitance and the conversion channel of the ADC, and the improvement of the conversion rate of the circuit, but it generates the power consumption of more than 4.1mW inevitably [5]. This paper designs a low-power successive approximation analog-to-digital converter for data acquisition system based on the low-power design requirements. A clock-controlled dynamic comparator and a built-in sample and hold circuit are used during the design process that make the entire circuit controlled by the clock, these greatly reduce the static power consumption of the circuit by 62.9%-70% compared to the above designs. At the same time the circuit structure is simple and easy to implement in a chip. The paper discusses the design of each module and system-level circuit in detail, completes the drawing of circuit schematics and the simulation of each parameter. 199

2 Theory and Structure Introduction of the Circuit Comparator Circuit Traditional comparators use an open-loop comparator with an operational amplifier structure, but they have the disadvantages of smaller input common-mode range, larger offset voltage and higher power consumption. Therefore, a higher accuracy, a lower offset voltage and a lower static DC current are needed to ensure a higher conversion accuracy of the ADC. A dynamic comparator controlled by the clock signal is designed based on these requirements [6-8] Figure 1 shows the internal circuit of the comparator. A low-level clock signal is required to initialize the circuit in the initial stage. When the rising edge of the clock arrives, Q5 turns on and the differential input is active. The difference between the input signals is amplified at the output nodes FN and FP. The second stage of the comparator converts the differential output signal into a logic signal as an additional gain stage and an output buffer stage for the circuit. When the clock signal returns to a low level, Q12 and Q15 turn on, the output pulled low, the circuit back to the pre-charge phase. This circuit has the advantage of higher gain and lower power consumption, the static current consumption has reduced by 1.207mA compared to the traditional design, the circuit structure is simple as well as run fast, easy to achieved in a chip. The back-end layout area is small which helps to reduce the cost of the chip. Comparator Circuit Figure 1. The circuit of the comparator. The DAC designed in this paper adds a sample-and-hold circuit based on the traditional charge redistribution structure which simplifies the overall circuit structure [9]. The circuit structure is shown in Figure 2. The capacitance value increases sequentially according to the geometric ratio of 2 to determine the minimum reference capacitance of 5.018fF so that the impact of the load on the DAC can be reduced while the layout area on the basis of the guaranteed circuit can be dropped to the lowest. The initial sequence numbers are from D9 to D0. The analog signal should be connected to the negative plate of the capacitor. At this time the sampling state begins, the total capacitance of the two electrodes of the capacitor can be expressed by Formula (1) 200

3 Figure 2. The structure of DAC. (1) After sampling, the switch signal falls to low level, at this point the circuit is in hold stage, the total amount of charge stored in the capacitor remains unchanged. When the input digital logic changes, the charge at the positive plate of the capacitor changes as well as the DAC output voltage will change. The pulse period of the switching signal is controlled by the SAR circuit to ensure the conversion of ten digital signals in each signal cycle. Overall Circuit Structure The overall circuit diagram of the ADC designed by Cadence is shown in Figure.3. Since the comparator and successive approximation registers work on the rising edge of clk, multiple inverters are used in turn to get a time delay, to ensure the digital output can enter the successive approximation register after the comparison function so as to make sure that the clock signal clk reaches the comparator first. The Q2' terminal of the last bit of the successive approximation register and the reset terminal of the external pin are connected to both sides of the logic gate so that the circuit can use the external input to reset directly before working. After the completion of an A/D conversion, the circuit can use Q2' to reset automatically, while the comparison is back to a low level to generate a reset signal. The output of the NOR gate access to the transmission gate to ensure that the clock signal clk is high when the reset signal works. Figure 3. The ADC overall circuit. 201

4 The control signal PLUSE of the sample-and-hold circuit is connected to the Q1' terminal of the successive approximation register. In the conversion process, PLUSE is low, the sample and hold circuit is in hold stage. When the conversion is completed, PLUSE returns to high, DAC re-sample the input signal to the next cycle of conversion. The MOSFETs diode connection can be used since the reference voltage Vref in the circuit is set as the power voltage. The voltage divider produce 1/2Vref voltage by adjusting the size of MOSFETs to change the dynamic resistance. Simulation of the Overall Circuit Parameters Static Power After the simulation of the static current of the circuit, when the power voltage supplied is 3.3V, the overall circuit simulation results is shown in Figure.4. The static current measured is 0.46mA. The static power consumption of the overall circuit is 1.518mW by calculation. Other Performance Parameters of ADC Figure 4. Static current simulation results. At the same time, the other parameters of ADC are also simulated with Cadence and MATLAB. And the parameters were compared with some ADC performance parameters, the results are shown in Table.1. Table 1. ADC performance comparison. This paper ADC101S021 ADS7817 AD7450 Structure SAR SAR SAR SAR Resolution power voltage 3.3V 3.3V 3.3V 3.3V INL ±1LSB ±0.7LSB ±1LSB ±1LSB DNL ±1LSB ±0.6LSB ±1LSB ±1LSB SINAD dB 61.5dB 71dB 68dB Power consumption 1.526mW 2.34mW 2.3mW 3.75mW Summary This paper designs a low power successive approximation ADC based on CSMC 0.35um standard CMOS technology. The successive approximation ADC uses a clock-controlled dynamic comparator, 202

5 while the sample-and-hold circuit is built into the ADC circuit to reduce the overall power consumption of the circuit greatly. Each part of the circuit design methods and implementation process has been introduced in this paper. The circuit parameters were analyzed through the simulation under Cadence and MATLAB. The power consumption is only 1.518mW under the condition of VCC = 3.3V and T = 25 with the simulation of the HSPICE simulator. Acknowledgement This research was financially supported by the National Science Foundation (LGD ). References [1] Wei-jia Xu, Qin Shi, Jun-jie Tian. A High Accuracy Comparator Circuit Applied to 10 - bit SAR ADC, J. Microcomputer and Application. 2017, 36(04): [2] Hai Huang, Low-voltage, low-power, high-precision successive approximation ADC design, D. Chendu City, University of Electronic Science and Technology,2013. [3] Jun-shi Qiao, Dong-mei LI, Low Power Consumption Successive Approximation ADC Design Based on Switching Amplifier, J. Semiconductor Technology. 2008, (03): [4] Qiu-lu Liang, Design and Research of 10-bit Precision and Low Power SAR ADC, D. Beijing Jiaotong University, [5] Hong-ming Chen, Sheng-rui Xu, Yu-guang Zeng, A 10-Bit 8-Channel 1MS/s Successive Approximation to AD Converter with Capacitive Arrays, J. China Integrated Circuit, 2013, 22(10): [6] Sarafi S, Hadidi K, Aain A, et al. 100 MS/s, 10-BIT ADC using pipelined successive approximation. Journal of Circuits, J. Systems & Computers. 2014; 23(5):1-17. [7] Jun-feng Gao, Guang-jun Li, Qiang Liu. High-speed low-power common-mode insensitive dynamic comparator. Electronics Letters. 2015; 51(2): [8] Liang-bo Xu, Jian Shi, Jia-xin Li, et al. Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs. Electronics Letters. 2015; 51(6): [9] Ren S, Emmert J. Successive approximation pipelined ADC with one clock cycle conversion rate. Electronics Letters. 2012; 48(20):