The need for Data Converters

Transcription

1 The need for Data Converters ANALOG SIGNAL (Speech, Images, Sensors, Radar, etc.) PRE-PROCESSING (Filtering and analog to digital conversion) DIGITAL PROCESSOR (Microprocessor) POST-PROCESSING (Digital to analog conversion and filtering) ANALOG OUTPUT SIGNAL (Actuators, antennas, etc.) CONTROL ANALOG A/D DIGITAL D/A ANALOG In many applications, performance is critically limited by the A/D and D/A performance

2 D/A Block Diagram Voltage Reference V REF Scaling DVREF Output vout = Network Amplifier KDV REF Binary Switches b b 2 b 3 b N Figure.-3 b is the most significant bit (MSB) The MSB is the bit that has the most (largest) influence on the analog output bn is the least significant bit (LSB) The LSB is the bit that has the least (smallest) influence on the analog output

3 Where the A/D is in the System Input(s) Preprocessing Anti-Aliasing Filter (Cont-t) Analog to Digital Converter Sample and Hold Digital Processor Sometimes the Digital Processor does part of the Conversion

4 Types of A/D Converters Conversion Rate Nyquist ADCs Oversampled ADCs Slow Integrating (Serial) Very high resolution >4 bits Medium Fast Successive Approximation -bit Pipeline Algorithmic Flash Multiple-bit Pipeline Folding and interpolating Moderate resolution > bits Low resolution > 6 bits

5 Ideal input-output characteristics of a 3-bit DAC. Analog Output Value Normalized to VREF LSB Infinite Resolution Vertical Shifted. Digital Input Code Fig..-4

6 D/A Definitions Resolution of the DAC is equal to the number of bits in the applied digital input word. Quantization Noise is the inherent uncertainty in digitizing an analog value with a finite resolution converter. Quantization Noise LSB.5LSB LSB -.5LSB Digital Input Code Fig..-5

7 A/D Definitions The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits (ENOB) of the ADC are the same as for the DAC Resolution of the ADC is the smallest analog change that can be distinguished by an ADC. Quantization Noise is the ±.5LSB uncertainty between the infinite resolution characteristic and the actual characteristic.

8 Ideal inputoutput characteristics of a 3-bit ADC Digital Output Code LSB Infinite Resolution Ideal 3-bit LSB Quantization Noise LSBs Analog Input Value Normalized to V REF Figure.5-3 Ideal input-output characteristics of a 3-bit ADC. v in V REF

9 Table Digital Output Codes used for ADCs Types of Encodings in A/Ds Decimal Binary Thermometer Gray Two s Complement

10 Testing of D/A Converters Digital Word Input (N+2 bits) N-bit DAC under test V out ADC with more resolution than DAC (N+2 bits) ADC Output Digital Subtractor (N+2 bits) Digital Error Output (N+2 bits) Fig..-9 Sweep the digital input word from... to... The ADC should have more resolution by at least 2 bits and be more accurate than the errors of the DAC INL will show up in the output as the presence of s in any bit. If there is a in the Nth bit, the INL is greater than ±.5LSB DNL will show up as a change between each successive digital error output. The bits which are greater than N in the digital error output can be used to resolve the errors to less than ±.5LSB

11 Testing of an A/D Converter V in N-bit ADC under test Digital Word Output (N bits) DAC with more resolution than ADC (N+2 bits) V in ' - + Q n = V in -V in ' Fig..5-7 The ideal value of Qn should be within ±.5LSB Can measure: Offset error = constant shift above or below the LSB line Gain error = contant increase or decrease of the sawtooth plot as Vin is increased INL and DNL

12 Offset and Gain Errors in D/As An offset error is a constant difference between the actual finite resolution characteristic and the infinite resolution characteristic measured at any vertical jump. Analog Output Value Normalized to VREF 7/ 6/ Actual Analog Output Value Normalized to VREF 5/ Offset 4/ Error Infinite 3/ Resolution 2/ Ideal 3-bit / Resolution Digital Input Code Offset Error in a 3-bit DAC 7/ 6/ 5/ Gain Error Actual 4/ Infinite 3/ Resolution 2/ Ideal 3-bit / Resolution Digital Input Code Gain Error in a 3-bit DAC Fig..-6 A gain error is the difference between the slope of an actual finite resolution and an infinite resolution characteristic measured at the right-most vertical jump.

13 Offset and Gain Errors in A/Ds Digital Output Code Ideal Offset =.5 LSBs v in V REF Digital Output Code Gain Error =.5LSBs Ideal v in V REF (a.) (b.) Figure (a.) Example of offset error for a 3-bit ADC. (b.) Example of gain Offset error for Error a 3-bit is the ADC. horizontal difference between the ideal finite resolution characteristic and actual finite resolution characteristic Actual Gain Error is the horizontal difference between the ideal finite resolution characteristic and actual finite resolution characteristic which is proportional to the analog input voltage

14 Monotonicity Digital Output Code Actual DNL = -2 LSB Ideal Fig..5-6L v in V REF

15 INL and DNL for a D/A Integral Nonlinearity (INL) is the maximum difference between the actual finite resolution characteristic & the ideal finite resolution characteristic measured vertically (% or LSB). Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels measured at each vertical jump (% or LSB). Analog Output Voltage Infinite Resolution LSB DNL 6 5 Nonmonotonicity - LSB INL LSB INL A LSB DNL 2 Ideal 3-bit Actual 3-bit Digital Input Code Fig..-7

16 Example of INL and DNL of a Nonideal 4- bit DAC Analog Output (Normalized to Full Scale) 5/6 4/ /6 /6 /6 9/6 /6 7/6 6/6 5/6 4/6 3/6 2/6 +.5 LSB INL Ideal 4-bit DAC -2 LSB DNL -2 LSB DNL -.5 LSB INL +.5 LSB DNL Actual 4-bit DAC /6 /6 b b 2 b 3 b 4 Digital Input Code Fig..-

17 INL and DNL of a 3-bit ADC Digital Output Code Actual INL = +LSB DNL = + LSB 2 3 Ideal 4 5 DNL = -2 LSB 6 INL = -2LSB 7 v in V REF Fig..5-6DL

18 INL and DNL in A/D converters Ideal Digital Output Code INL = -LSB INL = +LSB DNL = +LSB Actual DNL = LSB v in V REF Example of INL and DNL for a 3-bit ADC.) Fig..5-5

19 Dynamic Testing of D/A Converters Digital Pattern Generator (N bits) V REF N-bit DAC under test V out V out t Distortion Analyzer Vout(j ) fsig Noise floor due to nonlinearities Spectral Output Note that the noise contribution of VREF must be less than the noise floor due to nonlinearities. Digital input pattern is selected to have a fundamental frequency which has a magnitude of at least 6N db above its harmonics. Clock Fig..- Length of the digital sequence determines the spectral purity of the fundamental frequency. All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of the fundamental frequency The THD can be used to determine the SNR db range between the magnitude of the fundamental and the THD. This SNR should be at least 6N db to have an INL of less than ±.5LSB for an ENOB of N-bits. If the period of the digital pattern is increased, the frequency dependence of INL can be measured.