Low- Power Third- Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications

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1 C. Della Fiore, F. Maloberti, P. Malcovati: "Low-Power Third-Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications"; Ph. D. Research in Microelectronics and Electronics, PRIME 2006, Otranto, June 2006, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 Low Power,Third Order E/A Modulator with Cross- Coupled Paths for WCDMA Applications Cristina Della Fiore, Franco Maloberti Dept. of Electronic Engineering University of Pavia Pavia, Italy franco.maloberti(kunipv.it Abstract-This architecture realizes a third order shaping of the quantization error starting from a 3-Path Sigma-Delta architecture. Each path is made by a first order modulator and the Noise Transfer Function (NTF) is obtained by crosscoupling the quantization errors of the three paths to obtain the missing terms in the NTF. Simulation results meeting the WCDMA requirements obtain signal bandwidth of 1.92 MHz with an over-sampling-ratio (OSR) of 10 and an effective number of bits (ENOB) equal to 10. The resulting power consumption is lower than 2.8 mw. I. INTRODUCTION Analog to digital converters using low-voltage, low power, and with medium-accuracy are important elements in new generation handset. The requests of power consumption, over-sampling-ratio (OSR), and digital processing make sigma-delta modulators one of the preferred solutions for integrated applications. However, using high order modulators involves an increasing power for obtain good resolution (or SNR). On another hand the use of low-order modulators augments the OSR requirements or the number of quantization levels leading to demanding requirement of fast settling at high operating frequencies. According to these two opposite design strategies it is necessary to identify the best trade-off for the required resolution signal bandwidth and high robustness to circuit non-idealities. According to previous research [1] WCDMA specifications require using third order architecture that require using three op-amps. This paper also obtains a third order AL noise shaping but uses a clock frequency that is 1/3 the one used in the conventional counterpart. The used scheme has a less favorable feedback factor but obtains more thanlo-bit resolution and 1.92 MHz signal bandwidth using OSR=10, an operating sampling frequency 12.9 MHz and a power consumption of only 4.3 mw. The results are obtained thanks to a new architecture based on a 3-path AL scheme with cross-coupled branches that realizes the required response in a power effective way. Piero Malcovati Dept. of Electrical Engineering University of Pavia Pavia, Italy piero.malcovati@unipv.it II. DESIGN CONSIDERATIONS The architectures of WCDMA systems require at least 10-bit with signal bandwidth equal to 1.92 MHz and minimum power consumption. Since the use of OSR=10 and a 4 bits quantization leads to a third order -A scheme it is necessary using three op-amps and 15 comparators. In addition there is the DEM and the digital decimator. The power consumption is given by tot 3Pop-amp +4Scomp + Pdig (1) Assuming that using quantization with more than 4-bit is unpractical for the limits established by an effective DEM, the use of a second order modulator would lead to OSR= 18 for obtaining the same SNR. The power of the op-amp, in first approximation, increases proportionally to the clock frequency. Therefore, the power of two op-amps and 15 comparators running at a 1.8 x speed would lead to more power consumed in the analog section. A simpler decimation filter whose first stage runs at a higher frequency almost obtains equal power consumption in the digital section. The above considerations confirms that, for conventional architectures, the best trade-off is the one used by [1]. Therefore, for lower FoM it is necessary to study nonconventional solutions. WCDMA architectures use a large signal bandwidth but require low resolution. Therefore, the modulator can use very small sampling capacitances and op-amp with a relatively low gain as the thermal noise and the error caused by a dumped integrator are acceptable limits. Moreover, for parallel architectures, like the one used here, the required matching between paths is relatively low. III. PROPOSED METHOD As mentioned before the basic scheme of the modulator is an N-path AL scheme, As known [3] the N-path /06/$20.00 C2006 IEEE 133

3 transformation of a low-pass architecture realizes a z,zn transformation. For AL modulator the transformation holds for both STF and NTF. As known, the NTF of a third-order AL modulator is (1 _ 1)3. The simple below transformation NTF(z) = (I z =(z_ 3)Z3z '±3z 2 shows that we can distinguish between (I-z-3) and a residual term (-3z-'+3z-2). The first term is the noise transfer function of a first order AL modulator passed through the transformation z- z3. Therefore, it is possible to obtain the first part of the NTF by using the 3-path arrangement of first order AL schemes. Two extra branches per path as shown in Fig. 1 obtain the missing terms. The output of the modulator provides, in addition to the digital output the quantization error of the path. The intrinsic delay between paths gives rise to the delays and the multiplication by 3 or -3 realizes the required coefficients. In multiplied by the STF. The superposition of the three paths gives rise to ei)out=i(i-z )-3ei zstf+3eiz 2STF (6) where (i+l) and (1+2) are module 3 additions. 2) Observe that the multiplexing divide by 3 the power of each quantization error. Therefore, if STF=1 the noise at the output is equivalent to a single quantizer with third order shaping. IV. CLOCK TIMING The clock used in a switched capacitor integrator uses two phases with equal duration one for sampling and the other for the signal injection. Excluding the cases of double sampling or op-amp sharing, the op-amp operates during only one of the two phases. Consequently, the switched input structure is charged or discharged in a passive manner during one of the two phases. Since the only on-resistance of the switches limits the passive time constant, while the frequency limitation of the op-amp must be accounted for in the active phase, the time required for the passive phase can be lower than the other phase, thus relaxing the bandwidth and slew rate requirements of the op-amp. The outlined strategy is not used in conventional SC integrator as it would be required using a faster phase an extra control of switches. On the contrary, the method is naturally usable with N-path structures. Fig. 2 shows the clocks used in a conventional SC integrator and the phases required by a 3-path architecture. Since the sampling is performed using a T period (T/2 is also possible) the remaining 2T is for the active integration. Therefore, the time available for the op-amp settling is 4 times (or 5 times) larger than the one of the conventional integrator. Figure 1. Block diagram of the presented architecture. The output of each first order -A modulator is that, thanks to the z- Y-=Xi+(i(- z) ( Yi=Xi+ci z-3 transformation becomes -z-3 (4). Because of the used delays and the decimation by 3 the input is X ±=X2 z-1 + X -2 (5) Since the quantization error of a path is summed with the input of other paths its contribution at the output is (3) Conventional Temporization Proposed Temporization Figure 2. path path 2 path 3 Chosen temporization. V. OP-AMP SPEED REQUIREMENTS The speed of the op-amp (bandwidth and slew-rate) depends on the time allowed for the active phase and the feedback factor of the integrating network. If the gain of the integrator is 1 the feedback factor for the conventional scheme is 1/2. The additional branches gives rise (Fig. 3) to an extra capacitive load at the input that reduces the feedback factor to 1/8. The effect seems to require a wider bandwidth 134

4 and, by turns, a larger power consumption. The below shows that, on the contrary, the necessary power is reduced. Cu 1 it is necessary to have the second pole at a given distance from (OTi A0oo1. At angular frequencies much larger than (02 the second pole determines the phase margin (Qo)) 2 () =-- arctg-) (11) Cu _.\T kf -- 3Cu4 SIT' --- 3Ca _-T kf " _ K W Figure 3. Feedback networks in a conventional architecture (up) and in the proposed one (down). An input step Vin at t=0 gives rise to op-amp output transient that, accounting for the dominant pole only, is an exponential ::::: thv ise 1 8 (7) In order to obtain a phase margin 4=600 at (0 it is necessary to have = ) 2 (12) Therefore, for the two cases the positions of the second pole that ensures 4=60' at PfT are c2 = CT-3/2 for conventional case and (02 = C 8 for this architecture. Very low voltage schemes do not have room for cascode configurations and must obtain the required gain with the cascade of two gain stages. Therefore COT = gm]l C 3) where the time constant -c is coc= (c1gm2cc 2 CI C2 + (Cl + C2 )CC (14) 1 ( 2ir/8fT The time available for settling -cs must be a suitable number y of time constant c. For the two circuits of Fig. 3, being -s,=t/2 and Cs2=T/2, with feedback factors P3=1/2 and 12=1/8 respectively, it results ft] = zrt ft2 Y ;TT Therefore, both operational amplifiers need the same unity gain frequency. As known, for a given feedback factor it is necessary to ensure a suitable phase margin at PfT. Therefore, for a two poles the open loop gain ;TT 8) where gmi and gm2 are the transconductances of the two stages, Cl and C2 are their capacitive loads and Cc is the compensation capacitor. Since in general Cl<<C2 and C2ZCc, combining the above equations the compensation capacitor is estimated by (9) A(j)= AO (10) j1 J2 CC -C2 C2 gml C )T 9. 2 The use of the above equation for estimating the compensation capacitance in the conventional and this design gives rise to c= C2 13 g for the conventional case and 2 gm2 C = C 3 gm, in the presented architecture. 8 gm2 Therefore, the lower feedback factor enables using a smaller compensation capacitance. (15) 135

5 The above study shows that for the conventional and this design it is necessary to have the same ft, but for this design it si possible to use a smaller C,. Since ft=g,./(27cc,) a scaling of Cc enable a scaling of gm. Since for transistors in saturation gm (VGS -VTH )2 (16) Popamp= 560 ptw Pflash= 190 ptw Pkelvin div= 70 ptw Pdigital logic:= 288 iw Pphase_generator= 190 i\w That gives rise to an estimated total power Ptotal as low as to 2.4 mw. 3 (Popamp/2+Pflash+Pdigital_logic)+Pkelvin_div+Pphase_generator and the overdrive is almost the same for practical designs, reducing the transconductance diminishes the bias current and determines a power consumption reduction. In this design the improvement can be up to a factor 4. VI. BUILDING BLOCKS A. Operational Amplifier The low voltage supply (1.2 V) op-amp is a two stages scheme with AB class second similar to the one used in [1] for enhancing high slew rate also with low power consumption. The common mode feedback is a conventional switched capacitor scheme. Simulation result with a 0.18m technology and 560 ptw power consumption give Ao=83 db, an extrapolated ft=360 MHz being the phase margin equal to only 30. Since the feedback factor of 1/8 and the integration period is 2T the bandwidth that determines the speed limitations is 160 MHz; at that frequency the phase margin is 63. Since the clock in each path is 12.9 MHz the margin factor is y=12. B. Flash ADC The flash ADC uses 15 comparators whose input capacitance load the op-amp and give rise to some kick back. In order to reduce the two effects, since the op-amp is fully differential, the design uses single ended comparators half connected to the positive output and half plus one to the negative output. The strategy halves the capacitive and transforms into a common mode signal the kick back. The power consumption of each comparator is about 12 ptw. C. DAC A digital logic combines the output of the three paths for generating the control of the DACs realized by a resistive divider that requires 93 vta. Since the minimum unity capacitance that can be designed with the used technology is 110 ff. The use of an array of 15 capacitances would lead to a sampling capacitance of 1.65 pf, 2.5 times larger than the one used in this design. VII. SIMULATION RESULTS The proposed architecture has been simulated at the behavioral and the transistor level. Fig. 4 shows, for example, verify that the Power Spectral Density (PSD) at the transistor level match well the behavioral results.. The power consumption of the building blocks is Figure 4. PSD of the third order cross-coupled -A modulator. Fig. 5 compares the Dynamic Range (DR) of the presented architecture and the results given in [1]. The dynamic range and the peak SNR are almost the same or better but the power consumption is less than 50%. Proposed Architecture 67dB State of the Art ed Amplltud4 Figure 5. Comparison between the Dynamic Ranges of the two YA Modulators. 64 db VIII. REFERENCES [1] A. Dezzani, E. Andre, "A 1.2-V Dual-Mode WCDMA/GPRS YA Modulator", STMicroelectronic, Central R&D, Crolles, France, ISSCC [2] F.Maloberti, "Analog Design for CMOS VLSI Systems", (Kluwer Academic Publishers). [3] F. Maloberti, F. Francesconi, P. Malcovati, O.J.A.P. Nys, "Design Consideration on Low-Voltage Low-Power Data-Converters", IEEE Trans. Circuits Syst. I, vol. 42, NO. I 1, November