Two- Path Delay Line Based Quadrature Band- Pass ΣΔ Modulator

Transcription

1 Y.B. Nithin Kumar, E. Bonizzoni, A. Patra, F. Maloberti: "TwoPath Delay Line Based Quadrature BandPass ΣΔ Modulator"; IEEJ International Analog VLSI Workshop, Bali, 2 4 November 211, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 Decimation and DSP Quadrature filter Proceedings of the 211 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 24, 211 TwoPath Delay Line Based Quadrature BandPass Σ Modulator Nithin Kumar Y.B., Edoardo Bonizzoni, Amit Patra, and Franco Maloberti Department of Electronics, University of Pavia, Via Ferrata, Pavia ITALY Department of Electrical and Electronics, IIT Kharagpur INDIA nithin.shastri@gmail.com, edoardo.bonizzoni@unipv.it, amit.patra@ieee.org, franco.maloberti@unipv.it Abstract This paper presents a new concept for an effective quadrature bandpass Σ modulator and discusses the high level implementation for a third order twopath scheme based on delay line. The methodology uses an architecture which locks IF frequencies to the sampling frequency. Robustness of the structure against the mismatch is analyzed. Simulations at the behavioural level verify the architecture implementation which uses a novel switched capacitor scheme. Index Terms AnalogtoDigital conversion, bandpass Σ modulation, complex filters. RF amplifier and filter Fig. 1. R Q 9 Quadrature sigma delta modulator Generalized quadrature receiver architecture. I. Introduction Rapid developments in semiconductor technology support miniaturization of integrated communication devices with low power. These inexpensive devices known as Wireless Sensor Network (WSN) can be used to sense, compute and transmit the valuable information for applications in the field of space, buildings, home, transportation, biometrics, healthcare etc. The main advantage of WSN lies in the ability of self configuration, which can be monitored remotely. Unlimited potential of WSN resulted in different protocols depending on the application [1]. One of the fast evolving WSN applications is in healthcare sector. Wireless Body Area Network (WBAN) is a special purpose WSN that operates autonomously for medical monitoring, which may be planted inside the body as well as outside. By using a WBAN system, hospital can monitor blood pressure, blood glucose, ECG, body temperature etc. of a patient without affecting its normal life. A typical WBAN system consists of microprocessor, data storage, sensors, ADC, transceiver and an energy source [2]. The main requirement of sensor network is to operate at low power. ADC is one of the main power hungry blocks in the receiver architecture. Considering spectral efficiency and low power, the best candidate for low power architecture is quadrature bandpass Σ modulator [3]. The generalized quadrature receiver architecture is shown in Fig. 1. Unlike a real bandpass Σ modulators, the zeros of quadrature noise transfer function (NTF) do not need to be complex conjugate. Zeros can be distributed around the intermediate frequency (IF) from DC to f S /2, being f S the sampling frequency. Thus, it provides twice the noise shaping with respect to real bandpass Σ modulators [3]. However, quadrature architectures are vulnerable to path mismatches between I and Q paths. As a result, quantization noise in the image band is folded into signal band thus degrading the performance. A possible solution would be to place one of the zeros of quadrature NTF at image location [3], [4] or selecting signal band near to DC such that quantization noise at image location is still shaped [5]. This paper extends the study reported in [6] and presents an architectural solution and its implementation for third order quadrature Σ modulator. The circuit operates at IF = 5 f N /6, which is near to f N = f S /2, which relaxes image requirements. This work presents a new delay line based two path time interleaved modulator and its switched capacitors implementation. The circuit has been simulated at the behavioural level with non ideal blocks and achieves more than 7 db SNR for 1 khz bandwidth and more than 55 db SNR for 2.5 MHz bandwidth with clock frequency of 2 MHz. The following Section reviews the basic scheme for a delay based second order quadrature modulator. It also verifies signaltonoise ratio (SNR) as a function of bandwidth for WBAN systems requirements. Synthesis of third order NTF with realization techniques and robustness against mismatches analysis are discussed in Section III. Section IV presents a novel third order twopath modulator scheme while Section V illustrates an efficient switched capacitor implementation. Finally, Section VI draws some conclusions. II. Basic Second Order Architecture and Limitations Consider one of the possible NTFs [6] with zeros on the unity circle at the positions e jφ i, i = 1, n. The NTF is NT F = n 1 [ 1 e jφ ] i = 1 a 1 z z e j ni φ i z n (1) 65

3 Proceedings of the 211 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 24, 211 X R Y R X R X R1 Y R1 Y R )k1(ε q )k2(ε q (ε r ) )k2(ε q )k2(ε q (ε q ) [k((ε r )(ε q ) (ε r ) [k((ε r )(ε q ) (ε q ) X Q X Q1 Y Q1 Y Q X Q Y Q Fig. 4. Third order quadrature bandpass Σ architecture (IF = 5 f N /6) for NTF = 1 z 1 (k 1 jk 2 ) z 2 (k 2 jk 1 ) jz 3. Fig. 2. Second order quadrature bandpass Σ architecture for NTF = 1 z 1 k(1 j) jz 2 with IF = 3 f N /4. 2 PSD of the 3rd order Sigma Delta Modulator SNR [db] SNR vs Bandwidth of the 2nd order Sigma Delta Modulator PSD of the 2nd order Sigma Delta Modulator x (bw/fs) Fig. 5. PSD of the 5 f N /6IF third order quadrature bandpass modulator for k 1 = and k 2 = using the architecture of Fig. 4. Fig. 3. Simulated SNR as a function of the signal bandwidth. The inset shows the detail of the signal band. With zeros on the unity circle, the last term has modulus one and phase that is the addition of the phase of all the zeros. The method developed [6] and in this paper limits the zero positioning to situations for which n i φ i =, π/2, π, 3π/2 or correspondingly the last coefficient of (1) is 1, j, 1 or j. The reason for this choice is that the first and the last term can be implemented with minimal number of hardware. For n = 2, it is possible to implement following NTF as proposed in [6]. NT F = 1 z 1 k(1 j) jz 2 (2) In this work the specification of SNR for 1 khz bandwidth is more than 65 db and more than 5 db for 2.5 MHz bandwidth. However, the resulting k = with sampling frequency of 2 MHz just satisfies medium specification request. Fig. 2 shows the block diagram that implements the above NTF. SNR as a function of the bandwidth is given in Fig. 3. The inset shows the zoomed region of the signal band. Moreover, the accuracy of the components used to realize the coefficient k critically affects the SNR. Possible mismatch causes a shift in the zeros but they will remain in the unit circle with center frequency still locked to sampling frequency. Nevertheless, a shift of zeros augments the noise level in the signal band and makes this solution not affordable for the considered specifications. III. Third Order Quadrature BandPass Σ Modulator It is more effective to have an extra zero at the center of the signal band or near to the IF in order to satisfy higher SNR for lower bandwidth requirement. Consider the architecture shown in Fig. 4. It is the building scheme of the final design. Supposing to use coefficients k 1 = and k 2 =, i.e without injection of quantization error between delays, it realizes NTF = 1 ( j)z 3 (3) Note that in the signal band of interest around IF = 5 f N /6 there is only one zero and other two zeros located at f N /6 and f N /2 are not useful in enhancing the SNR. The simulated output spectrum is given in Fig. 5. In order to shift two of the zeros towards the signal band, we inject k 1 = and k 2 = 1.5 on the intermediate points of Fig. 4. This moves zeros at IF = 5 f N /6. The NTF is NTF = 1 z 1 (k 1 ( j)k 2 ) z 2 (k 2 ( j)k 1 ) ( j)z 3 (4) Imaginary Part Real Part Fig. 6. Location of the complex zeros for k 1 = 2.5 and k 2 =

4 Proceedings of the 211 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 24, 211 PSD of the 3rd order Sigma Delta Modulator Samples Fig. 7. PSD of the 5 f N /6IF third order quadrature bandpass modulator for k 1 = 2.5 and k 2 = using the architecture of Fig SNR[dB] Fig. 9. Histogram plot for mismatch analysis with 5% variance. SNR [db] SNR vs Bandwidth of 3rd order Sigma Delta Modulator 5 1 PSD of the 3rd order Sigma Delta Modulator x (bw/fs) Fig. 8. SNR versus Bandwidth plot of a third order quadrature bandpass Σ architecture. Inset shows zoomed region of signal band. SNR [db] k Fig. 1. 3D mismatch analysis plot showing SNR versus variation in coefficients k 1 and k 2. k Distributing the zeros around desired IF. Fig. 6 shows the zeros placement for k 1 = 2.5 and k 2 = The simulated spectrum is given in Fig. 7 while Fig. 8 shows SNR as a function of bandwidth. The performance mainly depends on the notch at IF = 5 f N /6 (inset diagram shows the zoomed region of the signal band). The SNR obviously depends on the accuracy of the injection parameters k 1 and k 2. Fig. 9 shows the histogram plot (3 samples) for the mismatch variation in coefficients k 1 and k 2 with standard deviation SD = Notice that more than 9% of the samples results in a SNR higher than 6 db for a bandwidth of 2.5 MHz. It is also worth to analyze the sensitivity of the modulator with respect to coefficients variation. The 3D plot shown in Fig. 1 confirms the robustness of the architecture. IV. Delay Line Based Two Path Third Order Modulator For the circuit implementation, this paper uses a twopath scheme. The solution costs an increased hardware but saves significant power (nearly 5%) [7]. There are architectures available in the literature, which use multipath scheme for lowpass [7] or bandpass modulator [8], [9], but all realizations are integrator based solution. The block diagram of Fig. 11 shows the twopath quadrature modulator. Each modulator operates at half the sampling frequency ( f S /2). Let us now consider again the architecture shown in Fig. 4. It uses three delay based cross coupled quadrature filters. We duplicate the core of the scheme of Fig. 4 for both even and odd paths to obtain circuits dedicated to the generation of Y Q1e, Y R1e, Y Q1o, and Y R1o (shown for Y Q1e and Y R1e in Fig. 12). Quadrature input signals X R1 and X Q1 result in filtered quadrature outputs Y R1 and Y Q1. Notice that goes through six delays to reach the output Y Q1e. Similarly, input propagates through six delays to reach the output Y R1e. A suitable transformation gives rise to schemes with double delays only. Fig. 13 shows the final even path scheme of the filter after rearranging the blocks. Odd path has similar block rearrangement. All the injection of the quantization error are rearranged such that they will foresee at least one single delay, necessary for the quantization. The obtained scheme requires 12 delay blocks that run at f S /2. The circuit of Fig. 4 uses 6 delays running at f S. Since reducing by 2 the clock frequency diminishes the power of active elements by 4, the twopath architecture reduces by 2 the expected consumed power. X R X Q X Re X Qe X Ro X Qo ΣΔ f s /2 ΣΔ Fig. 11. Generalized two path quadrature bandpass modulator. Σ is the scheme of Fig. 4. Y Re Y Qe Y Ro Y Qo Y R Y Q 67

5 Proceedings of the 211 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 24, 211 PSD of 3rd order Sigma Delta Modulator with path mismatch )k1(ε q )k2(ε q )k2(ε q )k2(ε q 5 Y Q1e 1 Y R1e )k1(ε q )k2(ε q )k2(ε q )k2(ε q Fig. 14. Simulated output spectrum of the twopath scheme with nominal mismatches. Fig. 12. Doubling the core of the scheme of Fig. 4. V in C V out )k1(ε q )k2(ε q z 2 )k2(ε q )k2(ε q z 2 z 2 Y Q1e Fig. 15. Fliparound technique for single delay realization. z 2 z 2 Y R1e )k1(ε q )k2(ε q Fig. 13. z2 )k2(ε q )k2(ε q Double delay based architecture after block reduction. The possible mismatch between the even and odd paths is not problematic because it generates tones at f S /4. Mismatches between I and Q paths give rise to tones at the image position as it happens for any quadrature solutions. Simulation results with mismatches lead to the spectrum of Fig. 14. The proposed method possibly allows us to add an extra zero at the image position to improve the image rejection. V. Switched Capacitor Implementation The architecture implementation uses switched capacitor. Fliparound method is chosen over the conventional methodology to reduce the slew rate problem as it requires only one capacitor for realization. Capacitor is already charged during the sampling phase, hence opamp performance can be relaxed. Because of the bandpass operation, the scheme is insensitive to offset of the opamps. Fig. 15 with its clocking scheme realizes a single delay. During phase φ 1, input voltage V in is sampled onto capacitor C and during the other phase, φ 2, capacitor is connected between output of the operational amplifier (opamp) V out and input negative terminal of the opamp. The scheme of Fig. 15 operates during phase φ 2 only. The complementary phase could be possibly used for offset cancellation. Since offset is not an issue, we use the solution reported in each stage of Fig. 16 to further relax the opamp specifications. During clock period 1, capacitor C is in the sampling mode, C is in the wait mode, and C is in the fliparound mode. During clock period 2, C goes in the wait mode, C flips around and C samples the new input. Similarly for the clock period 3. The solution is such that a capacitor remains in feedback around the opamp for an entire clock period. The proposed solution has been simulated at the behavioural level in Cadence environment and results totally confirm what achieved in MatlabSimulink TM. Both simulations include mismatches and opamps non idealities (finite gain, bandwidth and slewrate). VI. Conclusion This work extensively studied a quadrature bandpass Σ modulator based on a new design concept. The IF, locked to the sampling frequency, can be located in a limited number of fractional values of f S. The feature grants the benefit of an IF programmability just by changing f S. The architecture is robust against mismatches that just move NTF zeros whose 68

6 () Proceedings of the 211 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 24, 211 2T 2T 2T C I C I C I VR in C II I 2 C II I 2 C II I 2 VR out I 2 I 2 I 2 C III C III C III T & I 2 & & Fig. 16. Six delays implementation based on fliparound cell and driving phases. position, within limits, remains on the unity circle. The zero at IF is mismatch insensitive. Architectural details and circuit solutions are provided. The effectiveness of the proposed scheme was proved by simulations at the behavioural level. References [1] David Culler, Deborah Estrin and Mani Srivastava, Overview of Sensor Networks, IEEE Computer Society, pp. 4149, August 24. [2] ShihLun Chen, HoYin Lee, ChiungAn Chen, HongYi Hung and ChingHsing Luo, Wireless Body Sensor Network with Adaptive Low Power Design for Biometrics and Healthcare Applications, IEEE Systems Journal, vol. 3, no. 4, pp , Dec. 29. [3] S. A. Jantzi, K. W. Martin, and A. S. Sedra, Quadrature bandpass Σ modulation for digital radio, IEEE Journal of SolidState Circuits, vol. 32, no. 12, pp , Dec [4] R. Schreier, N. Abaskharoun, H. Shibata, D. Paterson, S. Rose, I. Mehr, Luu, A 375mW Quadrature Bandpass Σ ADC With 8.5MHz BW and 9dB DR at 44 MHz, IEEE Journal of SolidState Circuits, vol. 41, no. 12, pp , Nov. 26. [5] Lucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven and Gerard van der Weide, A 56 mw ContinuousTime Quadrature Cascaded Σ Modulator With 77 db DR in a Near ZeroIF 2 MHz Band, IEEE Journal of SolidState Circuits, vol. 42, no. 12, pp , Dec. 27. [6] Nithin Kumar Y.B., Selçuk Talay, and Franco Maloberti, On the Design of BandPass Quadrature Σ Modulators, Proc. of IEEE Asia Pacific Conf. on Circuits and Systems, pp , Dec. 28. [7] Erkan Bilhan and Franco Maloberti, A Wideband SigmaDelta Modulator With CrossCoupled TwoPaths IEEE Transactions on Circuits and SystemsI, vol. 56, no. 5, pp , May 29. [8] Feng Ying and Franco Maloberti, A Mirror Image Free TwoPath Bandpass Σ Modulator with 72dB SNR and 86dB SFDR, IEEE International SolidState Circuits Conference Dig. Tech. Pap., pp. 8485, Feb. 24. [9] Ivano Galdi, Edoardo Bonizzoni, Piero Malcovati, Gabriele Manganaro, and Franco Maloberti, 4 MHz IF 1 MHz Bandwidth TwoPath Bandpass Σ Modulator with 72 db DR Consuming 16 mw, IEEE Journal of SolidState Circuits, no. 7, vol. 43, pp , July