2011/12 Cellular IC design RF, Analog, Mixed-Mode
|
|
|
- Hector Jennings
- 5 years ago
- Views:
Transcription
1 2011/12 Cellular IC design RF, Analog, Mixed-Mode Mohammed Abdulaziz, Mattias Andersson, Jonas Lindstrand, Xiaodong Liu, Anders Nejdel Ping Lu, Luca Fanori Martin Anderson, Lars Sundström, Pietro Andreani Department for Electrical and Information Technology Lund University
2 Overview A reconfigurable channel-select filter Mohammed Abdulaziz A continuous-time ΔΣ A/D converter Xiaodong Liu A filtering continuous-time ΔΣ A/D converter Mattias Andersson PA / TX circuits Jonas Lindstrand A noise-shaping time-to-digital converter Ping Lu
3 Overview II Linear RX front-end (previous presentation) Anders Nejdel (SSF DARE project) Highly efficient class-c VCO (next presentation) Luca Fanori (FP7 DRAGON project, SoS) RX BB for carrier aggregation (not included) Martin Anderson, Lars Sundström
4 A reconfigurable channel-select filter (SSF DARE project) Limit unwanted signals falling close to the baseband Relax the dynamic range requirements of the ADC Mohammed Abdulaziz
5 Project goals and challenges Linearity vs. noise control via digital control word Break the linearity vs. noise trade-off with a linearization scheme R Q : tunes the Q factor of the filter C: selects the operating band R1, R2 and R3: compensate process variations
6 Chip photo and Simulations Taped out in June 2012, under measurement Parameter Value Process Technology 65nm CMOS Response Chebyshev Order 5 th Power Supply 1.2V Current Consumption 3.2 ma Input Referred Noise 38nV/ Hz IIP3 24 dbm Frequency Bands 20/15/10/5/3/1.4 MHz Tuning Range ±40% Complete RF front-end (LNA+Mixer+Filter) for Oct TO
7 Wideband A/D converters (SSF DARE project) Xiaodong Liu 3 rd order, 4-bit, f s =640MHz, BW=20MHz (OSR=16) Goal To meet the bandwidth requirement of LTE Advanced standard (20MHz to 100MHz) To demonstrate the feasibility of reducing power consumption while maintaining a good SNR by means of digital enhancement techniques Approach Continuous-time Delta-Sigma modulator is attractive for BW beyond 20MHz Pipelined A/D is a good candidate for the LTE Advanced maximum bandwidth of 100MHz
8 Delta-Sigma A/D system level design Magnitude [db] STF NTF CT sigma-delta modulator with inherent anti-aliasing Combination of feedforward and feedback topology Direct feedback path around quantizer through DAC 4 for delay compensation Frequency [Hz]
9 Circuit implementation Active-RC op-amp filter with feedforward gm compensation in the op-amp Current-steering DAC with non-return to zero (NRZ) pulses Dynamic element matching to mitigate distortion effect of mismatch in the DAC elements TO in March 2013
10 Continuous-Time ΔS ADC for LTE (FP7 DRAGON project, SoS) 3 rd order, 3-bit, f s =288MHz, BW=9MHz (OSR=16) Mattias Andersson 10 0 signal q-noise Tayloring the feedback pulses for the three DACs, the 4 th DAC around the quantizer is avoided!
11 Design details RZ pulses in DAC3 reduce sensitivity to loop delay Loop delay compensation (DAC4) can be omitted Quadrature clock phases assumed (available for free in any radio RX)
12 Measurement results Measured spectrum db spectrerf [dbfs] Matlab Frequency Frequency [Hz] Peak SNDR 69dB Peak SNR 71dB Very good predictions with spectrerf + transient noise
13 Chip photograph and performance summary To be presented at the A-SSCC nm CMOS Parameter Value BW 9MHz OSR 16 SNDR 69dB I vdd FOM 6.2mA 175fJ/conv step Area 0.1mm 2 Improved version with added filtering action: TO in June 2012 (not yet received), and again in Oct. 2012
14 Power Amplifier in 65nm CMOS (VINNOVA, SoS) Jonas Lindstrand Self-oscillating PA Supply (V dd ) modulation Reduced switching losses Wideband injection lock Resistive injection node M S amplifies injected current Tapped cascode C Tap + C par,mc Reduced stress on M I /M S Reduced SC loss on C par
15 Chip photograph and performance Presented at ESSCIRC 2011 Output power Power gain PAE Output power PAE
16 LO generation (VCO, active-ppf, 3/2 divider) Reduces VCO pulling from PA with M. Törmänen and A. Axholt BB + PPF 3/2 BB - 1mm 30mW Power Consumption 0.53mm
17 LO generation performance Switch Tuning
18 Models for ED-MOS in STM 65nm CMOS Increase PA output power Use ED-MOS transistors with high breakdown voltage No real RF model is supplied from CMP We will build our own RF MOS model Together with Prof. Christian Fager at Chalmers
19 MHz Impedance Tuner in STM 65nm CMOS-SOI Compensate for the antenna mismatch Up to a VSWR of 4.5 Low insertion loss (IL) Less then 1dB with off-chip inductor Q of 50 for L s,1 and L s,2 4-bit switched capacitor banks (C p,1, C p,2, C p,3 ) Can handle 30dBm of TX power at an antenna VSWR of 4 Taped-Out in June 2012 Still waiting for fabrication 1x1mm 2
20 Time-to-digital converter (VR, SSF DARE, EU Marie Curie) Ping Lu TDC in digital PLL replaces phase-frequency detector of analog PLL Smaller TDC-cell delay (Δt delay ) à lower in-band PLL noise
21 Ring-oscillator TDC Ring-Oscillator TDC à large detection range with few stages
22 Varnier TDC and GRO TDC Vernier TDC à t 1 -t 2 = Dt delay < t 1 (t 2 ) However, a very large number of stages are required Ring-Oscillator (RO) TDC à large detection range with few stages ü Gated-RO TDC à ar RO TDC, with quantization noise pushed to high frequencies
23 Vernier + gated ring oscillator New TDC à combines Vernier + GRO High Vernier time resolution + First-order noise shaping
24 Chip photograph and results of VGRO TDC Multi-Phase Counter PFD Harmonic spurs due to signal generator SGRO+FGRO Area 0.027mm 2 Process Current (Supply) Vernier resolution Effective in-band resolution (OSR= 16) 90nm CMOS 3mA (1.2V) ~5ps ~3ps Presented at ESSCIRC 2011 Invited and published in JSSC July 2012
25 Two-dimensional VGRO TDC Developed from VGRO TDC and 2-D Vernier (Univ. of Pavia, Italy) Many more signal pairs used than in 1-D VRGO TDC à enhanced detection range Reduce latency time Under measurement, to be presented at NORCHIP 2012 Vercesi et al, JSSC Aug. 2012
26 Chip photo and simulations t 2 t 2 t 2 t 2 t 1 t 1 t t 1 1 GRO based 2-D Vernier TDC implementation Transient output PSD of TDC output
27 SCANDINAVIAN EXCELLENCE DEFINED IN LUND
Digitally Assisted Radio Evolution DARE
Digitally Assisted Radio Evolution DARE Pietro Andreani Department of Electrical and Information Technology Lund University, Sweden The DARE Concept Focus on 4G radio receiver and frequency generation
2008/09 Advances in the mixed signal IC design group
2008/09 Advances in the mixed signal IC design group Mattias Andersson Mixed-Signal IC Design Department for Electrical and Information Technology Lund University 1 Mixed Signal IC Design Researchers Associate
Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC
Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Jinseok Koh Wireless Analog Technology Center Texas Instruments Inc. Dallas, TX Outline Fundamentals for ADCs Over-sampling and Noise
Research and Development Activities in RF and Analog IC Design. RFIC Building Blocks. Single-Chip Transceiver Systems (I) Howard Luong
Research and Development Activities in RF and Analog IC Design Howard Luong Analog Research Laboratory Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications
RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication
Reconfigurable Low-Power Continuous-Time Sigma-Delta Converter for Multi- Standard Applications
ECEN-60: Mixed-Signal Interfaces Instructor: Sebastian Hoyos ASSIGNMENT 6 Reconfigurable Low-Power Continuous-Time Sigma-Delta Converter for Multi- Standard Applications ) Please use SIMULINK to design
On the Study of Improving Noise Shaping Techniques in Wide Bandwidth Sigma Delta Modulators
On the Study of Improving Noise Shaping Techniques in Wide Bandwidth Sigma Delta Modulators By Du Yun Master Degree in Electrical and Electronics Engineering 2013 Faculty of Science and Technology University
DESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTA ADC FOR SIGNAL PROCESSING APPLICATION
ISSN: 2395-1680 (ONLINE) DOI: 10.21917/ijme.2016.0033 ICTACT JOURNAL ON MICROELECTRONICS, APRIL 2016, VOLUME: 02, ISSUE: 01 DESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTA ADC
CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC
CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC Hussein Fakhoury and Hervé Petit C²S Research Group Presentation Outline Introduction Basic concepts
SiNANO-NEREID Workshop:
SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates
Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters
0 Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters F. Maloberti University of Pavia - Italy franco.maloberti@unipv.it 1 Introduction Summary Sigma-Delta
Design Considerations for 5G mm-wave Receivers. Stefan Andersson, Lars Sundström, and Sven Mattisson
Design Considerations for 5G mm-wave Receivers Stefan Andersson, Lars Sundström, and Sven Mattisson Outline Introduction to 5G @ mm-waves mm-wave on-chip frequency generation mm-wave analog front-end design
A 1.7-to-2.2GHz Full-Duplex Transceiver System with >50dB Self-Interference Cancellation over 42MHz Bandwidth
A 1.7-to-2.2GHz Full-Duplex Transceiver System with >50dB Self-Interference Cancellation Tong Zhang, Ali Najafi, Chenxin Su, Jacques C. Rudell University of Washington, Seattle Feb. 8, 2017 International
A K-Delta-1-Sigma Modulator for Wideband Analog-to-Digital Conversion
A K-Delta-1-Sigma Modulator for Wideband Analog-to-Digital Conversion Abstract : R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University jbaker@boisestate.edu
A single-slope 80MS/s ADC using two-step time-to-digital conversion
A single-slope 80MS/s ADC using two-step time-to-digital conversion The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published
Integrated Microsystems Laboratory. Franco Maloberti
University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti franco.maloberti@unipv.it OUTLINE Introduction Managing the noise power budget Challenges of State-of-the-art
A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS
UT Mixed-Signal/RF Integrated Circuits Seminar Series A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS Pio Balmelli April 19 th, Austin TX 2 Outline VDSL specifications Σ A/D converter features Broadband
Challenges in Designing CMOS Wireless System-on-a-chip
Challenges in Designing CMOS Wireless System-on-a-chip David Su Atheros Communications Santa Clara, California IEEE Fort Collins, March 2008 Introduction Outline Analog/RF: CMOS Transceiver Building Blocks
Design of Wireless Transceiver in 0.18um CMOS Technology for LoRa application
Design of Wireless Transceiver in 0.18um CMOS Technology for LoRa application Yoonki Lee 1, Jiyong Yoon and Youngsik Kim a Department of Information and Communication Engineering, Handong University E-mail:
A/D Conversion and Filtering for Ultra Low Power Radios. Dejan Radjen Yasser Sherazi. Advanced Digital IC Design. Contents. Why is this important?
1 Advanced Digital IC Design A/D Conversion and Filtering for Ultra Low Power Radios Dejan Radjen Yasser Sherazi Contents A/D Conversion A/D Converters Introduction ΔΣ modulator for Ultra Low Power Radios
Session 3. CMOS RF IC Design Principles
Session 3 CMOS RF IC Design Principles Session Delivered by: D. Varun 1 Session Topics Standards RF wireless communications Multi standard RF transceivers RF front end architectures Frequency down conversion
An All CMOS, 2.4 GHz, Fully Adaptive, Scalable, Frequency Hopped Transceiver
An All CMOS, 2.4 GHz, Fully Adaptive, Scalable, Frequency Hopped Transceiver Farbod Behbahani John Leete Alexandre Kral Shahrzad Tadjpour Karapet Khanoyan Paul J. Chang Hooman Darabi Maryam Rofougaran
IF-Sampling Digital Beamforming with Bit-Stream Processing. Jaehun Jeong
IF-Sampling Digital Beamforming with Bit-Stream Processing by Jaehun Jeong A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering)
5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE a/b/g WLAN
5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN Manolis Terrovitis, Michael Mack, Kalwant Singh, and Masoud Zargari 1 Atheros Communications, Sunnyvale, California 1 Atheros
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5 20.5 A 2.4GHz CMOS Transceiver and Baseband Processor Chipset for 802.11b Wireless LAN Application George Chien, Weishi Feng, Yungping
Appendix A Comparison of ADC Architectures
Appendix A Comparison of ADC Architectures A comparison of continuous-time delta-sigma (CT ), pipeline, and timeinterleaved (TI) SAR ADCs which target wide signal bandwidths (greater than 100 MHz) and
Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers
2017.07.03 Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers Akira Matsuzawa and Kenichi Okada Tokyo Institute of Technology Contents 1 Demand for high speed data transfer Developed high
A High Dynamic Range Digitally- Controlled Oscillator (DCO) for All-DPLL systems is. Samira Jafarzade 1, Abumoslem Jannesari 2
A High Dynamic Range Digitally- Controlled Oscillator (DCO) for All-Digital PLL Systems Samira Jafarzade 1, Abumoslem Jannesari 2 Received: 2014/7/5 Accepted: 2015/3/1 Abstract In this paper, a new high
Design of Continuous Time Sigma Delta ADC for Signal Processing Application
International Journal of Luminescence and Applications (ISSN: 22776362) Vol. 7, No. 34, October December 2017. Article ID: 254. pp.486490. Design of Continuous Time Sigma Delta ADC for Signal Processing
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder Zhijie Chen, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology,
A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1, Bongjin Kim 1,2, Chris H. Kim 1 1
High Performance Digital Fractional-N Frequency Synthesizers
High Performance Digital Fractional-N Frequency Synthesizers Michael Perrott October 16, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. Why Are Digital Phase-Locked Loops Interesting? PLLs
Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation. Seyyed Amir Ayati
Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation by Seyyed Amir Ayati A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2 20.2 A Digitally Calibrated 5.15-5.825GHz Transceiver for 802.11a Wireless LANs in 0.18µm CMOS I. Bouras 1, S. Bouras 1, T. Georgantas
Pipeline vs. Sigma Delta ADC for Communications Applications
Pipeline vs. Sigma Delta ADC for Communications Applications Noel O Riordan, Mixed-Signal IP Group, S3 Semiconductors noel.oriordan@s3group.com Introduction The Analog-to-Digital Converter (ADC) is a key
1 Introduction to Highly Integrated and Tunable RF Receiver Front Ends
1 Introduction to Highly Integrated and Tunable RF Receiver Front Ends 1.1 Introduction With the ever-increasing demand for instant access to data over wideband communication channels, the quest for a
Bootstrapped ring oscillator with feedforward inputs for ultra-low-voltage application
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Bootstrapped ring oscillator with feedforward
Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies
A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.
Receiver Architecture
Receiver Architecture Receiver basics Channel selection why not at RF? BPF first or LNA first? Direct digitization of RF signal Receiver architectures Sub-sampling receiver noise problem Heterodyne receiver
Asynchronous Sigma Delta Modulators for Data Conversion
1 Asynchronous Sigma Delta Modulators for Data Conversion Wei Chen Imperial College London Department of Electrical and Electronic Engineering Submitted in Partial Fulfilment of the Requirements for the
Chapter 2 Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL
Chapter 2 Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL 2.1 Background High performance phase locked-loops (PLL) are widely used in wireless communication systems to provide
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver. Hamid Rategh
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver Hamid Rategh Center for Integrated Systems Stanford University OUTLINE Motivation Introduction
Bluetooth Receiver. Ryan Rogel, Kevin Owen I. INTRODUCTION
1 Bluetooth Receiver Ryan Rogel, Kevin Owen Abstract A Bluetooth radio front end is developed and each block is characterized. Bits are generated in MATLAB, GFSK endcoded, and used as the input to this
A VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping
A VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC.
Design Examples MEAD March 008 Richard Schreier Richard.Schreier@analog.com ANALOG DEVICES Catalog nd -Order Lowpass Architecture: Single-bit, switched-capacitor Application: General-purpose, low-frequency
EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.
EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:
NPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering.
NPTEL Syllabus VLSI Data Conversion Circuits - Video course COURSE OUTLINE This course covers the analysis and design of CMOS Analog-to-Digital and Digital-to-Analog Converters,with about 7 design assigments.
A 1.9GHz Single-Chip CMOS PHS Cellphone
A 1.9GHz Single-Chip CMOS PHS Cellphone IEEE JSSC, Vol. 41, No.12, December 2006 William Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, Keith Onodera, Steve Jen, Susan Luschas, Justin
FMC ADC 125M 14b 1ch DAC 600M 14b 1ch Technical Specification
FMC ADC 125M 14b 1ch DAC 600M 14b 1ch Technical Specification Tony Rohlev October 5, 2011 Abstract The FMC ADC 125M 14b 1ch DAC 600M 14b 1ch is a FMC form factor card with a single ADC input and a single
A 10 MHz Bandwidth Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners
Downloaded from orbit.dtu.dk on: Aug 23, 2018 A 10 MHz Bandwidth Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners Llimos Muntal, Pere; Jørgensen, Ivan Harald Holger; Bruun, Erik Published
Paper presentation Ultra-Portable Devices
Paper presentation Ultra-Portable Devices Paper: Lourans Samid, Yiannos Manoli, A Low Power and Low Voltage Continuous Time Δ Modulator, ISCAS, pp 4066-4069, 23 26 May, 2005. Presented by: Dejan Radjen
A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD
A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan
A 2.5 V 109 db DR ADC for Audio Application
276 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.4, DECEMBER, 2010 A 2.5 V 109 db DR ADC for Audio Application Gwangyol Noh and Gil-Cho Ahn Abstract A 2.5 V feed-forward second-order deltasigma
Low-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
ECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 11: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Exam 1 is on Wed. Oct 3
A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal Detection
A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal Detection Hamid Nejati and Mahmood Barangi 4/14/2010 Outline Introduction System level block diagram Compressive
DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS
DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven,
BandPass Sigma-Delta Modulator for wideband IF signals
BandPass Sigma-Delta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters
FD-SOI FOR RF IC DESIGN. SITRI LETI Workshop Mercier Eric 08 september 2016
FD-SOI FOR RF IC DESIGN SITRI LETI Workshop Mercier Eric 08 september 2016 UTBB 28 nm FD-SOI : RF DIRECT BENEFITS (1/2) 3 back-end options available Routing possible on the AluCap level no restriction
Lecture 10, ANIK. Data converters 2
Lecture, ANIK Data converters 2 What did we do last time? Data converter fundamentals Quantization noise Signal-to-noise ratio ADC and DAC architectures Overview, since literature is more useful explaining
ECEN 610 Mixed-Signal Interfaces
Spring 2014 S. Hoyos-ECEN-610 1 ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Oversampling ADC Spring 2014 S. Hoyos-ECEN-610 2 Spring 2014 S. Hoyos-ECEN-610
Reconfigurable and Simultaneous Dual Band Galileo/GPS Front-end Receiver in 0.13µm RFCMOS
Reconfigurable and Simultaneous Dual Band Galileo/GPS Front-end Receiver in 0.13µm RFCMOS A. Pizzarulli 1, G. Montagna 2, M. Pini 3, S. Salerno 4, N.Lofu 2 and G. Sensalari 1 (1) Fondazione Torino Wireless,
NEW WIRELESS applications are emerging where
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 709 A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis Shwetabh Verma, Member, IEEE, Junfeng Xu, and Thomas H. Lee,
A Low-Power Single-Bit Continuous-time DS Converter with 92.5dB Dynamic Range and design of Low-Voltage Σ ADCs
A Low-Power Single-Bit Continuous-time DS Converter with 92.5dB Dynamic Range and design of Low-Voltage Σ ADCs Sakkarapani Balagopal and Vishal Saxena* Department of Electrical and Computer Engineering
Integrated Circuit Design for High-Speed Frequency Synthesis
Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency
ADVANCES in VLSI technology result in manufacturing
INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 1, PP. 99 104 Manuscript received January 8, 2013; revised March, 2013. DOI: 10.2478/eletel-2013-0012 Rapid Prototyping of Third-Order
95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS
95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS Ekaterina Laskin, Mehdi Khanpour, Ricardo Aroca, Keith W. Tang, Patrice Garcia 1, Sorin P. Voinigescu University
A Continuous-time Sigma-delta Modulator with Clock Jitter Tolerant Self-resetting Return-to-zero Feedback DAC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.4, AUGUST, 2018 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2018.18.4.468 ISSN(Online) 2233-4866 A Continuous-time Sigma-delta Modulator
Radio Research Directions. Behzad Razavi Communication Circuits Laboratory Electrical Engineering Department University of California, Los Angeles
Radio Research Directions Behzad Razavi Communication Circuits Laboratory Electrical Engineering Department University of California, Los Angeles Outline Introduction Millimeter-Wave Transceivers - Applications
A Mostly Digital Variable-Rate Continuous- Time ADC Modulator
A Mostly Digital Variable-Rate Continuous- Time ADC Modulator Gerry Taylor 1,2, Ian Galton 1 1 University of California at San Diego, La Jolla, CA 2 Analog Devices, San Diego, CA INTEGRATED SIGNAL PROCESSING
Oversampling Converters
Oversampling Converters Behzad Razavi Electrical Engineering Department University of California, Los Angeles Outline Basic Concepts First- and Second-Order Loops Effect of Circuit Nonidealities Cascaded
26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone
26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone William W. Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, KeithOnodera, SteveJen, Susan Luschas, Justin Hwang, SuniMendis, DavidSu, BruceWooley
Minimizing Spurious Tones in Digital Delta-Sigma Modulators
Minimizing Spurious Tones in Digital Delta-Sigma Modulators ANALOG CIRCUITS AND SIGNAL PROCESSING Series Editors: Mohammed Ismail Mohamad Sawan For other titles published in this series, go to http://www.springer.com/series/7381
ECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 8: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam 1 is
High Performance Digital Fractional-N Frequency Synthesizers. IEEE Distinguished Lecture Lehigh Valley SSCS Chapter
High Performance Digital Fractional-N Frequency Synthesizers IEEE Distinguished Lecture Lehigh Valley SSCS Chapter Michael H. Perrott October 2013 Copyright 2013 by Michael H. Perrott All rights reserved.
Low Power Communication Circuits for WSN
Low Power Communication Circuits for WSN Nate Pletcher, Prof. Jan Rabaey, (B. Otis, Y.H. Chee, S. Gambini, D. Guermandi) Berkeley Wireless Research Center Towards A Micropower Integrated Node power management
A 15 GHz Bandwidth 20 dbm P SAT Power Amplifier with 22% PAE in 65 nm CMOS
A 15 GHz Bandwidth 20 dbm P SAT Power Amplifier with 22% PAE in 65 nm CMOS Junlei Zhao, Matteo Bassi, Andrea Mazzanti and Francesco Svelto University of Pavia, Italy Outline Wideband Power Amplifier Design
A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator
A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator ISSCC 00, Session 3. M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S.
CONTINUOUS-TIME (CT) ΔΣ modulators have gained
530 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 DT Modeling of Clock Phase-Noise Effects in LP CT ΔΣ ADCs With RZ Feedback Martin Anderson, Member, IEEE, and
A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL
A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL Chung-Lun Hsu and Drew A. Hall University of California, San Diego, La Jolla, CA, USA International Solid-State Circuits Conference
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction. Andrea Panigada, Ian Galton
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction Andrea Panigada, Ian Galton University of California at San Diego, La Jolla, CA INTEGRATED SIGNAL PROCESSING
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report
Lecture 9, ANIK. Data converters 1
Lecture 9, ANIK Data converters 1 What did we do last time? Noise and distortion Understanding the simplest circuit noise Understanding some of the sources of distortion 502 of 530 What will we do today?
A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier
A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier Hugo Serra, Nuno Paulino, and João Goes Centre for Technologies and Systems (CTS) UNINOVA Dept. of Electrical Engineering
Package and Pin Assignment SSOP-6 (0.64mm pitch) OSCIN OSCOUT TXEN 3 VSS 4 TXOUT 5 VSS 6 7 MODIN 8 HiMARK SW DO RES RESB VREFP VSS Symbol
Low Power ASK Transmitter IC HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior
Designing CMOS Wireless System-on-a-chip
Designing CMOS Wireless System-on-a-chip David Su david.su@atheros.com Atheros Communications Santa Clara, California Santa Clara SSCS (c) D. Su Santa Clara SSCS September 2009 p.1 Outline Introduction
Signal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE
RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE Mehdi Taghizadeh and Sirus Sadughi Department of Electrical Engineering, Science and Research Branch,
High Data Rate 60 GHz CMOS Transceiver Design
High Data Rate 6 GHz CMOS Transceiver Design Akira Matsuzawa Department of Physical Electronics Graduate School of Science and Electronics Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo, 152-8552,
ISSCC 2006 / SESSION 33 / MOBILE TV / 33.4
33.4 A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia Broadcasting Vincenzo Peluso, Yang Xu, Peter Gazzerro, Yiwu Tang, Li Liu, Zhenbiao Li, Wei Xiong, Charles Persico Qualcomm, San
Aspemyr, Lars; Jacobsson, Harald; Bao, Mingquan; Sjöland, Henrik; Ferndal, Mattias; Carchon, G
A 15 GHz and a 2 GHz low noise amplifier in 9 nm RF CMOS Aspemyr, Lars; Jacobsson, Harald; Bao, Mingquan; Sjöland, Henrik; Ferndal, Mattias; Carchon, G Published in: Topical Meeting on Silicon Monolithic
Low- Power Third- Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications
C. Della Fiore, F. Maloberti, P. Malcovati: "Low-Power Third-Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications"; Ph. D. Research in Microelectronics and Electronics, PRIME 2006, Otranto,
A New Current-Mode Sigma Delta Modulator
A New Current-Mode Sigma Delta Modulator Ebrahim Farshidi 1 1 Department of Electrical Engineering, Faculty of Engineering, Shoushtar Branch, Islamic Azad university, Shoushtar, Iran e_farshidi@hotmail.com
Design of a Sigma Delta modulator for wireless communication applications based on ADSL standard
Design of a Sigma Delta modulator for wireless communication applications based on ADSL standard Mohsen Beiranvand 1, Reza Sarshar 2, Younes Mokhtari 3 1- Department of Electrical Engineering, Islamic
A 98dB 3.3V 28mW-per-channel multibit audio DAC in a standard 0.35µm CMOS technology
A 98dB 3.3V 28mW-per-channel multibit audio DAC in a standard 0.35µm CMOS technology M. Annovazzi, V. Colonna, G. Gandolfi, STMicroelectronics Via Tolomeo, 2000 Cornaredo (MI), Italy vittorio.colonna@st.com
LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS. Alireza Nilchi
LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS by Alireza Nilchi A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical
A Pulse-Based CMOS Ultra-Wideband Transmitter for WPANs
A Pulse-Based CMOS Ultra-Wideband Transmitter for WPANs Murat Demirkan* Solid-State Circuits Research Laboratory University of California, Davis *Now with Agilent Technologies, Santa Clara, CA 03/20/2008
Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC
WCAS2016 Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC Andrade, N.; Toledo, P.; Cordova, D.; Negreiros, M.; Dornelas, H.; Timbó, R.; Schmidt, A.; Klimach, H.; Frabris, E.
Dual-Frequency GNSS Front-End ASIC Design
Dual-Frequency GNSS Front-End ASIC Design Ed. 01 15/06/11 In the last years Acorde has been involved in the design of ASIC prototypes for several EU-funded projects in the fields of FM-UWB communications
Phase-Locked Loops and Their Applications. Advanced PLL Examples (Part II)
Short Course On Phase-Locked Loops and Their Applications Day 5, PM Lecture Advanced PLL Examples (Part II) Michael Perrott August 15, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. Outline