2008/09 Advances in the mixed signal IC design group

Transcription

1 2008/09 Advances in the mixed signal IC design group Mattias Andersson Mixed-Signal IC Design Department for Electrical and Information Technology Lund University 1

2 Mixed Signal IC Design Researchers Associate Professor, Pietro Andreani Assistant Professor, Martin Anderson (SoS-DSCs, nov 2008) Post-Doc, Ping Lu (VR-ADPLL, april 2009) Ph.D Student, Dejan Radjen (VR-UPD, feb. 2009) Ph.D Student, Mattias Andersson (SoS-DSCs, feb. 2009) Adjunct Professor, Lars Sundström Adjunct Professor, Sven Mattisson Professor Emeritus, Jiren Yuan CAD support: Stefan Molund Linux support: Erik Jonsson 2

3 Publications Summary 2008/2009 Journal Papers: 6 (4 JSSC, 1 TMTT, 1 TCAS-II) International Conference Papers: 3 (2 ISSCC, 1 NORCHIP) Ph.D Thesis: 1 National Conference Papers / Presentations: >3 3

4 Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise Andrea Mazzanti and Pietro Andreani IEEE Journal of Solid-State Circuits Vol. 43, No. 12, pp , Dec

5 Class-C thanks to tail capacitance C tail L C tank V DD Class C Larger amplitude, same noise for same I bias C tail from foe to friend V bias MOS must not leave saturation Shift of MOS DC gate voltage I bias C tail = 2 C 2 6M (Cu) 0.13µm CMOS (no thick metal layers) 2.0nH inductor, A-MOS varactors, tank-q

6 State-of-the-art phase-noise performance 4.90 GHz < f c < 5.65 GHz V dd = 1V, I dd =1.4 ma f osc =5.52GHz f osc =4.90GHz -130 dbc/hz 6

7 General result on phase noise Harmonic oscillators Phase noise generated by active devices in oscillator core largely independent of the active device dimensions Instead, determined by resonator losses 7

8 DT Modeling and Reduction of Clock Jitter Sensitivity in CT Delta-Sigma Modulators Martin Anderson and Lars Sundström IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 7, pp , 2009 IEEE Journal of Solid-State Circuits vol. 44, no. 2, pp ,

9 Clock Phase-Noise Sensitivity Intro v c (t) v a (t) H(s) clk DAC v d [n] Desired signal Close in noise S d (f) 0 S clk (f) Shaped q-noise f clk f Wideband PN Quantization noise clk f Wideband noise Close-in PN Input signal 9

10 DT Clock Phase-Noise Modeling Method v d PN v c CT Σ modulator v d Pulse-Position Noise (PPN) models the modulation with strong signals and close in PN PPN model PPN Noisy clock Signal gen v c DT Σ modulator v d Pulse-Width Noise (PWN) models the modulation between quantization noise and wideband PN PWN model v d PN PWN Ideal clock Faster simulations with arbitrary input signals and arbitrary clock PN spectra 10

11 DT Clock Phase-Noise Modeling Method Typical DT simulation output spectra v d PN v c CT Σ modulator v d Noisy clock OFDM input signal PWN QN DT sim. PPN Frequency [MHz] PPN model Signal gen PWN model PPN v c PWN DT Σ modulator v d Ideal clock v d PN 11

12 DT Modeling Summary and Conclusions In-band noise a function of phase-noise spectra input signals quantization noise spectrum (NTF) DT modeling method enables fast and accurate PN simulations Verified with simulations and measurements Conclusion PWN limits the performance in many practical situations. 12

13 SC-feedback reduces clock jitter sensitivity CT Σ modulator with SI RZ feedback CT Σ modulator with SCR feedback - High sensitivity to PW variations + Small peak current + Low sensitivity to PW variations - Large peak current 13

14 SC-feedback with variable series resistor Switched capacitor Reduced sensitivity to PW variations Variable resistance Reduced peak current Reset Constant current Exponential discharge 14

15 PN Measurements PN Amplitude Sweep Sensitivity to systematic (single tone) f o / f s = 0.3 PN tone amplitude sweep 30 db IBN improvement IBN [dbfs] SI DAC PWN simulation Total measured IBN Total simulated IBN SI DAC PWN simulation PW jitter, (σ pw / T s ) [%] 15

16 Summary and Conclusions The SCSR feedback DAC concept is proposed Reduced sensitivity to wideband phase-noise Reduced peak feedback current ADC circuit fabricated A 5-mW, 312-MHz, 2 nd -order CT Σ modulator with SCSR feedback, 66dB SNR. 30dB reduction of sensitivity to wideband clock PN measured 16

17 Work in Progress Ping Lu (postdoc) a REF PFD/TDC Loop Filter Σ Tuning Bank Controller b DCO Δ Modulator /N New Time-to-Digital Converter design 17

18 Work in Progress Dejan Radjen (Ph.D student) Ultra low power 3rd order, 3 bits CT Σ - ADC with modified feedback pulses Sampling frequency = 5MHz, Bandwidth = 125 khz, SNDR = 74 db, Power consumption = 100 μw 18

19 Work in Progress Mattias Andersson (Ph.D student) CT Σ ADC for LTE (short term goals) 3rd order, f s =288MHz, BW=9MHz v c (t) H(s) clk v d [n] Protection New clocking scheme Multibit DACs and DEM v a (t) DAC clk Tapeout planned Q

20 Journal Publications 2008/2009 S. Mattisson, H. Hagberg, P. Andreani, Sensitivity degradation in a tri-band GSM BiCMOS direct-conversion receiver caused by transient substrate heating. IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, pp , A. Mazzanti, E. Sacchi, P. Andreani, F. Svelto, Analysis and design of a doublequadrature CMOS VCO for subharmonic mixing at Ka-band, IEEE Transactions on Microwave Theory and Techniques, Vol. 56, No. 2, pp , L. Lu, Z. Tang, P. Andreani, A. Mazzanti, A. Hajimiri, Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators, IEEE Journal of Solid- State Circuits, Vol. 43, No. 9, pp , A. Mazzanti, P. Andreani, Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise, IEEE Journal of Solid-State Circuits, Vol. 43, No. 12, pp , M. Anderson, L. Sundström, Design and Measurement of a CT Delta-Sigma ADC with Switched-Capacitor Switched-Resistor Feedback, IEEE Journal of Solid State Circuits, Vol. 44, No. 2, pp , M. Anderson, L. Sundström, DT Modeling of Clock Phase Noise Effects in LP CT Delta-Sigma ADCs with RZ Feedback, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 7, pp ,

21 Conference Publications 2008/2009 P. Lu, H. Sjöland, A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM, Norchip, Tallinnn, J. Citakovic, P. F. Høvesten, G. Rocca, A. van Halteren, P. Rombach, L. J. Stenberg, P. Andreani, E. Bruun, A compact CMOS MEMS microphone with 66dB SNR, 2009 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco, Vol. 52, pp , A. Mazzanti, P. Andreani, A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz, 2008 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, S. Francisco, CA, pp , 629, Feb. 4-6,

22 SC ANDINAVIAN EXCELLENCE DEFINED IN LUND