A GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FoM using inductor splitting for tuning extension

Transcription

1 A GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FoM using inductor splitting for tuning extension E. Mammei, E. Monaco*, A. Mazzanti, F. Svelto Università degli Studi di Pavia, Pavia, Italy * STMicroelectronics, Pavia, Italy International Solid State Circuits Conference, ISSCC 2013

2 Mm-wave VCOs - issues Tuning Range [%] Tuning Range reduces dramatically Wide Tuning Range leads to poor phase noise FoM State of the art FoM and wide tuning range is challenging 2

3 Review of switched capacitor tuning C FIX : parasitic cap of buffer and core devices C FIX equal or greater than C T at mmwave SW ON: f MIN 2 1 L C C T FIX T SW OFF: f MAX determined by C FIX f MAX 2 L T C FIX 1 csw CT, CFIX 1 Cc 2 LC T SW T CT csw FIX 3

4 Proposed switched capacitor tuning c SW in series with C T +C FIX Much higher frequency jump SW ON: f MIN as in switched cap. oscillator SW OFF: C FIX no more limiting f MAX f MAX 2 1 csw CT, CFIX 1 C 2 T CFIX c Lc SW T LT C C c T FIX SW SW Mammei et al., ISSCC

5 Comparison with same frequency jump Assuming: C FIX =C T =100fF, L T =100pH, FOM SW =550fs f MIN =35.6GHz, f MAX /f MIN =1.2 W sw =41m, c SW =50fF W sw =330m,c SW =400fF Switch off r SW =11, Q=8 r SW =1.37, Q=16 Switch on -r CFIX CT LT rsw -r CFIX CT LT rsw 5

6 Q vs f max /f min with finite components Q Proposed tank Traditional switched capacitor Advantage increase for higher frequency step and/or larger C fix 6

7 VCO Design Inductor splitting with M SW for the largest tuning step Variable tank capacitance (C T ) with switched digital MOMs and varactor L T =100pH, C T =140fF, C FIX 120fF Tank Q ranges from 4 to 5.5 Transformer feedback avoids latching when M SW is off R b instead of current mirrors lowers 1/f noise 7

8 Test Chip CMOS 32nm LP from STMicroelectronics Core Area 70um x 120um 40GHz center frequency Phase Noise measured after divider by 4 in X-Band (8-12GHz) 9.8mW from 1V supply 8

9 Phase Noise & FoM over Tuning Range 10 MHz offset 9

10 Summary and Comparison REF FREQ [GHz] TR [%] POWER [mw] [dbc/hz] FOM [dbc/hz] TECH CICC / / / /180 65nm RFIC / /29-107/-127* 158.6/ nm RFIC / /-121* 178.4/ nm JSSCC / /-119* 179/180 65nm ISSCC / nm This Work 33.6/ / /180 32nm * estimated from the reported phase noise at 1MHz 10

11 Outline VCO Design in ultra scaled technology Analysis of the proposed resonator Test chips design and experimental results Conclusions 11

12 CMOS Technology Evolution 0.13 um 6 layers IEDM 2010, S. Francisco Continuous scaling driven by complex Systems on Chip ~ 20-30% f T improvement only per generation mmwave passive components penalty due to BEOL scaling 12

13 CMOS 65nm vs 32nm: BEOL Top Level Metal High Level Metals [H.L.M.] Low Level Metals [L.L.M.] High Level Vias Low Level Metals 32nm H.L.M closer to substrate (~85%) but same thickness 32nm L.L.M. closer to substrate and thinner (~50% ) 2 time resistivity of 32nm VIAs CMOS65nm CMOS32nm 13

14 Performance of MOS Switches Switch On Switch Off rsw csw r SW 1 g m c SW C GS Trade-off between c sw and r sw FOM sw measures quality of the switch: 1 FOMSW COFF RON f 14 T

15 MOS Switch With Routing Parasitics Switch On Switch Off rsw csw w.routing w.o.routing Routing parasitics comparable to r SW and c SW FOM tends to saturate in ultra scaled technologies 15

16 CMOS 65nm vs 32nm: Inductors Inductors usually realized with top metals for maximum Q and self Resonance frequency Slightly lower dielectric constant in 32nm compensates lower metal distance to substrate in 32nm 16

17 CMOS 65nm vs 32nm: MOM Capacitors MOM capacitors realized with low level metals for max. density MOM Q in 32nm ~70% than 65nm due to half thickness of LLM and 2x via resistance 17

18 Diapositiva 17 F4 Evidenzierei con una caption qual è la misura e quale la simulazione Frank; 19/01/2013

19 Switched Capacitor Tank Q low 2 C 2R r MOM MOM SW Transistors Switch FOM, saturating in ultra scaled technologies, determines the trade off between Tuning Range and Q Significant MOM loss (R MOM ) due to higher metals and vias resistivity Switched cap. tank does not benefit from technology scaling C C MAX MIN C 2c MOM SW 1 18

20 Q versus C MAX /C MIN 32nm switched MOM slightly worse than 19

21 Outline VCO Design in ultra scaled technology Analysis of the proposed resonator Test chips design and experimental results Conclusions 20

22 . Switched Cap. Oscillator C FIX : buffer parasitic and core devices C FIX equal or greater than C T at mmw SW ON f MIN 2 1 L C C T FIX T SW OFF: f MAX determined by C FIX f MAX 2 L T C FIX 1 csw CT, CFIX 1 Cc 2 LC T SW T CT csw FIX 21

23 . Proposed Oscillator c SW in series with C T +C FIX Higher frequency jump SW.ON: f MIN as in switched cap. oscillator SW.OFF: C FIX no more limiting f MAX f MAX 2 1 csw CT, CFIX 1 C 2 T CFIX c Lc SW T LT C C c T FIX SW SW 22

24 . Comparison for the Same Frequency Jump Assuming: C FIX =C T =100fF, L T =100pH, FOM SW =550fs f MIN =35.6GHz, f MAX /f MIN =1.2 c SW =50fF c SW =400fF For the same frequency step, switch in the proposed tank may display much larger c sw 23

25 . Comparison for the Same Frequency Jump Assuming: C FIX =C T =100fF, L T =100pH, FOM SW =550fs f MIN =35.6GHz, f MAX /f MIN =1.2 -r CFIX CT LT -r CFIX CT LT rsw rsw c SW =50fF r SW =11 Q=8 c SW =400fF r SW =1.37 Q=16 Much lower r sw leads to 2x tank Q 24

26 Diapositiva 24 F7 Scrivi Ohm per rsw. Perchè 2x improvement? Frank; 19/01/2013

27 Q vs Frequency step with finite components Q Quality Advantage increases for higher frequency step and/or larger C fix 25

28 Outline VCO Design in ultra scaled technology Analysis of the proposed resonator Test chips design and experimental results Conclusions 26

29 Loop Gain with a conventional transconductor G LOOP =g m R P Switch ON R L Q PON T T Switch OFF R Loop gain penalty L Q POFF T T 2 csw C C c T FIX sw Tank is an open at DC, latching issue 27

30 Loop Gain with Transformer Feedback GLOOP m g Z 21 Switch ON LS Z21 K R L T PON Switch OFF S POFF Z21 K L T csw C C c T FIX sw Transformer restores loop gain and avoids latching 28 L R

31 Simulated Impedance R P and Z 21 Impedance[Ω ] 29

32 Spec for a 60GHz Sliding IF Architecture first down-conversion to 1/3 the received frequency quadrature down-conversion to DC 40 GHz VCO center frequency with more than 20% T.R. Phase 10MHz offset better than -115dBc/Hz 30

33 Realized VCO Inductor splitting with M SW for largest tuning step Variable tank capacitance (C T ) with switched digital MOMs and varactor LT=100pH, C T =140fF, C FIX =120fF Tank Q ranges from 4 to 5.5 R b instead of PMOS mirrors lowers 1/f noise 31

34 Chip Blocks Diagram Direct output and after div. by 4 for Phase Noise measurement in X- Band (8-12GHz) CMOS 32nm LP from STMicroelectronics Supply voltage:1v Core area: 70um x 120um 32

35 40GHz Phase Noise Measurement 33

36 Phase Noise and FoM over Tuning Range 34

37 Summary and comparison REF FREQ [GHz] TR [%] POWER [mw] [dbc/hz] FOM [dbc/hz] TECH CICC / / / /180 65nm RFIC / /-121* 178.4/180 65nm JSSCC / /-119* 179/180 65nm ISSCC / nm This Work 33.6/ / /180 32nm * estimated from the reported phase noise at 1MHz 35

38 Outline VCO Design in ultra scaled technology Analysis of the proposed resonator Test chips design and experimental results Conclusions 36

39 Conclusions Design of mmw VCOs does not benefit from ultra scaled technologies. BEOL scaling increases routing parasitics and loss of MOM capacitors A new switched resonator circuit topology, improving Q for large frequency tuning step, has been presented A 40 GHz VCO in 32nm CMOS has been presented. Measurements proved a state of the art FOM over a very large tuning range 37