Something More We Should Know About VCOs

Transcription

1 Something More We Should Know About VCOs Name: Yung-Chung Lo Advisor: Dr. Jose Silva-Martinez AMSC-TAMU 1

2 Outline Noise Analysis and Models of VCOs Injection Locking Techniques Quadrature VCOs AMSC-TAMU 2

3 The First Oscillator Phase Noise Model Leeson Model (1966) Leeson Model (LTI): AMSC-TAMU 3

4 Harjimiri s Model (T. H. Lee) Injection at Peak (amplitude noise only) Injection at Zero Crossing (maximum phase noise) AMSC-TAMU 4

5 Limit-cycle Limit-cycle due to amplitude restoring mechanism Can impulse response model deal with the Flicker noise? AMSC-TAMU 5

6 ISF Model The phase variation due to injecting noise can be modeled as: The function, Γ(x), is the time-varying proportionality factor and called the impulse sensitivity function. The phase shift is assumed linear to injection charge. ISF has the same oscillation period T of the oscillator itself. The unity phase impulse response can be written as: AMSC-TAMU 6

7 Typical ISF Example The ISF can be estimated analytically or calculated from simulation. The ISF reaches peak during zero crossing and zero at peak. AMSC-TAMU 7

8 General Response For any deterministic injection charge, the excess phase can be calculated using superposition integral. Because ISF is periodic, AMSC-TAMU 8

9 The Complete Process and System The conversion from current to phase The equivalent system for ISF decomposition AMSC-TAMU 9

10 The Conversion of Tones All noise around the harmonic frequencies and DC contribute to the phase noise. Flicker noise (1/f) contribute the 1/f 3 region. AMSC-TAMU 10

11 Summary of ISF Good insight. Applicable in both LC and ring-based oscillators. Reasonable accuracy using SPICE-like transient simulator (tedious work). Can not address flicker noise. Can not use for quadrature VCOs. No sufficient physical meanings. Tedious to design. AMSC-TAMU 11

12 Hegazi s Model (A. Abidi) How noise source contributes to the phase noise? The physical meanings? AMSC-TAMU 12

13 Tail Current Noise Only the noise located at even harmonics will produce the phase noise. AMSC-TAMU 13

14 Differential Pair Noise If the output impedance of current source is infinite, only the noise of diff-pair around odd harmonics contribute to phase noise. AMSC-TAMU 14

15 Loading in Current-Biased Oscillator Role of the current source. AMSC-TAMU 15

16 Noise Filtering in Oscillator Only thermal noise in the current source transistor around 2 nd harmonic of the oscillation cause phase noise. A high impedance at the tail is only required at the 2 nd harmonic to stop the differential pair FETs in triode from loading the resonator. AMSC-TAMU 16

17 Noise Filtering in Oscillator Tail-biased VCO with noise filtering. AMSC-TAMU 17

18 Noise Filtering in Oscillator Top-biased & voltage-biased VCO with noise filtering AMSC-TAMU 18

19 Tail Current-Shaping to Improve Phase Noise AMSC-TAMU 19

20 Tail Current-Shaping to Improve Phase Noise VCO1 VCO2 (no shaping technique) (shaping technique) AMSC-TAMU 20

21 Outline Noise Analysis and Models of VCOs Injection-locked Techniques Quadrature VCOs AMSC-TAMU 21

22 VCO Pulling and Pushing Pulling Injection Pulling: Oscillation frequency varies due to the noise frequency ex: PA output couples to local oscillator, large interference couples from LNA to VCO through mixer Load Pulling Oscillation frequency changes as the loading changes Add buffer or reduce parasitics AMSC-TAMU 22

23 VCO Pulling and Pushing Pushing Oscillation frequency changes as the supply level changes because the capacitance of varactor and the drain capacitance of MOS can be varied with the DC bias conditions Add regulator AMSC-TAMU 23

24 Injection Locking Technique Injection Locking Whe the injection frequency is close to the oscillation frequency and the injection signal is large enough, the oscillation frequency shifts toward the injection frequency. AMSC-TAMU 24

25 Injection-locked Frequency Divider Design concept of injection-locked oscillator (ILO) F in nf in + mfout LPF/BPF F out Unwanted harmonics may exist. Self-coupling may produce unwanted tones too. Injection-locked frequency dividers (ILFD) feature lower power consumption and more excellent noise performance than digital dividers. AMSC-TAMU 25

26 LC INFDs Advantage: Better noise performance (LC filtering) Low power consumption Very high operation frequency (~ fmax) Disadvantage: Smaller locking range (LC limited) Unwanted harmonics Large silicon area due to L and C Very difficult to provide multiple phases or large divisor number in one LC oscillator stage (area penalty) Difficult to find an excellent source to inject signal AMSC-TAMU 26

27 Ring-Oscillator-Based ILFDs Advantage: Smaller area Wide locking range Small power consumption Disadvantage: Inferior phase noise to LC ILFDs (Still decent) Worse unwanted harmonics (No LC resonant filtering) False locking AMSC-TAMU 27

28 Injection-Locked Frequency Divider (ILFD) with interpolated phases 3-stage ring oscillator Injected clock at 3 time the output frequency 3 clock phases are interpolated Transitions are dictated by Vin,j Excellent phase noise performance 28

29 29 Application(3) Phase Tuning Circuit Control Vbp and Vbn to change the free-running frequency vary Δϕ Phase tuning/alignment in high-speed links

30 Complementary Injection-Locked Frequency Divider (CILFD) Large odd-modulus(101) Only dynamic power consumption 100% frequency locking range Differential input/output 50% duty cycle Small area Auxiliary Inverter F in ( /(2n+1) ) F in ( 0 ) F in ( (2n)/(2n+1) ) F in ( (2n)/(2n+1) ) (2n+1)-stage F in ( /(2n+1) ) F in ( 180 ) (2n+1)-stage (2n+1) F in ( ø + 0 ) (2n+1) F in ( ø ) 30

31 Complementary Injection Scheme Complementary injection reinforces the injection strength to widen the frequency locking range. Only when the inverter transits state the tail transistors inject current. Independent tail injection to each stage avoids the interference between each stage. Injection Signal Ring-oscillator output Tail NMOS injection current Tail PMOS injection current 31

32 Power Consumption and Phase Noise Power consumption: 2 1 One ring-oscillator stage: PStage CVDD f Inj 2n 1 2 CILFD: PStage 2CVDD f Inj The power consumption is independent to the division modulus (# of ring-oscillator stage). Phase noise: The phase noise of CILFD is mainly determined by the phase noise of injection signal. PN ( CILFD) PN ( Incident ) 10log Modulus No. 2 From top to bottom (1) free running CILFD, (2) incident signal, and (3) locked CILFD 32

33 Measurement Results* Chip Photo Odd-Modulus Summary Table Divide-by-3 Divide-by-7 Free Running Frequency 1.15 GHz 540 MHz Locking -4 dbm Input Power 1.2 ~ 4.9 GHz 1.4 ~ 4.4 GHz Power Consumption@4.5 GHz Frequency 0.74 mw 0.88 mw Power Consumption@1.5 GHz Frequency 0.31 mw 0.36 mw Core Area µm µm 2 Comparison Table Chip Photo Even-Modulus Ref This Work [8] [9] [10] Technology 0.18µm CMOS 0.18µm CMOS 0.13µm CMOS 0.18µm CMOS Div. Ratio Input Power (dbm) -4 0 NA Locking Range (GHz) 1.2 ~ ~ ~ ~ ~ ~ 1.22 Power (mw) ~ *Yung-Chung Lo, Y.-H. Hwang, J. Silva-Martinez, Low-power, wide-locking-range complementary injection-locked frequency dividers and their applications, to be submitted to IEEE JSSC.

34 Outline Noise Analysis and Models of VCOs Injection-locked Techniques Quadrature VCOs AMSC-TAMU 34

35 Generation of Quadrature Signal IQ mixing in RF frond-end (Image Rejection) SSB mixer CDR phase detector Implementation: 4-stage differential Ring Oscillator AMSC-TAMU 35

36 LC-Based Quadrature VCO Active device coupling (Transistor coupling) Fast settling and locking Smaller phase error Worse phase noise More power consumption Passive component coupling (Transformer, Cap, Ind) Better phase noise No power penalty Smaller locking range and slow locking Large phase error Area penalty AMSC-TAMU 36

37 Direct Transistor Coupling Bottom-series PN: Power: 16 ma from 1.3 V supply Phase error < 0.6º Oscillation frequency : 2 GHz 0.35 µm CMOS technology Parallel Coupling* Top-Series** Bottom-Series*** ** A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi. A 900MHz CMOS LC-Oscillator with Quadrature Outputs. In Proc. ISSCC 1996, pp , February * P. Andreani. A Low-Phase-Noise, Low-Phase-Error 1.8 GHz Quadrature CMOS VCO, in IEEE ISSCC Dig. Tech. Papers, 2002, pp *** P. Andreani. A 2GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6º phase error. Proceedings of the 28th European Solid-State Circuits Conference, pp , Sept,

38 Transformer Superharmonic Coupling (1) fo: 4.88GHz PN: -125 Tuning Range: 13% Power: 22 mw 2.5 V power supply 0.25 µm CMOS technology * S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp , Jul

39 Transformer Superharmonic Coupling (2) * C. W. Yao and A. N. Willson, A phase-noise reduction technique for quadrature LC-VCO with phaseto-amplitude noise conversion, in IEEE ISSCC Dig. Tech. Papers, 2006, pp

40 Capacitive Common-Source Coupling Improve PN? fo: 2 GHz PN: -124 dbc/hz@1mhz Tuning Range: 18% Power: 3 mw 1.5 V power supply 0.25 µm BiCMOS technology * B. Soltanian and P. Kinget, A Low Phase Noise Quadrature VCO Using Capacitive Common-Source Coupling, IEEE ESSCIRC2006, pp

41 QVCO Design Example LDO L Tank L Tank 6-Bits Cap Bank 6-Bits Cap Bank Q+ Q I I+ V ctrl C Vara C Vara V ctrl C Vara C Vara C Fix C Fix C Fix C Fix V Bias V Bias V Bias V Bias M Diff M Diff M Diff M Diff V S1 L Filter V S2 C Filter C Filter V Bias * S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp , Jul

42 42 Limitation: Bimodal Oscillation Bi-modal oscillation: One biasing condition has two possible oscillation frequency and two phase sequences Uncertain band selection Im I Gmc iv G I mc Im I Q o LC ivi R p o, o I Gmr V G I mr 1 I R VI R θ Tank p Re I Gmr V G I mr θ Tank 1 I R VI R p Re I Q o LC ivi R p o, o I Gmc iv G I mc Phasor Diagram: Bi-modal Oscillation Linear QVCO Modal

43 43 Phase Shift in Coupling Path Phase-shifted coupling path: Eliminate bi-modal oscillation Improve phase noise Improve phase accuracy I+ I- Q+ Q- Q- Phase Phase Q+ I+ Phase Phase I- Sifter Sifter Sifter Sifter M Gmc M Gmr M Gmr M Gmc M Gmc M Gmr M Gmr M Gmc Stage-Q I Gmr I Gmc I Gmr I Gmc node-q V Q G mc Phase Shifter Parallel QVCO with Phase Shift C p Lp R p G mr Im Im -1 φ I Gmc I LC Phase Shifter I Gmc node-i G mc I Gmr I R V I I LC I R Re I Gmr θ Tank Re G mr R p L p C p I Gmr φ θ Tank φ I R I LC I Gmc Stage-I Linear QVCO Model with Phase Shift Phasor Diagram (phase shift eliminates bi-modal oscillation)

44 44 Phase Accuracy Simulation Adding phase shift desensitizes the phase errors to mismatches Large coupling ratio preferred for reducing phase error Phase Error (Degrees) Phase Error due to 0.5% Δω o m=0.2 m=0.4 m=0.6 m=0.8 Phase Error (Degrees) Phase Error (Degrees) Phase Error due to 2% Δ Gmr Phase Shift (Degrees) m=0.2 m=0.4 m=0.6 m=0.8 Phase Error due to 2% Δ Gmc m=0.2 m=0.4 m=0.6 m= Phase Shift (Degrees) Phase Shift (Degrees)

45 45 Solution 1: Capacitive Source Degeneration Coupling* CSD Phase Shift CSD QVCO with Phase Shift Excellent Phase Accuracy Linear CSD QVCO model *H. Tong, S. Cheng, Yung-Chung Lo, A. I. Karsilayan, and J. Silva-Martinez, An LC quadrature VCO using capacitive source degeneration coupling to eliminate bi-modal oscillation, IEEE Transactions on Circuits and Systems I: Reg. Papers, to be published, October 2012.

46 46 Solution 2: Dynamic Current-Clipping QVCO Dynamic current-clipping coupling Excellent phase noise Inject current/noise at less sensitive timings Excellent phase accuracy І ІІ ІІІ IV Q N Q p t Large coupling ratio I N I p Q P B0 B1 B2 B3 Q N I P B0 B1 B2 B3 I N t I P I Gmcp M Cup 4-Bit Cap Bank I Gmcn I N M Cup Q N M Cup 4-Bit Cap Bank M Cup Q P І I Gmcp Output Waveforms i o =0 ІІІ i o =0 I N M Cdn VC M Cdn I P Q P M Cdn VC M Cdn Q N on I P i n off I P t R S M Gmr M Gmr R S R S M Gmr M Gmr R S off I N I Gmcn on I N in I Tail I Tail t Current-Clipping QVCO Noise Analysis Operation

47 47 Measurement Results** Technology (μm) Comparison Table Frequency (GHz) Supply Voltage (V) Power (mw) Phase Noise (dbc/hz) FoM (dbc) 2008 MWCL [2] CMOS @1MHz JSSC [3] CMOS @1MHz CSD QVCO [4] CMOS @3MHz 176 This work CMOS @1MHz 189 Output Waveform Chip Photo Phase Noise 0.3 mm 0.9 mm **Yung-Chung Lo, Jose Silva-Martinez, A 5-GHz CMOS LC Quadrature VCO with Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy, submitted to IEEE JSSC.