Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band Federico Pepe, Student Member, IEEE, Andrea Bonfanti, Member, IEEE, Salvatore Levantino, Member, IEEE, Carlo Samori, Senior Member, IEEE, and Andrea L. Lacaita, Fellow, IEEE Abstract Flicker noise up-conversion in voltage-biased oscillators can be effectively suppressed by inserting resistances in series to the drain of the transconductor MOSFETs. This solution avoids the degradation of the start-up margin and the adoption of area-demanding resonant filters with proper tuning. This paper presents a detailed theoretical analysis of 1/f noise up-conversion and quantitatively addresses the impact of two major contributions, namely the Groszkowski effect and the loop delay caused by stray capacitances at the drain node of the transistors. A simple flow for the design of an oscillator with suppressed flicker noise up-conversion is presented which is based on first-order closed-form formulas. Finally, theoretical estimates are compared to experimental results on a 65-nm CMOS VCO covering the GHz band. Index Terms Cyclostationary noise, flicker noise, harmonic distortion, impulse sensitivity function (ISF), oscillator nonlinearity, phase noise, voltage-controlled oscillator. I. INTRODUCTION CLOSE-IN phase noise in CMOS LC oscillators is largely dominated by flicker noise up-conversion. Since sub-micrometer devices feature noise corner frequency well beyond 1 MHz, the resulting phase noise is hardly mitigated even if the VCO is placed inside a phase locked loop (PLL). In fact, the PLL loop bandwidth is usually limited to khz [1] to filter out noise from other blocks (e.g., reference, divider and modulator) thus making the phase noise a limiting factor in many applications [2]. Therefore, in the last decade extensive efforts have been devoted to understanding and minimizing mechanisms of flicker noise up-conversion [3] [22]. In this perspective, two challenges have been faced: i) the nonlinear and time-varying nature of oscillators, which makes difficult to find a theoretical explanation to experimental phase-noise performance; ii) the presence in VCO topologies of many noise sources. A first practical step to minimize phase noise is therefore to simplify the VCO circuits. For example, the current source of the traditional differential topology can be removed, thus resorting to the voltage-biased topology (also known as Van der Pol oscillator) [6], [23] depicted in Fig. 1(a). Although this topology is known to be in general more sensitive to voltage-supply variations than the current-biased one, noise associated to the supply voltage can Manuscript received May 23, 2012; revised April 04, 2013; accepted July 03, Date of publication July 29, 2013; date of current version September 20, This paper was approved by Associate Editor Jacques C. Rudell. The authors are with the Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy ( bonfanti@ elet.polimi.it). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /JSSC Fig. 1. Double cross-coupled voltage-biased oscillator: traditional implementation (a) and topology with added drain resistances. be mitigated by adopting large-area transistors in the voltage regulator and bandgap-reference circuits. Thus, in practice, the dominant contributors to phase noise are the transconductor active devices whose flicker noise is up-converted via three mechanisms: 1) amplitude to phase noise conversion due to nonlinear tank varactors [4] [7]; 2) amplitude to phase noise conversion due to nonlinear transconductor parasitic capacitance [24]; 3) modulation of the harmonic content of the output voltage waveform, i.e., Groszkowski effect [9] [15], [25]. The first contribution can be minimized by using a bank of digitally-switchable capacitors. This solution drastically reduces the tank capacitance nonlinearity, without impairing the overall VCO tuning range [18]. The second contribution can be made negligible by adopting small-area transistors. In addition, the voltage-biased topology is intrinsically less prone to amplitude modulation since the transconductor nonlinearity clamps the oscillation amplitude to voltage supply reducing amplitude noise [26]. In practice, the modulation of the harmonic content is by far the dominant up-conversion mechanism in scaled-technology voltage-biased VCOs [25], [26]. Thus, effective mitigation of the phase noise can be attained by increasing the tank quality factor up to the limit set by the available technology options for the reactive components of the integrated LC tank. Moreover, further improvements can be obtained by: 1) linearizing the transconductor either by reducing the transistor width or by adopting resistors in series to transistor sources [10], [11], [25]; IEEE

2 2376 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER ) using a resonant filter at the transistor sources [8], [27]. The former solution reduces harmonic generation and therefore the Groszkowski effect but at the expenses of excess gain and start-up margin. This solution is explained and assessed in [25], where the authors quantitatively evaluate the phase noise in a voltage-biased oscillator taking into account the cyclostationary nature of the noise and relate the flicker noise up-conversion mechanism to transconductor nonlinearity and oscillator harmonic distortion. The second technique requires a LC filter tuned to twice the oscillation frequency. In practice, a tuning mechanism is required, especially if the VCO has to cover a large frequency band. In addition, non negligible silicon real-estate is needed to integrate the filter inductor. To circumvent these limitations, an alternative topology was proposed in [19] where resistors are inserted at the transistor drains, as depicted in Fig. 1(b). It has been shown that the circuit reaches remarkable phase noise suppression, avoiding resonant solutions and the corresponding area penalties. Moreover, since the resistors are at the MOSFET drains, the start-up margin is not degraded. In addition, numerical simulations showed the potential to highly suppress the noise up-conversion by tailoring the resistor values. As the resistances are increased, the phase noise first decreases, reaching a minimum,andthen it rises again. In [19], an intuitive and heuristic justification of this behavior was proposed. In this paper, the analysis is revised and a quantitative framework is introduced to explain the peculiar up-conversion mitigation reached in the circuit in Fig. 1(b). The paper is organized as follows. Section II briefly recalls the up-conversion mechanism acting in a voltage-biased topology and its quantitative description, while in Section III the analysis is applied to the proposed oscillator topology. The explanation for the phase-noise dependence on the resistance value is provided in Section IV. Section V is devoted to comparing theory, simulations and experimental results for the 65-nm CMOS VCO previously reported in [19], while Section VI provides the design guidelines to implement a VCO with reduced flicker-induced phase noise. The conclusions are drawninsectionvii. II. UP-CONVERSION MECHANISM IN TRADITIONAL VOLTAGE-BIASED OSCILLATORS Fig. 1(a) shows a classic double cross-coupled voltage-biased oscillator. The analysis of phase noise in this classical topology has been carried out in [25] and it will be briefly recalled in this section. Due to large-signal periodic time-variant regime, the flicker noise current sources become cyclostationary. From the viewpoint of second-order statistics, the calculation of phase noise contribution of such noise generators can be greatly simplified if the noise process is described as a stationary noise process multiplied by a periodic modulating function [28], as depicted in Fig. 2. This is the case of the current noise of the transistor in Fig. 1(a). Following the simple SPICE model [29], the power spectral density of can be written as: (1) Fig. 2. Schematic block diagram describing the generation of phase noise from the modulation through of a stationary process. where is a process-dependent constant, the specific oxide capacitance, the MOS channel length, while is given by: where is the transistor channel current and an exponent ranging between 1 and 2. By means of the impulse sensitivity function [30], it is then possible to calculate the output phase shift induced by a single tone of the stationary noise process: where is the maximum charge displacement taking place during the oscillation period across the tank capacitor and the ISF associated to the noise current generator 1. The ISF can be reasonably approximated by its fundamental harmonic [25], [31]: where is a phase shift that prevents the first harmonic of the ISF to be perfectly in quadrature with respect to the output voltage. Under this assumption, the phase noise is only due to the two current tones up-converted around the fundamental frequency. Denoting with and the magnitude and the phase of the first harmonic of, respectively, the Single- Sideband-to-Carrier Ratio (SSCR or )isequalto[25]: 1 In the original definition of ISF in [30], the impulse phase response is normalized with respect to the charge displacement at the node of interest. Normalizing with respect to the maximum charge on tank capacitor allows to directly compare the phase sensitivity of two nodes using the corresponding functions. (2) (3) (4) (5)

3 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2377 The overall phase noise should be computed by summing-up all the contributions, formally similar to (5), arising from all the noise sources. Referring to the oscillator in Fig. 1(a), all the flicker noise sources can be taken into account by substituting in (5) with: and being the flicker noise parameters of NMOS and PMOS, respectively. Equation (5) suggests that the phase noise depends on the difference between two key phase shifts, and. The smaller the difference between these two phase shifts, the lower the close-in phase noise. As shown in [25], both phases are determined by the transconductor nonlinearity, thus by the oscillator excess gain,, being the small-signal transconductance of the double crosscoupled differential pair. This parameter is usually set between 2 and 4 by properly sizing the transistor widths to assure a reliable start-up of the oscillator. By assuming the same threshold voltage for both types of transistor and that PMOS and NMOS widths are adjusted to balance the different mobility (i.e., ), is equal to the transconductance of a single MOSFET and the excess gain can be expressed as: In [25], closed-form expressions of the two phases and for the traditional voltage-biased oscillator have been derived: In [25] it has been demonstrated that a phase shift of the ISF can also arise due to the presence of non-linear capacitances, which can cause amplitude to phase noise conversion. However, in scaled technologies like the 65-nm adopted in the present work, the modulation of transconductor parasitics has a negligible impact on the ISF phase shift, which is thus mainly determined by the distortion effect. In conclusion, (8) and (9) suggest that both phases are functions of excess gain and quality factor, which set the oscillator nonlinearity, and they will be adopted in the following to provide a quantitative insight of the proposed phase-noise suppression technique. III. VCO WITH SUPPRESSED PHASE NOISE Let us now consider the VCO topology in Fig. 1(b) with resistors at the transistor drains. If the voltage drop due to these resistors is lower than the threshold voltage,, when the circuit is balanced (i.e., at the oscillator start-up), the transistors are in saturation and the small-signal transconductance of the differential pair is not affected in practice. In fact, considering (6) (7) (8) (9), the overall transconductance of the double-coupled pair results: (10) being the channel-length modulation factor and the ohmic drop across the drain resistors, once.thus, the excess gain of the proposed oscillator in Fig. 1(b) mildly depends on the added resistors, its dependence being limited to the channel-length modulation 2. For the 1.2-V supply 65-nm CMOS technology considered in this paper, and. Thus, even considering a voltage drop as large as the threshold voltage, the reduction of excess gain is limited to a factor of about 1.3. As far as the flicker-induced phase noise concerns, the output phase shift induced by the cyclostationary noise current of transistor in Fig. 1(b) can be estimated as: (11) In (11), is the equivalent current noise source that must be placed across the tank to account for the same phase contribution of. This approach allows to evaluate the phase shift once the tank-referred ISF,,isknown.Theratio in (11) is a periodic small-signal transfer function and will be denoted as. Moreover, from (11) it immediately follows that: (12) Now the question is how the equivalent current noise can be evaluated. For the noise current generator,the system is linear although time-variant. Thus, the equivalent current can be evaluated as the current flowingintheequivalent Norton short circuit between the output nodes. Since the circuit has a periodic steady state and being the output voltage harmonic for relative high-q oscillator, the short circuit can be substituted by a sinusoidal voltage generator with the same oscillation amplitude. In the traditional voltage-biased oscillator topology, is approximately equal to. In fact, the impedances of the two branches ( and )infig.1(a)arealmostthe same for any operating bias point along the oscillation cycle. Thus, about half the noise current injected at the drain node will flow through the equivalent short circuit between the output nodes. This approximation corresponds to assuming in (12), thus justifying (4). 2 In the case of resistors added at the transistor source nodes, the overall transconductor can be estimated as, being the transconductance without source degeneration. This approximation is valid if the ohmic drop across the resistor is much lower than the transistor overdrive voltage without source degeneration, i.e.,.

4 2378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Let us now apply the analysis to the VCO topology in Fig. 1(b) with resistors at the transistor drains. Also in this topology, as it will be shown in the following, the main contribution to phase noise derives from the first harmonic of (see (5)). Furthermore, being almost sinusoidal, it results from (12:) (13) being the average value of the function.thus,it is likely that the amplitude of is a function of the drain resistor value. In fact, during the oscillation cycles, when the voltage at the node approaches the negative rail, enters the ohmic region. If the drain resistor is larger than the transistor channel resistance, most of the current noise of the device is expected to re-circulate within the channel, not reaching the tank, with beneficial impact on phase noise. The larger the resistor value, the lower and the magnitude of. On the other hand, these resistors together with the transistor stray capacitances may cause signal delays within the oscillator loop that can affect the noise up-conversion mechanisms by changing the phase shifts in (5). In order to have reference values, phase noise simulations were performed on the circuit in Fig. 1(b) designed in a 65-nm technology. The resonance frequency was set to 3.6 GHz by using, and,leadingtoa quality factor of 10. The transistors were sized to have an excess gain,, of 2.8, enough to guarantee a safe start-up. Since, the stray capacitance at the drain of the NMOS transistors,, is half the PMOS capacitance,.therefore, to equalize the two delays the choice was to set and.thedelay will be denotedinthefollowingas. Fig. 3 shows the phase noise at 1-kHz offset computed by using both SPICE and BSIM4 flicker noise models for different values of. At 1-kHz offset, flicker-induced phase noise is the dominant contribution. For both noise models, by increasing the phase noise decreases reaching a minimum at (SPICE)orat (BSIM4) corresponding to the white noise floorofabout.itisevident that the specific noise model slightly shifts the optimum resistance value of noise suppression but the general feature of the phase noise trend is retained and deserves to be better understood. In fact, it is unlikely that a complete noise cancellation can be explained only by. This value is expected to decrease as increases but there is no clear reason why, in some cases, it should become nil. The sine function in (5) suggests instead that a cancellation may occur when the phase shifts within its argument cancel out. Their values as a function of the drain resistor are shown in Fig. 4 (solid lines). For,theexcess phase and in the SPICE flicker noise model are equal. For this resistor value, the phase noise resulting from the flicker current noise tones folded around the fundamental frequency is expected to be nil. Indeed, the flicker-induced phase noise suppression in Fig. 3 happens for a slightly larger value of. Fig. 3. Flicker-induced phase noise evaluated at 1-kHz offset from the carrier. The simulation results with both SPICE and BSIM4 models are shown. Fig. 4. and as functions of the drain resistance for the circuit in Fig. 1(b). Dashed lines refer to the case without parasitic drain capacitances. Moreover, once the resistor has been sized, the reduction of phase noise is effective even if the oscillation frequency is changed. Fig. 5 shows the phase noise at 1-kHz and 1-MHz offset for the novel oscillator topology in Fig. 1(b) when its oscillation frequency is tuned between 3 and 4 GHz, corresponding to a tuning range equal to 28%. The phase noise at 1-kHz offset is close to along the whole tuning range. Fig. 5 also shows that the proposed technique is not detrimental in terms of phase noise, since it causes an increase always lower than 2 db. The following section will be therefore devoted to analyzing more in depth the circuit and the impact of the component values on both flicker-induced and phase noise. In addition, a quantitative explanation for the opposite trends of and versus will be presented. IV. CIRCUIT ANALYSIS A. Effect of Loop Delay on ISF First, let us consider the transistor at the bottom-left side in Fig. 1(b). When the differential output is negative (i.e., the

5 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2379 Fig. 5. Phase noise at 1-kHz and 1-MHz offset for the oscillator in Fig. 1(b) whentunedbetween3and4ghzfor and.thebsim4 flicker noise model is adopted. voltage at the node is lower than the voltage at the node ), the device enters the ohmic region. The larger,the larger is the voltage drop at the drain node and the deeper is the ohmic region. Fig. 6(a) shows the dependence of on the phase compared to. Note that as becomes ohmic, i.e., for negative values of the differential output voltage, approaches zero, in agreement with the idea that the resistance forces most of the current noise to re-circulate within the transistor. This consideration is confirmed by looking at the function showninfig.6(b)fordifferent values of the resistance :for, when the transistor is in deep ohmic region, the value of falls down preventing the current noise to reach the tank. By increasing, the effect becomes stronger and the magnitude of the first harmonic of decreases (Fig. 7(a)), although its value is only reduced from 0.5 for to 0.38 for. On the other hand, the drain resistance has an impact on the phase of both and.fig.7(b)showsthe excess phase of the first harmonics of the two sensitivity functions. The zero phase value corresponds to the perfect quadrature with respect to the output voltage. The two phases start from a positive value determined by the nonlinearity of the system [25]. For, is set by (8). However, as increases both the first harmonics of and begin to lag, thus suggesting that, by increasing, an additional delay due to and stray capacitances on the transistor drain nodes comes into play, thus modifying the term appearing in (5). To strengthen this theory, the phases and have been computed removing the parasitic capacitance at the drain node of the transconductor transistors. The results are shown in Fig. 4 (dashed lines). The two phases weakly depend on, thus confirming that the oscillator nonlinearity is mildly dependent on the added drain resistors. A more quantitative insight can be gained by studying the oscillator model in Fig. 8 where the transconductor is followed by a delay block.asimplified analysis may be performed by decoupling the effects of the added delay and transconductor nonlinearity. The first step is to consider the transconductor linear, thus taking and Fig. 6. and (a) and function (b) referred to the bottom-left transistor in Fig. 1(b) as functions of the output voltage phase for three different values. refers to the differential output voltage. Fig. 7. Magnitude (a) and excess phase (b) of first harmonics of and as functions of. Dashed lines refers to the added delay phase,., and compute the ISF across the tank,, relating the phase to the loop delay. To this purpose, Fig. 9(a) shows the phasors of the fundamental harmonic of the voltage waveform across the tank and of the current delivered by the transconductor. In addition, it highlights two current noise tones injected across thetankatanoffset from the carrier with a initial

6 2380 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Fig. 8. Behavioral model of the oscillator with added delay block,,inthe feedback path. Fig. 10. as function of added phase delay,, for the behavioral oscillator of Fig. 8. The dashed line refers to the estimate of given by (15). Fig. 9. Injection of two current tones at an offset from the carrier in the case of loop delay,, and linear transconductor (a). The phase of the current is left unchanged if the small tones are applied with initial phase equal to - (b). phase. Due to noise injection, the phase of the output voltage is modulated at a frequency according to: (14) Equation (14) emphasizes that for the two current tones do not modulate the phase of the output voltage. The same condition of no output voltage modulation can be identified referring to Fig. 9(b). Note that if the noise tones do not modulate the phase of the current and therefore no phase modulation of the output voltage arises, if AM-to-PM contribution is neglected. By equating the two conditions, and it follows that the ISF excess phase follows the loop delay. Regarding the impact of transconductor nonlinearities, (8) suggests that they cause a positive phase shift between the first harmonic of the ISF and the output voltage. Therefore, by adding the two contributions, may be taken as: (15) The approximation has been verified by means of behavioral simulations. The model in Fig. 8 has been implemented in a Cadence environment and linear time-variant simulations (PSS and PAC analyses) have been performed in order to evaluate the phase of the ISF first harmonic. The transconductor was taken with a third-order nonlinearity, i.e.,.in agreement with parameter values met in realistic RF circuits, the tank quality factor and the excess gain,, have been set equal to 10 and 3, respectively. Fig. 10 shows the dependence of on the phase delay, which is in good agreement with (15). The excess phase,, is approximately 3 for and it decreases almost linearly as the added delay increases as predicted by (15) (dashed line in Fig. 10). The dependence of the excess phase on added delay given by (15) holds well also if applied to the oscillator in Fig. 1(b). In fact, both and decrease following the increasing loop delay, which can be quantified in a first order approximation as (Fig. 7(b)). B. Effect of Loop Delay on Noise Modulating Function Let us now analyze the impact of on the noise modulating function andonthephaseshiftofitsfirst harmonic. shows the opposite dependence on drain resistor value with respect to (see Fig. 4, solid lines). By increasing,the first harmonic of progressively leads the voltage waveform even if the current flowing through the branch of the transconductor features an increasing phase delay. A qualitative explanation of this trend can be derived by looking at the simulated voltage and current waveforms in Fig. 11. Fig. 11(a) shows the voltage waveforms at the drain and gate nodes of the transistor in Fig. 1(b), while Fig. 11(b) shows the transistor channel current,, and the total current,, flowing through the drain resistor. The latter also includes the current flowing through the stray capacitance. The voltage and current waveforms for are also shown for reference. Due to the delay at the drain node, the drain voltage and are delayed with respect to the case.notealso that by increasing the value, the transistor channel current, which has a symmetric waveform for,showsa first peak higher than the second one. In fact, the current peak is reached at the boundary of the saturation region, i.e., when the transistor enters or leaves the ohmic region (see Fig. 12). This happens when the gate-drain voltage is close to the threshold voltage, i.e., when.thus,due to the delay at the drain node, the condition is verified for two different gate voltage values and the first current peak is higher since corresponds to a slightly larger gate voltage. It follows that by increasing the delay, the first harmonic of leads the driving voltage at the gate node and, which can be approximated by the phase of the first harmonic of the transistor channel

7 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2381 being the phase delay at the drain node equal to. Thus, in the expression of the drain voltage we neglect the ohmic drop across the resistance. Under these approximations, the transistor channel current when is ohmic can be expressed as: From (16), (17) and (18) the phase of the first harmonic of can be easily derived as: (18) (19) Fig. 11. Voltage and current waveforms of in Fig. 1(b). The dashed lines refer to the case without delay, i.e.,. For the considered technology, being and,itresults. Finally, taking into account the effect of the transconductor nonlinearity, which sets the phase of the transistor current also in the case (see (9)), the phase of the modulating function can be approximated as: (20) Equation (20) suggests that the phase of the modulating function depends on the added loop delay. As increases, departs from the negative value set by the Groszkowski effect, eventually becoming positive. For ranging from 0 to and considering a parasitic capacitance at the NMOS drain node of 7 ff, the estimated phase increases by 2.7,ingoodagreement with the simulation result of 3.5 (see Fig. 4). Fig. 12. Simplified voltage and current waveforms of the transistor in Fig. 1(b). The transistor current peak occurs at the boundary of the ohmic region. Due to the delay of the voltage waveform at the drain node, the condition is reached for two different gate voltage values: the first occurs at a larger gate voltage, thus implying a larger current. current [25], moves towards more positive values as shown in Fig. 4, eventually reaching the crossover with. The phase can be quantified resorting to first-order approximations:,being the phase of the first harmonic of the transistor channel current, ; the phase of the transistor channel current is determined when the MOS is in ohmic region, as depicted in Fig. 11(b); the gate and drain voltages can be expressed as: (16) (17) C. Drain Resistor Sizing The analysis reported in the previous sections shows that both phase shifts and depend on the added delay.byassuming and approximating the modulating function with the transistor channel current, from (15) and (20) the condition can be expressed in terms of added loop delay and excess gain: (21) It results that the drain resistance value that allows to suppress the flicker noise up-conversion is: (22) For the considered oscillator with,, and, the optimum drain resistance results, close to the simulated value (see Fig. 4). Other simulations were run by adding extra capacitances of 15 ff at the drain of NMOS transistors and 30 ff at the drain of p-mos- FETs. Fig. 13(a) shows the two simulated curves of and as functions of,comparedtothetwophasesinthecircuit without extra capacitances. It turns out that by increasing the capacitance value, the phase drops more rapidly and, on the opposite, grows faster, as predicted by (15) and (20),

8 2382 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Fig. 13. and (a) and phase noise at 1-kHz offset (b) for an added capacitance of 15 ff at NMOS transistor drains (30 ff at PMOS drains), as functions of. For comparison, also the case without added capacitance is shown. Fig. 15. Phase noise at 1-kHz offset as function of the drain resistance. Solid line refers to the SpectreRF pnoise simulation while dashed line refers to the contribution. Triangles and squares refer to the phase noise estimated considering only the first harmonic and all the harmonic terms of the ISF, respectively. frequency is changed, both the added loop delay and vary, being. This consideration suggests a slight dependence of the optimum resistance value on the oscillation frequency and explains why the proposed method works over a wide tuning range, as shown in Fig. 5. Fig. 14. Drain resistance corresponding to for a capacitance added at the NMOS drain nodes. For the PMOS transistors isaddedatthedrainterminals.adrainparasitic capacitance of 7 ff is considered for the NMOS transistors (14 ff for p-channel FETs). D. The Effect of ISF High-Order Harmonics Fig. 15 shows the comparison between the simulated phase noise at 1-kHz offset (solid line) and its estimate (squares) using (5) and considering the simulated phases and in Fig. 4. As already pointed out, the minimum of the phase noise occurs at a slightly higher resistance value. To fully explain the numerical results, the impact of higher-order harmonics should be taken into account, since is not harmonic due to the distortion introduced by the function. Thus, the phase noise can be written as in [25]: respectively. The condition is reached for, while the estimated optimum resistance is very close, being. This shift of the noise minimum towards lower values is confirmed by the simulated phase noise at 1-kHz offset (Fig. 13(b)). Fig. 14 shows the drain resistance corresponding to for different values of added capacitance,while refers to the total capacitance at the NMOS drain node, being.forcomparison,fig.14alsoshows the curve corresponding to the estimated optimum resistance given by (22) that confirms the validity of the quantitative analysis so far reported. Actually, the dependence of the optimum value of on excess gain is less than quadratic. This happens since the phase of the modulating function depends more weakly on with respect to the prediction given by (20). Thus, if the oscillation (23) where,, and are the magnitude and the phase of the harmonic of and. In (23), the functions for NMOS and PMOS transistors have been taken the same. This assumption is reasonable since all transistors are electrically equivalent and the added delay on each drain node has been tailored to be equal. Fig. 15 (triangles) shows the phase noise at 1-kHz offset obtained by properly summing-up all the contributions as in (23). The correlated contributions arising from the higher-order harmonics shift the phase noise suppression at (for SPICE flicker noise model) where the overall phase noise becomes limited by the contribution (dashed line in Fig. 15). The estimate compares very well with the simulation results.

9 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2383 TABLE I 1-MHZ NOISE CONTRIBUTIONS Fig. 16. Effective functions for the thermal noise current generator of in the oscillator in Fig. 1(a) and in the improved topology of Fig. 1(b). Both functions are normalized to the same value to make the comparison fair. E. Impact of Drain Resistors on Phase Noise The adoption of resistors at the transistor drain nodes is not detrimental in terms of the phase noise. In fact, the added drain resistors reduce the oscillation amplitude and are sources of white noise, but, at the same time, they prevent the transistors to load the tank. Their impact on phase noise will be quantitatively addressed in the following. As far the oscillation amplitude concerns, it can be estimated in the proposed oscillator as [19]: (24) where and are the resistances of the transistors in deep ohmic region. Clearly, the oscillation amplitude is reduced with respect to the traditional oscillator by a factor of (25) Considering,, and, this factor is equal to 1.4 and would cause an increase of phase noise of about 3 db. Additionally, the drain resistors contribute to phase noise with their noisy current. However, this noise is injected only when the corresponding transistor is in deep ohmic region. When this happens, the corresponding ISF (i.e., the ISF for a generator placed across the resistor terminals) is low since it occurs at the negative peak of the differential output voltage. On the other hand, at the zero crossing of the output voltage, the transistors are in saturation and no current noise is injected into the tank. On the other hand, the drain resistor has a positive effect on transistor noise, since it makes the transistor current noise to re-circulate into the transistor itself when it is ohmic. In other words, the resistor prevents the transistor to load the resonator and the noise current to reach the tank. This qualitative analysis is confirmed by observing Fig. 16 that shows the effective functions [30] corresponding to the white noise current generator of the transistor in the oscillator of Fig. 1(a) and in the improved topology of Fig. 1(b) 3. When the resistor is added at the transistor drain node, the effective is lower, in particular when the MOS is in ohmic region (for a phase around, being the differential output voltage a cosine), thus preventing to load the tank and to inject its current noise. To strengthen this theory, Table I shows the oscillation amplitude, the contributions to the output noise of both active and passive devices and the overall phase noise at 1-MHz frequency offset for the oscillators in Figs. 1(a) and 1(b) with. Simulation results show that the oscillation amplitude is reduced once the drain resistors are added at the drain nodes by a factor 1.4, as predicted by (25), leading to an increase of phase noise of about 2.7 db. However, the noise due to the transistor is almost halved, thus balancing the voltage amplitude reduction. Moreover, the noise added by the drain resistors is about one order of magnitude lower than the noise due to the active devices and tank loss resistor. This justifies the worsening of phase noise limited to only 0.6 db. V. MEASUREMENT RESULTS The proposed technique has been adopted in a 65-nm CMOS VCO, already presented in [19], covering the Italian 3.5-GHz WiMAX frequency band ( GHz). The VCO tank features a 4.55-nH inductor while the capacitance consists of two banks of 20 switched metal-insulator-metal capacitors and two thick-oxide MOS varactors. The tank quality factor is approximately set to 10 by the small-area inductor. In order to bias the oscillation voltage at the middle of the supply rails, the widths ofthep-andn-mosfetshavearatioof2.thesameratio applies between their drain parasitic capacitances. As a result, the drain resistors have been scaled accordingly. The transistor width was chosen to guarantee an excess gain larger than 2 over the whole tuning range. The drain resistors were sized to and to equalize the delays at the transistor drain nodes. The simplified schematic is depicted in Fig. 17. The VCO core is followed by a differential output buffer, which creates a disturbance at 3 The effective ISF,, is the ISF multiplied by the modulating function of cyclostationary noise (denoted as in [30]), i.e., in the case of white current noise, divided by the peak value of. In this case, both the effective functions have been normalized dividing the ISF by the maximum value of the function corresponding to the transistor for.

10 2384 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Fig. 17. Schematic of the implemented voltage-biased oscillator with drain resistors together with the output buffer. on the supply rail. Note that the noise from the buffer transistors could be up-converted as supply noise around,then further down-converted at by the VCO switching as amplitude noise across the tank, finally giving rise to phase noise. Thus, the network was added to filter out the signal at, avoiding any residual phase-noise contribution. The measured tuning range spans between 3.0 and 3.6 GHz with a maximum power consumption of 0.7 mw from the 1.2-V supply (excluding buffers). A VCO with identical topology but with no drain resistors was also fabricated as reference on the same die (see the inset of Fig. 18) 4. Fig. 18 shows the phase noise spectra of the two free-running VCOs at 3.57-GHz oscillation frequency. The modified voltagebiased oscillator outperforms the standard topology by about 9 db at 1-kHz offset. Furthermore, as expected, the phase noise of about at 1-MHz offset is not significantly degraded by the added resistors, leading to a Figure-of- Merit [32] of about 186 db. Fig. 19 compares the measured and simulated phase noise at 1-kHz and 1-MHz frequency offset along the tuning range in order to quantify both and contributions. Noise simulations have been run using BSIM4 model for both flicker and thermal noise and the parameters set by the technology specs. Simulation results compare reasonably well with experimental values over the extended GHz range. The experimental trend of the phase noise is well captured by simulations from 3.2 to 3.6 GHz even if the actual improvement ranges from 5 to 9 db, about 3 4 db less than the numerical expectations. In 4 Note that the resistors have a positive impact in terms of phase noise due to transconductor transistors, since they slightly reduce the oscillator nonlinearity lowering the effective power-supply voltage. However, the reduction of flicker-induced phase noise due to these resistors is of about 4 db. Both the implemented oscillators feature the network. the frame of flicker-induced phase-noise analysis, the agreement shown in Fig. 19 may be considered good taking into account the sensitivity of phase noise on the specific flicker noise model and the parameters spread. In fact, even adopting the same noise model, simulations performedondifferentcorners show a 6-dB variation of the phase noise at 1-kHz frequency offset for both the standard and the improved topology. However, the reduction of flicker noise up-conversion is confirmed also varying the process corner. Finally, the adoption of the drain resistor has a slight benefitin terms of reduction of low-frequency noise from power supply. In fact, the measured sensitivity from power supply, [6], varies from 10 MHz/V to 20 MHz/V along the tuning range for the implemented traditional VCO, while the sensitivity is slightly lower for the improved topology, being in the range 7 15 MHz. In fact, the low-frequency noise from power supply modulates the output voltage common mode and is up-converted by modulating the nonlinear capacitances at the output nodes and the bias voltage of the transconductor, thus its nonlinearity. Since the nonlinear capacitances have been drastically reduced in both oscillators and the nonlinearity is only slightly affected by adding the drain resistors, it is likely that the improved oscillator features a mildly lower power-supply sensitivity. Table II compares the performance of recently-published oscillators that aim to minimize phase noise by means of a new Figure-of-Merit whose definition is theoretically justified in the Appendix: (26) being expressed in ma. The presented VCO shows the best. Only the VCO in [27] has a higher but

11 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2385 Fig. 18. Comparison between measured phase noise for the standard oscillator (upper curve) and the proposed one (lower curve) at the upper-side of tuning range. In the inset, the microphotograph of the die. VCO1 and VCO2 refer to traditional and modified voltage-biased oscillators, respectively. up-conversion without degrading start-up margin and phase noise. The oscillator design can be based on the following steps: The minimum tank capacitance,, is chosen in order to satisfy the requirements on phase noise, i.e.,, [33] (27) being the maximum oscillation frequency and the transconductor noise factor. The minimum parallel loss resistance of the tank is determined as: Fig. 19. Measured phase noise at 1-kHz and 1-MHz offset over tuning range for the standard topology (triangles) and the proposed one (squares). Solid and dashed lines refer to the phase noise estimated by post-layout simulations on the oscillator with and without drain resistors, respectively. it features an off-chip high-q inductor and the suppression of noise up-conversion is obtained by means of a tail resonant filter, thus making the phase noise and its related varying along the oscillator tuning range. VI. DESIGN CRITERIA The analysis reported in the previous sections suggests the criteria to design an oscillator with reduced flicker noise (28) being the minimum oscillation frequency, and the overall transconductor is set to assure a reliable start-up at : (29) Assuming n- and p-channel MOSFETs sized in order to balance their different mobility, the n-mosfets can be designed with aspect ratio equal to: (30)

12 2386 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 TABLE II MEASURED PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY PUBLISHED LOW PHASE NOISE VCOS After determining the value of the parasitic capacitance,, at the drain of the NMOS transistors, the drain resistance is derived from (22) as: (31) which minimizes flicker noise upconversion. Clearly,itmustbe and in order to have the same delay at NMOS and PMOS drain nodes. The value of given by (31) must fulfill the condition, being the ohmic drop across the drain resistor at DC bias, which assures the transistor to be in the saturation region. If this condition is not verified, has to be increased in order to accommodate a smaller value of. As phase noise minimization is obtained thanks to a proper value of the delay introduced in the oscillator loop, the resistor value can always be kept low by choosing the appropriate value of. This option may be useful when high current consumption and low phase-noise oscillators is required. In this case, there may be no need of extra capacitances at drain nodes. In fact, the equivalent parallel tank loss resistance scales and transistor widths have to be accordingly increased to achieve the same excess gain, resulting into larger parasitics. To further demonstrate this point, we adopted the proposed technique to design a 3.6-GHz voltage-biased oscillator featuring 10 times higher power consumption with respect to the reference oscillator but with the same tank quality factor of 10. The drain resistors were sized as 35 and, preventing the transistors to enter the ohmic region at the start-up. Due to the higher current drawn by the VCO, the transistors were sized with 60 and. Thus, there was no need to add a capacitor at the drain nodes of the devices since the parasitic capacitance itself is sufficient to create the proper delay with the adopted resistors. The simulated phase noise at 1-MHz offset is 127 dbc/hz for both the classical voltage-biased oscillator and the proposed topology. In the region, the conventional oscillator features 42 dbc/hz at 1-kHz offset, while it reduces to 62 dbc/hz in the improved topology. VII. CONCLUSIONS By adopting resistors in series to the drain nodes of the transconductor transistors, the up-conversion of flicker noise in a voltage-biased oscillator can be effectively reduced. The resistors, together with the parasitic drain capacitance, introduce a delay in the loop gain shifting both the ISF and the current waveform of the MOSFETs. It follows that noise up-conversion can be properly reduced by judiciously tailoring the component values without degrading the start-up margin or adopting resonant filters. In this paper, a theoretical explanation and a quantitative analysis have been carried out addressing in details the different effects and a comparison has been made between numerical results and experimental measurements on a 65-nm CMOS VCO. Finally, the Figure-of-Merit for the flicker-induced phase noise,, is introduced allowing to compare oscillators featuring different oscillation frequencies and current consumptions. Adopting this, the presented oscillator outperforms other integrated VCOs with reduced flicker noise up-conversion. APPENDIX In this appendix, we provide a theoretical framework to the definition of the Figure-of-Merit for flicker-induced phase noise,, adopted in Section V. Although flicker-induced phase noise is of great concern in oscillators and can worsen the performance of the whole synthesizer, such a Figure-of-Merit has never been introduced in literature to compare different VCOs to the best of our knowledge. However, it is reasonable to assume that such a figure of merit has to be similar for the classical FoM derived for noise [32]. In fact, the phase noise is still a phase fluctuation, so

13 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2387 it is expected to scale as and with the power absorbed by the tank. On the other hand, flicker-induced phase noise is proportional to current, while white-induced one depends only on tank losses [34]. Equation (5), which expresses the phase noise in a general case, suggests that: phase noise is proportional to the flicker noise current tones up-converted around the fundamental carrier, i.e., (32) being the magnitude of the first harmonic of the transistor current. For simplicity, we have considered the exponent in SPICE flicker noise model and in (2) equal to 1. Only a small fraction of these noise components gives rise to a phase modulation (PM) of the output voltage, this fraction being proportional to the term in (5). Thus, the PM current noise components around the carrier have a power spectral density given by: (33) The PM current tones determine a phase modulation of the output voltage being multiplied by the lossless tank impedance, resulting in: (34) (35) The amplitude of the carrier is proportional to the tank loss resistance,,and,i.e., (36) Taking into account the above mentioned considerations, the flicker-induced phase noise can be written as: (37) The current flowing into the transistors and in the tank is proportional to the average current drawn by the power-supply,,i.e., (38) being the current efficiency of the oscillator which quantifies how much the oscillator is prone to convert the average power-supply current into a first-harmonic current to be delivered to the tank. Note that a similar argument has been adopted in [32] to derive the Figure-of-Merit for the phase-noise. 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Solid-State Circuits, vol. 43, no. 12, pp , Dec Federico Pepe (S 11) was born in Avellino, Italy, in He received the Master degree in electrical engineering from Politecnico di Milano in His Master research was focused on the investigation of the up-conversion of flicker noise in LC-tuned oscillators and on the design of a 3 4 GHz 65-nm CMOS technology VCO with reduced 1/f phase noise. He is currently pursuing the Ph.D. degree at the Politecnico di Milano, Italy. In 2010 he worked as an analog designer in Pegasus Microdesign, Arcore, Italy, involved in the design of LDOs and DC-DC converters for low-power applications. Andrea Bonfanti (M 09) was born in Besana Brianza (Milan), Italy, in He received the Laurea degree in electrical engineering and the Ph.D. in electronics and communications from the Politecnico di Milano, Italy, in 1999 and 2003, respectively. During his Ph.D. program, he studied the up-conversion of flicker noise into phase noise in bipolar and CMOS LC-tuned oscillator. From 2003 to 2008 he was a Postdoctoral Researcher at the Politecnico di Milano involved in the study and design of fully-integrated oscillators, RF frequency synthesizers, A-D converters and low-power analog and mixed-signal circuits for neural signal processing. During this period he was a consultant for ST-Microelectronics (Agrate Brianza, Italy), Accent (Vimercate, Italy) and the Center of Excellence for Research, Innovation and Industrial Laboratories (CEFRIEL), Milano, Italy. From 2008 to 2009 he had a post-doc position at the Italian Institute of Technology (IIT, Genova, Italy) where he was involved in the design of integrated circuits for neural signals acquisition in the framework of the Brain Machine Interface Project. Currently, Dr. Bonfanti is an Assistant Professor with the Dipartimento di Elettronica, Informazione e Biongegneria, Politecnico di Milano. He is coauthor of approximately 40 papers published in journals or presented to international conferences. Salvatore Levantino (S 99 M 02) received the Laurea degree (cum laude) and the Ph.D. in electrical engineering from the Politecnico di Milano, Milan, Italy, in 1998 and 2001, respectively. From 2000 to 2002, he was a consultant at Bell Labs, Lucent Technologies, Murray Hill, NJ, USA. Since 2005, he has been an Assistant Professor and subsequently Associate Professor of electrical engineering at Politecnico di Milano. In past years, he has contributed to the understanding of phase noise generation mechanisms in oscillators and frequency dividers and to the development of new design methodologies for radio-frequency front-ends and frequency synthesizers. He is coauthor of Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). His current research includes wireless transceivers, frequency synthesizers, and data converters. Dr. Levantino is as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II and he serves on the Technical Program Committee for the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Carlo Samori (M 98 SM 08) was born in He received the Laurea degree in electrical engineering in 1992, and the Ph.D. in electronics and communications at the Politecnico di Milano, Italy, in In 1996 he was appointed Assistant Professor and since2002heisassociate Professor of electronics at the Politecnico di Milano. He initially worked on high-speed low-noise front-end circuits for photodetectors, then in the areaofdesignandanalysisofintegrated circuits for communications both in bipolar and in CMOS technology. Among his works, he contributed to a time-variant theory of phase noise generation in LC-tuned VCO, he collaborated to the design of several low phase noise VCO in bipolar and CMOS technology. He has contributed to the design of fractional- and integer-n PLLs for multistandard WLAN applications. From 1997 to 2002 he was a consultant for Bell Labs, Murray Hill, NJ, USA (then Agere Systems). Currently, his research interests are frequency synthesizers and data converters. He is co-author of about 80 papers in international journals and conferences. In 2007 he published, as a co-author, the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press). He is a member of the Technical Program Committee of the IEEE International Solid-State Circuits Conference (ISSCC).

15 PEPE et al.: SUPPRESSION OF FLICKER NOISE UP-CONVERSION IN A 65-nm CMOS VCO IN THE 3.0-TO-3.6 GHz BAND 2389 Andrea L. Lacaita (M 89 SM 94 F 09) graduated in nuclear engineering in From 1987 to 1992 he was Researcher of the CNR (Italian National Research Council). Since 1992 he has been EE Professor at the Politecnico di Milano (Full Professor since 2000). He has been Visiting Scientist/Professor at the AT&T Bell Laboratories, Murray Hill, NJ, USA ( ) and the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA (1999). From 2006 to 2008 he served as Department Chair of the Dipartimento di Elettronica e Informazione and as a member of the Academic Senate ( ). He began his research activity on physics and technology of SPADs (Single Photon Avalanche Diodes) and related electronics. He contributed to the understanding of the ultimate performance and potentials of these detectors, pioneering their applications in the near-infrared. He investigated quantum effects in nanoscale MOSFETs and contributed to the development of characterization techniques and numerical models of nonvolatile memories, both Flash and emerging (PCM, RRAM). In the field of RF integrated circuit design, he devoted research activity to noise optimization of fully integrated VCOs and to designing novel PLL frequency synthesizers for multistandard terminals. Some of the results are described in the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). He is a coauthor of more than 250 papers published in international journals or presented to international conferences, patents, and several educational books in electronics. Dr. Lacaita has served on several scientific committees, including IEEE IEDM ( ), IEDM European Chair ( ), IEEE VLSI Symposium ( ), and ESSDERC (2005, 2007 to date).