Large-Signal Analysis of MOS Varactors in CMOS Gm LC VCOs

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST Large-Signal Analysis of MOS Varactors in CMOS Gm LC VCOs Ryan Lee Bunch, Member, IEEE, and Sanjay Raman, Member, IEEE Abstract MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D=S=B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary LC VCO using I-MOS varactors implemented in m CMOS technology. Index Terms CMOS integrated circuits, nonlinear circuits, oscillators, varactors. I. INTRODUCTION THE explosive growth in wireless communications has led to an increased demand for wireless products that are low-cost, low-power, and compact in size. Recently, there has been considerable interest in the use of CMOS technology to implement RF components such as low-noise amplifiers (LNAs), mixers, and voltage-controlled oscillators (VCOs) [1], [2]. The benefits include leveraging high-volume silicon CMOS fabrication capacity for RF products and the potential for achieving high-levels of RF/analog/digital integration, rapidly approaching single-chip system implementations [3]. VCOs are key components in frequency synthesizers for RF wireless applications. Differential approaches are typically required because these frequency sources are used to pump Gilbert-cell-type mixers. A standard approach for differential VCOs is the use of cross-coupled transistors to generate a negative resistance. The negative resistance generated by the cross-coupled pair should be sufficient to overcome the equivalent parallel resistance of the VCO tank circuit to generate the desired oscillation. These VCO circuits are known as LC-tank VCOs. In CMOS technologies, both cross-coupled nmos and cross-coupled pmos versions are realizable. A number of CMOS LC VCOs have been reported in the literature, e.g., [4] [8]. The complementary oscillator circuit is the result of using both pmos and nmos cross-coupled pairs in parallel Manuscript received March 28, 2002; revised April 17, This work was supported by the National Science Foundation under Award R. Bunch is with RF Micro Devices, Greensboro, NC USA ( rbunch@rfmd.com). S. Raman is with the Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA USA ( sraman@vt.edu). Digital Object Identifier /JSSC Fig. 1. Simple CMOS complementary 0G oscillator. to generate the negative resistance. This topology has been demonstrated to have reduced noise upconversion properties [9]. Fig. 1 shows a simple CMOS complementary oscillator. The tank capacitance is some combination of fixed and tunable (varactor) capacitances. Because the same bias current flows through both the pmos and nmos devices, the negative resistance can be twice as large for the same power consumption. The bias current source, often referred to as the tail current source, provides the designer with a means to make the best compromise between phase noise and power dissipation. A number of complementary VCOs have been reported recently in the literature [10] [12]. There are a number of options available to RF designers for the realization of varactor tuning elements in silicon CMOS technology. First, there are standard pn-junction varactors; in an n-well CMOS process the p /n-well junction is the most suitable for varactor implementation. A number of recent monolithic CMOS LC oscillators designs have used such diodes as tank circuit tuning elements [4], [5], [8], [13]. A p /n-well structure can typically have a quality factor of 20 or better. One disadvantage of junction varactors is that they can become forward biased by large-amplitude voltage swings. Alternatively, MOS gate capacitors can be used to implement varactors. The capacitance of a MOS device varies nonlinearly as the dc gate bias of the MOSFET is varied through accumulation, depletion, and inversion. By making appropriate connec /03$ IEEE

2 1326 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 tions with the terminals of the MOSFET, the tuning characteristics of its capacitance can be changed. The specific MOS varactor topologies resulting from these connections and their corresponding characteristics are detailed in Section II. In either case, when varactors are incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the curve of the particular varactor device structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary LC VCO employing MOS varactors implemented in m CMOS technology. II. MOS VARACTORS Different variations on the basic MOS structure have been explored in order to realize varactors with the highest possible quality factor. Andreani and Mattisson presented a thorough discussion of these different MOS varactors for RF VCOs in [14]. Fig. 2 shows the cross sections and corresponding characteristic for each of these structures. The characteristics are normalized to the same maximum capacitance. Each structure shown is similar to a pmos transistor situated in an n-well; pmos is preferred (in an n-well process) because the bulk terminal of an n-well can be biased at a variable voltage. The first structure [Fig. 2(a)] consists of a pmos transistor with the drain, source, and bulk connected together (denoted ) to form one node of the capacitor, and with the polysilicon gate as the other node. This structure has a capacitance that varies nonmonotonically, because the device can operate in inversion, depletion, and accumulation [14], [15]. Fig. 2(b) shows the dc tuning curve of this structure. The maximum capacitance in both inversion and accumulation is approximated by, which can be calculated from the device dimensions assuming a simple parallel plate capacitor (i.e. neglecting fringing effects). This curve also represents the capacitance versus voltage if a very small signal,, is superimposed onto the dc bias voltage. Another option is the inversion-mode MOS (I-MOS) capacitor [Fig. 2(c)]. Like the capacitor, the basic structure is identical to a pmos transistor. The drain and source are shorted together to form one capacitor terminal while the polysilicon gate forms the other. However, the bulk (n-well) of this structure is connected to the highest voltage available in the circuit,. Because the n-well connection of the device is always at a higher or equal potential with respect to the gate, the device can only operate in inversion. This yields the dc/small-signal characteristic shown in Fig. 2(d). This characteristic is nonlinear and near-monotonic, but the transition from to is very sharp. Although the dc characteristic of the I-MOS device suggests an extremely large (and effectively useless) tuning gain, as will be discussed below, the large-signal swing of a VCO output will result in an actual tuning curve that deviates significantly from this dc/small-signal characteristic. Finally, MOS capacitors may also be designed to operate in accumulation mode. Fig. 2(e) shows the structure of an accumulation-mode (A-MOS) capacitor. This structure departs somewhat from the standard pmos transistor, because it replaces the p diffusions of the drain and source with n regions. This suppresses the injection of minority carriers (holes) into the channel and prevents inversion. The use of n regions also obviates the need for n ohmic contacts to bias the n-well, so this structure can be smaller than the other MOS capacitors. Because this device works in accumulation and depletion only, the dc/small-signal capacitance characteristic shown in Fig. 2(f) results. The curve is still nonlinear, and also monotonic. A-MOS varactors have been shown to have very large to ratios compared to other structures [16]. III. LARGE-SIGNAL ANALYSIS OF MOS VARACTORS IN LC VCOs Now, if the signal voltage swing across these devices is large (as would be the case in a VCO tank circuit), then the instantaneous value of the capacitance changes throughout the signal period. The effective capacitance seen by the large signal will be a weighted average of the small-signal capacitance over a single period. Because of this averaging effect, the oscillator RF output frequency versus tuning voltage curve and the dc/smallsignal curve will not be equivalent. A similar qualitative discussion was recently presented in [11] for standard nmos and pmos gate varactor structures. An analysis of this largesignal averaging effect will now be presented. The meaning of large-signal average capacitance must first be defined. From nonlinear network theory, the current into a time-invariant voltage-controlled capacitance (i.e., the characteristic does not vary with time) is defined as [17] where is the dc curve as shown in Fig. 2. If it is assumed that the oscillator output voltage (which drops across the varactor) is nearly sinusoidal (a reasonable assumption for the complementary design [9]) at frequency, then the average capacitance can be expressed as where is the root mean square of the periodic signal with period. In this derivation, the current components at harmonics of are neglected; in reality, these higher harmonic currents will be present in the varactor, but ultimately only play a small role in determining the frequency of oscillation of the circuit. If a signal where represents the dc tuning voltage applied to the varactor and represents the sinusoidal voltage amplitude, is applied to the circuit, the current can be calculated using (1). The fundamental frequency rms current can be calculated by determining the Fourier series coefficient using (1) (2) (3) (4)

3 BUNCH AND RAMAN: LARGE-SIGNAL ANALYSIS OF MOS VARACTORS IN CMOS LC VCOs 1327 (a) (b) (c) (d) (e) (f) Fig. 2. MOS capacitor structures and C V curves. (a) D=S=B structure. (b) D=S=B C V curve. (c) Inversion-mode structure. (d) Inversion-mode C V curve. (e) Accumulation-mode structure. (f) Accumulation-mode C V curve. This equation is a mathematical way of discarding the higher order harmonics, yielding the fundamental rms current. Combining (1), (2), and (3) yields (5) where may be an expression fitted to the dc/smallsignal characteristic. Equation (5) can be integrated numerically. For the three MOS varactor types, the resulting versus tuning bias ( ) curves for voltage amplitudes ( ) of 0.1, 0.5, and 1.0 V are superimposed on the corresponding dc/smallsignal curves in Fig. 3. As can be seen, for the device

4 1328 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 (a) which is advantageous for phase-locked loop (PLL) applications (linear tuning gain). A similar analysis of accumulation-mode pmos devices was also presented recently in [18]. Finally, for the I-MOS device, the tuning curve [Fig. 3(c)] is also highly linear, and the linear region of the characteristic becomes wider as the amplitude becomes larger. The and I-MOS structures can both be modeled in a straightforward manner using existing BSIM3v3 models. On the other hand, A-MOS devices have historically not had model support. However, this is no longer the case for many advanced CMOS processes augmented for RF/mixed-mode applications. A further benefit of the inversion-mode structure is that its n-well connection is tied to rather than a tuning voltage, and therefore the device is less vulnerable to latch-up. On the other hand, A-MOS varactors can have larger tuning ranges if voltages larger than the standard supply are available to tune the varactors, have a more compact geometry (as mentioned above), and have been shown to possess somewhat higher values [14]. For the example design presented in the following section, I-MOS varactors were chosen due to the lack of A-MOS varactor models in the technology used at the time this project was undertaken. (b) (c) Fig. 3. MOS capacitor C V curves showing large-signal effects. (a) D=S= B. (b) A-MOS. (c) I-MOS. In each case, the heavy curve is the dc/small-signal curve, and the lighter curves are for voltage amplitudes A of 0.1, 0.5, and 1.0 V, respectively. [Fig. 3(a)], the effect of increasing the large-signal amplitude is to fill in the local minimum of Fig. 2(b), thereby significantly reducing the effective tuning range of an oscillator using this device in its tank circuit. For the A-MOS varactor, the tuning curve [Fig. 3(b)] does not suffer from the tuning range degradation seen in the varactor case due to the monoticity of the dc/small-signal curve. The tuning curve also becomes fairly linear over a large portion of the dc bias range, IV. EXAMPLE: I-MOS VARACTOR-TUNED m CMOS VCO IMPLEMENTATION A 2.5-GHz complementary LC VCO employing I-MOS varactors was implemented in TSMC m single-poly four-metal 3.3-V CMOS technology [12]. Active buffer circuits (basically a pair of CMOS inverters) are used to present a high impedance to the oscillator output. The capacitance of the inverters must be accounted for in the design of the tank circuit. The complete buffered VCO design is shown in Fig. 4. The transconductances of the devices, and, were chosen to be equal so that the dc voltage at each side of the tank is maintained at approximately. Biasing this node at allows the oscillator waveform to be very symmetric because the positive and negative halves of the waveform will have the same amount of headroom. The symmetry of this circuit topology has also been reported to result in a lower noise corner frequency, which is important for low close-in phase noise performance [9]. The MOS devices were implemented using the minimum gate length allowed in this process (0.35 m). In order to realize ms, m, and m were chosen for the pmos and nmos devices, respectively. The tuning capacitance for the complementary VCO design is implemented in a differential fashion by connecting two identical (single-ended) I-MOS varactors such that their source and drain nodes are tied together and to the tuning control voltage, and their body nodes are tied together and to, as shown in Fig. 4. The gate nodes of the two I-MOS devices connect in parallel with a differential inductor structure to form the overall tank circuit structure. Therefore, the total tank varactor capacitance is half the value of the individual varactors. If the circuit is properly balanced, connecting the tuning capacitors in series creates a virtual ground at the common node.

5 BUNCH AND RAMAN: LARGE-SIGNAL ANALYSIS OF MOS VARACTORS IN CMOS LC VCOs 1329 Fig. 5. Varactor C V test circuit. V is the dc varactor tuning voltage. The 1.65-V voltage at the gate represents the dc operating point of that node in the complementary 0G oscillator circuit (i.e., V =2). Fig. 4. Complete buffered VCO design schematic. When the additional parasitics of the oscillator circuit (tank circuit and actives) were considered, it was decided to design each varactor for a maximum capacitance of approximately 1 pf yielding a maximum total differential capacitance of 0.5 pf. The parasitics of the remainder of the circuit provide the other half of the tank capacitance. To a large extent, the layout geometry of a MOS capacitor determines its. The series resistance of an inversion-mode pmos varactor will include the combination of the gate resistance, the contacts to polysilicon and diffusion, and the resistance of the inverted channel. An expression for the series resistance of an accumulation-mode varactor is developed in [19]. Here this expression was modified slightly (, the n-well sheet resistivity, was replaced by, the inversionlayer sheet resistivity) to reflect its use in an inversion-mode device: where is set equal to the sheet resistance of the channel in the triode region and is the number of gate fingers. can be estimated from a dc sweep of the MOSFET in simulation. Equation (6) was used as a guideline to ensure that the design led to a reasonable. Because, (6) indicates that should be minimized to reduce the series resistance. For this reason, the process minimum channel length was utilized (0.35 m). The width of each channel was chosen to be 3.3 m, which represents a compromise between quality factor, varactor size, and parasitics. Each of the two single-ended varactors consists of four parallel devices with 40 gate fingers each (contacted on both ends of the channel). The entire structure is placed in a common n-well, and n ohmic bulk contacts connect the n-well to between each 40-finger section of the varactor. Using (6) for each varactor, was calculated to be Considering the total tank varactor, the total series resistance would be The total varactor capacitance varies from to pf. Assuming the tuning range extends from 2.3 to 2.8 GHz (as predicted by simulations), the of the varactor will vary from 19.5 to In this technology, the of the (6) tank circuit will be dominated by the of the integrated spiral inductors. The characteristic for one side of the tank circuit varactor was simulated using the test circuit shown in Fig. 5. The amplitude of the ac source represents the voltage swing across the tank circuit. The 1.65-V voltage at the gate represents the dc operating point of that node in the complementary oscillator circuit (i.e. ). The resulting dc/small-signal curve is shown in Fig. 6(a). Note the similarity to the heavy curve in Fig. 3(c). [Note that the latter plot does not account for the 1.65-V dc offset due to the dc operating point of the gate node in the complementary oscillator circuit (i.e., ).] This characteristic was then swept with the large-signal voltage waveform shown in Fig. 6(b), which is represented mathematically by (3) where V and V, resulting in the time-varying capacitance shown in Fig. 6(c). This shows that the nonlinear capacitance establishes the oscillator as a linear time-variant system, although the fundamental characteristic of the varactor is time invariant. Another way of thinking about this is that the I-MOS tank capacitance is pulsewidth modulated by the large signal swing across the dc characteristic; the width of the capacitance pulses will become wider (narrower) as the tuning voltage increases (decreases). Fig. 6(d) shows how the nonlinear capacitance results in a distorted current waveform. In this development, the choice of time scales does not impact the results; is ultimately determined by the amplitude of the large-signal voltage swing, and is effectively independent of the frequency of this waveform. Of course, in an oscillator circuit, the voltage waveform will tune to the frequency determined by the tank circuit and.as discussed above, Fig. 3(c) shows versus tuning voltage for various tank voltage amplitudes. The linearizing effect of the large-signal amplitude on the tuning curve is one reason why the varactor is a poor choice for a tuning element. Although the ratios of the and I-MOS varactors are similar, the nonmonotonicity of the device hampers its tuning range because its large-signal average capacitance never gets as low as. Fig. 7 shows the simulated tuning curves of two simple VCOs (e.g., Fig. 1) that have the same varactor dimensions, but with one implemented using and the other using I-MOS. The tuning curves are calculated from the tank circuit and. The simulated tuning range is shifted up from that of the design in Fig. 4 as this simulation does not fully

6 1330 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 (a) (b) Fig. 6. (c) (d) Time domain effect of nonlinear capacitance for one side of the implemented tank circuit varactor. (a) C(v). (b) v(t). (c) C(v(t)). (d) i(t) = C(v(t))((@v(t))=(@t)). account for circuit parasitics. In each case, the of the tank circuit is assumed to be high and the voltage amplitude at the varactor gate terminals is. Notice that the tuning range of the is only 0.14 GHz (5.3%) whereas the I-MOS has a tuning range of 0.6 GHz (20.7%). Furthermore, the maximum operating frequency of the oscillator is lower than the I-MOS oscillator. The simulated tuning curves display the same characteristics as those predicted by the large-signal modeling in Section III. V. MEASURED RESULTS The VCOs and associated test circuits were laid out on a single CMOS test chip m m fabricated in the TSMC m CMOS process. Fig. 8 shows a micrograph of a fabricated CMOS VCO with RF (GSSG) and dc probes in contact. The die area of the VCO circuit is m m, excluding the pads. For the measurements presented in this paper, the VCO chip was mounted and wirebonded into an Amkor 32-pin 4 mm 4 mm MLF2 package. The package was then mounted on a printed circuit test board to facilitate testing. The peak measured output power of the buffered oscillator is 2 3 dbm into a 50- load. The tuning curve of the VCO was measured by stepping the tuning voltage and measuring the resultant output frequency with the spectrum analyzer. These tuning curves were measured at the maximum tail bias current of 9 ma. Fig. 9 shows the tuning curve of the buffered VCO design. Note the close agreement with the shape of the tuning curve predicted by the large-signal modeling of the circuit in Section IV. The VCO demonstrates a linear tuning characteristic centered at approximately 2.45 GHz, and a tuning sensitivity of 207 MHz/V. The overall measured tuning range is 425 MHz (17%), although there appears to be additional tuning room above V. This compares favorably with the simulated tuning range of 21%. The deviation is due to higher than anticipated tank parasitic capacitance, largely contributed by the integrated inductor. This is supported by measurements of a standalone inductor test structure [20], which show a total differential inductance of nh at 2.5 GHz, but a self-resonant frequency of GHz versus over 10 GHz as predicted by full-wave EM simulations.

7 BUNCH AND RAMAN: LARGE-SIGNAL ANALYSIS OF MOS VARACTORS IN CMOS LC VCOs 1331 (a) Fig. 8. Micrograph of a fabricated CMOS VCO with probes in contact. The die area of the VCO circuit is 550 m m, excluding the pads. An RF GSSG probe is at the right and the dc probe is at the left. (b) Fig. 9. Measured buffered VCO tuning curve. Fig. 7. Simulated MOS capacitor VCO tuning curves. (a) D=S=BVCO tuning curve. (b) I-MOS VCO tuning curve. The VCO phase noise was measured with an Agilent E5500 phase noise measurement system, which is based on the frequency discriminator delay-line method. Phase noise was measured over the V range of. The best case phase noise was measured at V (2.67 GHz), yielding a value of dbc Hz at a 100/600-kHz offset. The oscillator core draws 9 ma; the buffer circuits draw an additional 7 ma. VI. CONCLUSION The effect of large-signal voltage swings across MOS varactor-tuned tank circuits in LC VCOs has been analyzed quantitatively. The large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates significantly from the dc/smallsignal tuning curve of the particular varactor structure. For the varactor, the effect of increasing the large-signal amplitude is to fill in the local minimum of characteristic, thereby significantly reducing the effective tuning range of an oscillator using this device in its tank circuit. For the A-MOS and I-MOS structures, the large-signal tuning curve does not suffer from the tuning range degradation seen in the varactor case due to the monoticity of the dc/small-signal curve, and becomes fairly linear over a large portion of the dc bias range, which is advantageous for PLL applications (linear tuning gain). Simulated results are compared to measurements for an example 2.5-GHz complementary LC VCO using I-MOS varactors implemented in m CMOS technology. The measured tuning characteristic agrees well with the tuning curves predicted by the large-signal analysis. ACKNOWLEDGMENT The authors would like to thank G. Studtman of M/A-COM, Roanoke, VA, for assistance with mounting the test chip die for on-wafer testing. They would also like to thank RF Microdevices, Greensboro, NC, for wirebonding, packaging, and providing the test boards for the packaged VCO measurements, and for providing access to state-of-the-art phase noise measurement equipment. REFERENCES [1] T. H. Lee, CMOS RF: No longer an oxymoron, in IEEE GaAs Integrated Circuit Symp. Dig., 1997, pp [2] T. Manku, Microwave CMOS: Device physics and design, IEEE J. Solid State Circuits, vol. 34, pp , Mar [3] A. Matsuzawa, RF-SoC: Expectations and required conditions, IEEE Trans. Microwave Theory Tech., vol. 50, pp , Jan

8 1332 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 [4] J. Craninckx and M. S. J. Steyaert, A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors, IEEE J. Solid-State Circuits, vol. 32, pp , May [5] B. Razavi, A 1.8-GHz CMOS voltage-controlled oscillator, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1997, pp [6] B.-H. Park and P. E. Allen, Low-power, low-phase-noise CMOS voltage-controlled-oscillator with integrated LC resonator, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 1998, pp [7] F. Svelto, S. Deantoni, and R. Castello, A 1.3-GHz low-phase noise fully tunable CMOS LC VCO, IEEE J. Solid-State Circuits, vol. 35, pp , Mar [8] B. De Muer, M. Borremans, M. Steyaert, and G. Li Puma, A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization, IEEE J. Solid-State Circuits, vol. 35, pp , July [9] A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE J. 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Wong, Analysis and optimization of accumulation-mode varactor for RF ICs, in Symp. VLSI Circuits Dig. Technical Papers, June 1998, pp [17] L. O. Chua, Introduction to Nonlinear Network Theory. New York: McGraw-Hill, [18] S. Levantino, C. Samori, A. Bonifanti, S. L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion, IEEE J. Solid-State Circuits, vol. 37, pp , Aug [19] C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. O, High-Q capacitors implemented in a CMOS process for low-power wireless applications, IEEE Trans. Microwave Theory Tech., vol. 46, pp , May [20] R. L. Bunch, D. I. Sanderson, and S. Raman, Quality factor and inductance in differential IC implementations, IEEE Microwave Mag., vol. 3, pp , June Ryan Lee Bunch (S 98 M 01) was born on May 25, 1977 in Suffolk, VA. He received the B.S. and M.S. degrees from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 1999 and 2001, respectively. During the summers of 1998 and 1999, he interned as an Analog Circuit Designer with IBM, Raleigh, NC. In August 1999, he returned to Virginia Tech to pursue graduate studies in electrical engineering. His research there focused on CMOS radio-frequency circuits. He is currently a Design Engineer with the Digital Cellular Products Line of RF Micro Devices, Greensboro, NC, where he specializes in CMOS analog/rf design for GSM/PCS applications. Sanjay Raman (S 84 M 98) was born on April 25, 1966 in Nottingham, U.K. He received the B.S.E.E. degree from the Georgia Institute of Technology, Atlanta, in 1987 and the M.S.E.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1993 and 1997, respectively. His Ph.D. work involved novel millimeter-wave integrated antennas and electronics. From 1987 to 1992, he served as a nuclear-trained Submarine Officer with the U.S. Navy. He joined the faculty of the Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, in January 1998 as an Assistant Professor. He established the Wireless Microsystems Laboratory to explore enabling ideas and technologies for integrated microsystems, in particular microsystems that are connected to the information infrastructure via wireless communications links. His research interests include RF/microwave/millimeter-wave integrated circuits and antennas, integrated wireless communications and sensor microsystems, high-speed/mixed-signal ICs, interconnects, and packaging, RF MEMS and MEMS sensors, micromachining, and solid-state technology. Dr. Raman s academic honors include the Presidential Early Career Award for Scientists and Engineers (PECASE) for , the 2000 Virginia Tech College of Engineering Outstanding New Assistant Professor Award, First Place in the Student Paper Competition of the 1996 IEEE MTT-S International Microwave Symposium, the Armed Forces Communications and Electronics Association (AFCEA) Postgraduate Fellowship, and First Place in the Student Paper Competition of the 1995 IEEE Antennas and Propagation International Symposium.