Passive Device Characterization for 60-GHz CMOS Power Amplifiers

Transcription

1 Passive Device Characterization for 60-GHz CMOS Power Amplifiers Kenichi Okada, Kota Matsushita, Naoki Takayama, Shogo Ito, Ning Li, and Akira Tokyo Institute of Technology, Japan 2009/4/20

2 Motivation 1 60GHz unlicensed band Australia America, Canada Europe Australia America, Canada Japan Europe Japan Frequency [GHz] Frequency [GHz] [1] 9GHz-BW around 60GHz Several-Gbps wireless communication Use of CMOS process Fab. cost is very important to generalize it. RF&BB mixed chip can be realized.

3 Our target 2 8b DAC 8b DAC DAC LNA LPF LPF Buff Buff VGA VGA ADC ADC DAC 60GHz Tripler with I/Q ch 20GHz PLL PLL 36MHz TCXO ch 3456MHz PLL PLL DAC Digital Base Band PA DAC 8b+6b DAC 8b+3b LPF LPF DAC DAC DAC 8b DAC 8b Reg. bank addr/data 60GHz 2.16GHz-full 4ch direct-conversion by CMOS Tr QPSK 3Gbps & 16QAM 6Gbps & 64QAM 9Gbps IEEE c conformance Dynamic power management: <300mW for RF front-end

4 Circuit blocks of 60GHz transceiver 3 60GHz LNA Down-Mixer 20GHz PLL 60GHz PA Up-Mixer 60GHz Tripler with quadrature output

5 mmw CMOS circuit design 4 Matching is very important for mmw circuit design, because (1) The wave length is very short, (2) Tr s gain is very small, and (3) Loss of TL is very large. Matching blocks Inductor@ Transmission line@60 At 60GHz, every interconnects should be dealt with as a distributed component. The accurate characterization is required.

6 Overview of device characterization 5 Initial T.O. Second T.O. Initial T.O. for Modeling Transistors (CS, CG with various layouts) Transmission line (various length & Z0) Branch & bend line Spiral inductor Balun Series capacitor Decoupling capacitor De-embedding patterns 1-stage amplifier for the model evaluation DC probe Second T.O. Circuit building blocks Whole system

7 Overview of characterization 6 Transmission line Branch & bend line Decoupling capacitor De-embedding patterns 1-stage amplifier DC probe 4-stage power amplifier

8 Dummy metal 7 To avoid random production of dummy metal, it is manually placed to keep good reproducibility. Metal dummy 40um Metal dummy

9 Tile-base layout 8 Each component is previously measured and modeled. The same layout is utilized to maintain modeling accuracy. 5µm pitch T-Junction Tr TL C L-Bend MIM TL RF PAD GND-Tile

10 Transmission line in CMOS chip 9 Guided microstrip line GND Signal GND e γl K S11 + S 21 = ± K 2S21 ( S = S ) (2S ) (2S 11 ) Z 2 = Z 2 0 (1 + S (1 S γ = α + j β Slow-wave coplanar-waveguide is also utilized depending on a required characteristic impedance. ) ) 2 2 S S

11 Cross-sectional structure Ω/mm G S G Top metal 1.2um 8.0um 15um 10um 15um 40um Metal 1(shield/slit) Substrate 320um 0.2um 0.3um

12 Modeling of transmission line 11 ADS s CPW model To meet measured α, β, Q and Z 0, substrate model is individually extracted for each structure.

13 Transmission line (200µm) Measurement Model Measurement Model Q 20 Z 0 [Ω] Frequency [GHz] Frequency [GHz] Improved Mangan s method is utilized with 200µm and 400µm transmission lines. [2] A.M. Mangan, et al., IEEE Trans. on Electron Devices, vol. 53, no. 2, pp , Feb. 2006

14 Transmission line (400µm) Measurement Model Measurement Model Q 20 Z 0 [Ω] Frequency [GHz] Frequency [GHz] 400µm of transmission line has almost the same characteristics with that of 200µm, which is a good proof of accurate modeling.

15 Overview of characterization 14 Transmission line Branch & bend line Decoupling capacitor De-embedding patterns 1-stage amplifier DC probe 4-stage power amplifier

16 Branch & bend modeling 15 with 4 bending parts with 200µm shunt TL with 300µm shunt TL Each red-box part is characterized as a combination of optimized transmission lines.

17 T-junction modeling 16 Straightforward modeling Lower Z0 TLs are utilized, and Z0 is adjusted for the measurement results. Dummy metal causes unexpected response.

18 Experimental results for T-junction 17 0 No model ADS model S(2,1) [db] Our model Measurement Without T model With T model Modeling Frequency [GHz] T-junction with 200µm shunt TL S(2,1) [db] Our model extracted from 200µm TEG Measurement Modeling Frequency [GHz] T-junction with 300µm shunt TL

19 Overview of characterization 18 Transmission line Branch & bend line Decoupling capacitor De-embedding patterns 1-stage amplifier DC probe 4-stage power amplifier

20 MIM capacitor for de-coupling 19 Area efficiency is large, but the self-resonance freq. is low. The regular layout of MIM cap. cannot be used at 60GHz.

21 Interdigital MIM capacitor 20 Interdigital structure with the optimized finger length is utilized. to DC-Pad MIM cap. is modeled as a lowimpedance transmission line. to Matching block

22 Distributed modeling of MIM cap. Modeled as a transmission line 21 reflection 1-67GHz

23 Overview of characterization 22 Transmission line Branch & bend line Decoupling capacitor De-embedding patterns 1-stage amplifier DC probe 4-stage power amplifier

24 An evaluation using a 1-stage amplifier 23 Transmission line De-coupling cap. :CS Transistor (De-embedded S-parameter) Comparison between model and measurement.

25 Model evaluation in input&output reflection 24 S11(gate-side reflection) S22(drain-side reflection) 60GHz Measurement with de-coupling model without de-coupling model De-coupling MIM model is required for reliable design. 90nm CMOS is used.

26 Other modeling issues 25 De-embedding Transistor layout optimization Spiral inductor Balun RF Pad DC probe / bonding wire / bump / filler / PCB

27 In-house PDK 26 PVT C MIM TL TL with L/T NMOS PMOS R RF PAD DC probe Varactor MIM MOS cap Each component is implemented as an in-house PDK for Agilent ADS.

28 Overview of characterization 27 Transmission line Branch & bend line Decoupling capacitor De-embedding patterns 1-stage amplifier DC probe 4-stage power amplifier

29 4-stage class-a Power Amplifier CMOS 65nm process Short stub 28 Vds4 370 m Vds3 5.75pF 290 m Vgs4 5.75pF 310 m 7.25pF 75fF RFout 70 m 140 m 20 m 100fF 50 m W=80 m 150 m W=80 m

30 Chip micrograph 60GHz CMOS PA mm IN OUT surface ground plane 1.5mm CMOS 65nm process

31 Measurement results S21: 16.4dB S11: <-8dB S22: <-10dB

32 Measurement results 31 Power gain: 16.4dB P1dB: 4.6dBm PDC: 122mW

33 Measurement summary 32 Reference Technology Freq. [GHz] Gain [db] P1dB [dbm] 1dB [%] PDC [mw] VDD [V] [4] JSSCC nm CMOS [5] RFIC nm CMOS [6] ISSCC nm CMOS [7] ISSCC nm CMOS [8] ISSCC nm CMOS [9] ISSCC nm CMOS [10] ISSCC nm CMOS [11] MWCL nm CMOS This work 65nm CMOS [4] T.Yao, et al., JSSC 2007(Tronto Univ.) [5] T.L.Rocca, et al., RFIC 2008 (UCLA) [6] T.Suzuki, et al., ISSCC 2008 (Fujitsu) [7] D. Chowdhury, et al., ISSCC 2008 (UCB) [8] M. Tanomura, et al., ISSCC 2008 (NEC) [9] W.L. Chan, et al., ISSCC 2009 (Delft Univ.) [10] K. Raczkowski, et al., ISSCC 2009 (KU Leuven&IMEC) [11] J.-L.Kuo, et al., MWCL 2009 (NTU)

34 Summary & Conclusion 33 In this presentation, I presented a modeling approach to design a 60GHz CMOS amplifiers. 1. Design issue of TL on CMOS chips is different from that of compound semiconductors. e.g., dummy metal, lossy substrate, large conductive loss, etc 2. Branch modeling 3. Distributed modeling of de-couple MIM cap. 4. Evaluation using a 1-stage amplifier By the proposed modeling method, 60GHz power amplifier can be successfully realized.

35 Acknowledgement 34 This work is partially supported by MIC, STARC, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd. Special thanks to Dr. Joshin, Dr. Hirose, Dr. Suzuki, Dr. Sato, and Dr. Kawano of FUJITSU Lab., Ltd. for their fruitful discussion.