A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS Using Dummy-Prefilled Microstrip Lines

Transcription

1 A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS Using Dummy-Prefilled Microstrip Lines M. Seo 1, B. Jagannathan 2, C. Carta 1, J. Pekarik 3, L. Chen 1, C. P. Yue 1 and M. Rodwell 1 1 Dept. of Electrical and Computer Engineering g University of California, Santa Barbara 2 IBM, Burlington, VT 3 IBM, Crolles, France 1

2 Outline Introduction Dummy-Prefilled Microstrip Line Structure and Modeling Design and Simulation Measurement Results 2

3 Beyond 100GHz: What Applications? Attenua ation (db/km m) O 2 94GHz 140GHz 220GHz O 2 H 2 O H 2 O Frequency (GHz) Communication Outdoor, indoor Imaging (Passive, active) Security All-weather radar Medical 3

4 Beyond 100GHz: Why CMOS? Low-cost Low-power Large-scale Integration Parallelism Large monolithic phased array, imager. RF/mm-wave, IF/analog, DSP on a same die. System-on-chip Digital calibration of RF/analog circuit imperfections, process variations. Reconfigurability and adaptability 4

5 What Challenges in 150GHz CMOS Amp? Low available FET gain, Low Supply Voltage Careful FET layout & sizing Multi-stage Common-Source Modeling uncertainties Simple matching topology with microstrip (MS) lines Automatic dummies alter MS-line characteristics Propose Dummy-prefilled MS-line Characterization Full 2-port on-wafer TRL calibration 5

6 FET Layout Maximum m Stable Gain (db) x1um/65n Parallel gate feed (PGF) Series gate feed (SGF) Frequency (GHz) Finger design: Reduce R g,ext and C gd (W F =1um) Wiring multiple fingers: Parallel versus Series G S S G G D D 6

7 Microstrip Line in Nanoscale CMOS Ground plane Automatic dummies/holes to meet metal density rules. Line capacitance increases ΔC depends on E-field orientation Anisotropic Direct E/M simulation nearly impossible 7

8 Possible Shapes of Dummy Pre-fillers LINE dummies Parallel to current flow dummies LINE dummies Perpendicular to current flow SQUARE dummies No preferred direction of current flow 8

9 Reducing Complexity in E/M Sim Dummy Pre-fillers W S E/M simulation feasible by significantly reducing # of dummies Signal Signal E-field lines Dummy-free uniform dielectric i with adjusted diel. constant ε ε Successive dummy-layer substitution by parallel-plate capacitor simulation 9

10 Line Inductance/Capacitance vs Fill Ratio % chang ge L per unit length (317nH/m w/o fillers) 25% Fill W:S = 1: % ch hange % +32% C per unit length (103pF/m w/o fillers) 56% Fill W:S = 3: Fill Ratio (%) 10

11 Ground Plane Construction Solid GND plane not allowed + Put holes, and strap M1 & M2 M1 M2 via Where current flow is uniform (e.g. under MS-line) Where current flow is not uniform (e.g. under bends, T-junction, radial stubs) 11

12 THRU-REFL-LINE (TRL) Calibration (1) THRU Half THRU (2) REFL (3) LINE 450um ΔL Reference plane (Open, short, etc) (ΔL= 90 freq) Amplifier Test REFL & LINE need not be accurately known Measurements normalized to the line impedance 12

13 3-Stage 150GHz Amplifier: Schematic Radial stub V2 V3 TL1 TL2 TL3 TL4 All TL s: Z 0 = 51.2 W=10u (25% fill) V1 M1 M2 M3 V4 Half THRU 30u/65n 30u/65n 30u/65n Amplifier Half THRU No DC block: Forces V GS =V DS for M1 & M2, but eliminates loss and modeling uncertainties associated with DC-block cap FET size is chosen for low matching loss 13 Radial stub for lower loss than quarter-wave TL

14 FET Sizing constant-g circle (20mS) S22* (g22 g11) Z 0 Large FET S11 Small FET constant-q circle Conjugate input/output/inter-stage t t/i t t match with shunt tuning stubs only. 14

15 Simulated 150-GHz Amplifier Gain 7 S21 (db B) AC short ¼λ P DC = 25mW Radial stub (45deg opening) 0.65V 1.1V Open-stub Z0=34, W=20u 2 1 ¼λ Open-stub Z0=51, W=10u Frequency (GHz) 15

16 Die Photograph 640μm Dummy-prefilled radial stub Area = 0.4mm 2 (w pads) = 0.16mm 2 (w/o pads) Stack: 9 Cu + 1 Al Dummy-prefilled MS-lines Automatic dummies Reference planes 640μm 16

17 S-parameter Measurement Setup GGB Probes OML Inc. Agilent Probe W/G GHz Coax 8510C Station WR05 mm-wave heads IF/LO VNA 17

18 Can we trust the calibration? S11 THRU < -40dB S21 (db) S21 THRU < 0.1dB S11 OPEN < 0.2dB Frequency (GHz) S11 LINE < -35dB Probe coupling < -40dB Repeatability issues Probe placement Probe contact resistance 18

19 S S21 (db/ /mm) S21 Pha ase (deg g) Prefilled MS-Line: Measurement mm-long Line E/M Sim LINE standard 60 E/M Sim (8% error) Frequency (GHz) 19

20 Measured Amp. S-Parameters r (db) Peak S21 = 8.2dB S21 3dB BW= 27GHz Meas Sim P DC = 25.5mW 0.65V 1.1V S-pa aramete S11 meas S22-20 S11 sim Frequency (GHz) 20

21 S21 versus Current Density 8 60 S2 21 (db) ~0.9V V Drain Current Density (ua/um) DC Po ower (m mw) 21

22 Drain Bias (M3) S21 (db B) V1=V2=V3<V4 1.1V 0.5~0.9V V V V DC power (mw) 22

23 Amplifier Stability Factor 5 Sta ability Fa actors K > 1 B1 > Frequency (GHz) Unconditionally stable over GHz. 23

24 Large-Signal Setup 20 GHz Signal Source x12 Freq. Multiplier Virginia Diode Inc. WR05 Variable Attenuator WR05 GGB probes On-wafer DUT 0.2dB loss WR05- WR10 P IN = -20dBm ~ +15dBm Freq= 153GHz ~175GHz Power Meter Erikson Instruments. Power correction: Insertion calibration using W/G THRU & On-wafer THRU 24

25 Large-Signal Characteristics Pow wer Adde ed Effici iency (% %) P sat =+63dBm +6.3dBm 20 5 op 1dB =+1.5dBm Peak PAE= 8.4% P in (dbm) n (db) P out (db Bm), Gai freq= 153GHz P DC = 25.5mW 0.65V 1.1V 25

26 Comparison of Measured S21 S21 (db) S21 from VNA Meas. S21 from Power Meas Frequency (GHz) VNA Measurement: Full 2-port TRL calibration Power Measurement: Insertion calibration 26

27 Performance Summary Technology 65nm digital CMOS Topology Center freq 3dB BW Peak Gain 3-stage Common-source 150GHz 27GHz 8.2dB Input RL -7.4dB 74dB Output RL -13.6dB DC Power 25.5mW5 P 1dB P sat +1.5dBm +6.3dBm 27

28 Conclusion Minimalistic Circuit Design Strategy Design-rule Compliant Transmission Line Structure and Modeling Linear/Power measurement up to 200GHz Highest frequency CMOS amplifier reported to date 28

29 Acknowledgement IBM for chip fabrication and support OML Inc. This work was supported by the NSF under grants CNS and ECS