Thales UK Designs GaN MMIC/Packaging for EU MAGNUS Program Using NI AWR Software

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1 Success Story Thales UK Designs GaN MMIC/Packaging for EU MAGNUS Program Using NI AWR Software Company Profile Thales UK is a world-leading innovator across the aerospace, defense, ground transportation, security, and space industries. The company provides world-leading technology for both the civil and defense markets and its products impact the lives of people every day. Thales UK s work is at the forefront of safeguarding people and organizations in the UK and across the globe. Wherever safety and security are critical, Thales delivers. Together, Thales UK innovates with its customers to build smarter solutions, everywhere. The Design Challenge Thales UK is one of six companies from five European countries involved in designing products for the MAGNUS program, a European Defense Agency project aimed at developing European sourced application technologies for gallium nitride (GaN) on silicon (SiC). The technologies are used in advanced radar, communications, and electronic warfare systems covering the electromagnetic (EM) spectrum from 2-18 GHz. Thales UK was responsible for the design of 10 W GaN monolithic microwave integrated circuit (MMIC) power amplifiers based on the United Monolithic Semiconductors (UMS) 0.25 µm foundry process. In parallel with this activity, package design and thermal analysis tasks were also performed. Once the MMICs had been realized and packaged, they were used to design a demonstrator unit, which Thales UK then leveraged to design a 30 W microwave power module (MPM). Two foundry runs were permitted. Table 1 shows the MMIC specifications. Application: MMIC Software: NI AWR Design Environment Microwave Office AXIEM Analyst Our design and simulation efforts showed that the UMS PDK as well as the Microwave Office and Analyst models were very accurate, which led to the success of this project. Parameter Requirements Comments Frequency 8-18 GHz Aim: 6-18 GHz Gain > 10 db Output power > 10 W Input return loss > 7 db Aim: > 10 db Duty cycle 20% PAE > 20% Drain bias V Chip size 5x4 mm 2 Rashid Fazaldin Microwave Design Engineer Thales UK thalesgroup.com Table 1: MMIC design specifications. The goals for this design were a frequency range of 6-18 GHz, 10 db gain, and 10 W output power. It was decided to use a non-uniform distributed amplifier topology, which is ideally suited for broadband operation because it is inherently stable. The goal was to design two distributed amplifiers on a chip between a pair of splitter/combiner networks. For the first foundry run the amplifiers were combined off chip and for the second run the combining was done on chip. ni.com/awr

2 The Solution The MMIC designs were carried out using NI AWR Design Environment, specifically Microwave Office circuit design software, the passive structures were simulated in AXIEM 3D planar EM simulator, and the package was analyzed in Analyst 3D finite-element method EM simulator. The layout of the MMIC for the first foundry run, which was done with the amplifiers combined off chip, is shown in Figure 1. The drain line and gate line can be seen, with the capacitors in series with each field-effect transistor (FET). There is also a shunt resistor, which supplies bias to each FET. Most of this was taken from the FETs and the inductor was taken from the design. But the team had to design its own high-power inductor, which was achieved using NI AWR Design Environment. Figure 2 shows the passive structures (high current choke, drain structure, and Lange coupler) simulated in AXIEM. Figure 3 shows the small-signal on-wafer results achieved on the first run for S 21 and S 22. Figure 1: Layout of MMIC for first foundry run. Amplifiers were combined off chip. Figure 2: Passive structures simulated in AXIEM. Figure 3: On-wafer results achieved on the first run for S 21 and S 22.

3 The magenta line is the simulated gain, which is slightly greater than 10 db. There was excellent agreement between the simulated and measured results. The output power and power-added efficiency (PAE) also agreed very well with the simulation, as shown in Figure 4. Approximately 5 W was achieved per single engine device with some roll off at the 18 GHz end and greater than 20 percent efficiency across the band. Results are shown for all chips. Figure 4: Simulation results for output power and PAE. The first foundry run yielded the following: Average gain > 10.5dB Flat gain over frequency: ±0.75dB Spread for S21 < 1dB Good input return loss > 12dB Good output return loss > 8.5dB Stable K factor >1 Output power, single ended ~37dBm Flat saturated output power over frequency Spread < 0.5dB PAE ~ 20% Electrical yield 100% Lange coupler - good correlation The second foundry run is shown in Figure 5. The design kit was changed for this run from v2 to v3.1, which resulted in a different geometry of the FET from the first run. Figure 5: Layout of MMIC for second foundry run.

4 Figure 6 shows the simulated results of the Lange coupler, with a length of 2400 µm, 8 µm width, separation of 6 µm, and loss of 0.3 db per coupler. Figure 7 shows the on-wafer results for the second run with, again, excellent agreement with the simulation results in both gain and return loss and Figure 8 shows the first run MMIC package, simulated in Analyst, where a) is the complete package and b) shows detail of the ceramic port and tape transition. The final step of the program was to design a demonstrator where the MMICs performed a function. The design team used Microwave Office to design a 30 W MPM with a low-loss power combiner and biasing/control circuitry. Figure 6: Simulated results for the Lange coupler. Figure 7: On-wafer results for gain and return loss for the second run. Figure 8: First run MMIC package simulated in Analyst, with a) complete package simulated with a microstrip line and b) detail of the ceramic port and tape transition. a) b)

5 Figure 9 shows the four MMICs going into the low-loss combiner. Figure 10 shows the results of the Wilkinson power combiner/dividers designed in NI AWR Design Environment. The input return loss was > 15dB and S 22 less than -20 db, and the isolation was > 17 db. Simulation results obtained include db of gain, 10 db of return loss, and 30 W of power measured between 6-18 GHz, all shown in Figure 11. Figure 9: MPM showing four MMICs going into a low loss combiner. Figure 10: Results of Wilkinson power divider designed in NI AWR Design Environment. Figure 11: Measured power showing 6-18 GHz. Why NI AWR Design Environment The key feature that enabled the success of this project was the extremely accurate models in NI AWR Design Environment. The ability to work seamlessly between Microwave Office circuit design environment, AXIEM EM simulation of the passives, and Analyst EM simulation of the package streamlined the project considerably National Instruments. All rights reserved. AWR, AWR Design Environment, AXIEM, Microwave Office, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. SS-M-THLS