Gallium Nitride MMIC Power Amplifier

Transcription

1 Gallium Nitride MMIC Power Amplifier August 2015 Rev 4 DESCRIPTION AMCOM s is an ultra-broadband GaN MMIC power amplifier. It has 21dB gain, and >41dBm output power over the 0.03 to 6GHz band. This MMIC is matched to 50 Ohms at the input but un-matched at the output above 1GHz. The chip is also available as a drop-in carrier () for attachment to a metal heat sink. FEATURES Ultra wide bandwidth from 30MHz to 6GHz Saturated output pulse power P5dB > 42dBm Small signal gain, 21dB Input matched to 50 Ohms APPLICATIONS Software Radio, ECM Instrumentation Gain block TYPICAL PERFORMANCE * A) Bias Conditions**: V ds1 = +30V, I dq1 = 400mA, V dd2 = +60V, I dq2 = 1000mA (100µs pulse, 10% duty cycle) Parameters Minimum Typical ** Maximum Frequency 0.1 5GHz GHz Small Signal Gain 17dB 21dB 25dB Gain Ripple ± 2dB ± 3.0dB 0.5GHz 41dBm 43dBm 3.0GHz 40dBm 42dBm 6.0GHz 40dBm 0.5GHz 43dBm 45dBm 3.0GHz 42dBm 44dBm 6.0GHz 41dBm P5dB 0.5GHz 47% P5dB 3.0GHz 30% P5dB 6.0GHz 20% Noise Figure IP3 Input Return Loss 15dB 17dB Output Return Loss 5dB Thermal Resistance

2 B) Bias Conditions**: V ds1 = +28V, I dq1 = 400mA, V dd2 = +28V, I dq2 = 1000mA (CW) Parameters Minimum Typical ** Maximum Frequency 0.1 5GHz GHz Small Signal Gain 14dB 18dB 22dB Gain Ripple ± 2dB ± 3.0dB 0.5GHz 37dBm 39dBm 3.0GHz 37dBm 39dBm 6.0GHz 35dBm 0.5GHz 39dBm 41dBm 3.0GHz 39dBm 41dBm 6.0GHz 36dBm P5dB 0.5GHz 40% P5dB 3.0GHz 30% P5dB 6.0GHz 10% Noise Figure IP3 Input Return Loss 15dB 17dB Output Return Loss 5dB Thermal Resistance * Specifications subject to change without notice. ** Data obtained using test fixture shown in this datasheet. Gate biases corresponding to above currents are V gs1 =-3.75V, V gs2 =-3.75V, and may vary from lot to lot. *** Input RF power should not exceed 0.8W (29dBm). ABSOLUTE MAXIMUM RATING (10% Pulse) Parameters Symbol Rating First stage drain voltage V ds1 35V Second stage drain voltage V dd2 70V Gate source voltage V gs1 & V gs2-6v Drain source current I dq1 0.7A Drain source current I dq2 1.75A Continuous dissipation at 25ºC P t 40W Channel temperature T ch 175 C Operating temperature T op -55 C to +85 C Storage temperature T sto -55 C to +135 C Maximum input RF power P in 0.80W

3 Gain & Return Losses (db) AMCOM Communications, Inc. SMALL SIGNAL DATA A) CW S-Parameters (V ds1 = 28V, I dq1 =0.4A, V dd2 =28V, I dq2 =1.0A) Gain Output RL Input RL Frequency (GHz) B) 10% Duty Cycle Pulsed S-Parameters (V ds1 = 30V, I dq1 =0.4A, V dd2 =60V, I dq2 =1.0A) NOISE DATA ()

4 PULSED POWER DATA* * Power measured under pulse conditions using test fixture with matching shown in this datasheet. Pulse is 100µsec with 10% duty cycle. Bias is V ds1 =25V, V dd2 =60V, I dq1 =400mA, I dq2 =1000mA CW POWER DATA** ** Power measured under CW conditions using test fixture with matching shown in this datasheet. Bias is V ds1 =28V, V dd2 =28V, I dq1 =400mA, I dq2 =1000mA

5 CHIP OUTLINE () Pin Layout Pad No. Function Bias 1 RF in 2 Vgs1-3.75V 3 Vds1 +30V 4 Vgs2-3.75V 5 Vgg2 +60V 6 Vdd2 & RF out +60V 7 Vdd2 & RF out +60V 8 Vdd2 & RF out +60V 9 Vdd2 & RF out +60V 10 Vgg2 +60V 11 Vgs2-3.75V 12 Vds1 +30V Gate biases are for reference only and may vary from lot to lot For CW Operation bias for V gg2, V ds1 & V dd2 is +28V 13 Vgs1-3.75V

6 CARRIER OUTLINE () Pin Layout Pin No. Function Bias 1 RF in 2 Vgs1-3.75V 3 Vds1 +30V 4 Vgs2-3.75V 5 Vgg2 +60V 6 Vdd2 & RF out +60V 7 Vgg2 +60V 8 Vgs2-3.75V 9 Vds1 +30V 10 Vgs2-3.75V Gate biases are for reference only and may vary from lot to lot. For CW Operation bias for V gg2, V ds1 & V dd2 is +28V

7 TEST CIRCUIT for GHz Important Notes: 1- The +60V pulsed bias to the output port could be provided via a bias tee or suitable chokes to be soldered on the board. Inductance of choke should be large enough to have high impedance at lowest frequency of operation (300nH is adequate). 2- For CW operation use +28V for V gg2, V ds1 & V dd2. 3- Input RF power should not exceed 0.80W 4- Recommended pulsed current biases are 400mA and 1000mA for the first stage and second stage respectively. Gate biases of -3.75V are for reference only. V gs1 & V gs2 could be adjusted to vary the currents going thru the first stage (V ds1 pin) and the second stage (V dd2 pin) respectively. 5- Do not apply V ds1 & V dd2 without proper negative voltages on V gs1 & V gs2. Otherwise MMIC would fail due to excess heat.