Improved Modeling of Sigma- Delta Modulator Non- Idealities in SIMULINK

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1 A. Fornasari, P. Malcovati, F. Maloberti: "Improved Model of Sima-Delta Modulator Non-Idealities SIMULINK"; Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 005, Kobe, 3-6 May, Vol. 6, pp xx IEEE. Personal use of this material is permitted. However, permission to reprt/republish this material for advertis or promotional purposes or for creat new collective works for resale or redistribution to servers or lists, or to reuse any copyrihted component of this work other works must be obtaed from the IEEE.

2 Improved Model of Sima-Delta Modulator Non-Idealities SIMULINK A. Fornasari, P. Malcovati and F. Maloberti Department of Electrical Eneer, University of Pavia Via Ferrata 1, 7100 Pavia, Italy {andrea.fornasari, piero.malcovati, Abstract The oal of this paper is to present an extension of the behavioral models, implemented the Matlab/Simulk environment, previously presented [1, ] and available [3]. This toolbox allows us to simulate at behavioral level most of the switched-capacitor (SC) sima-delta (!") modulator non-idealities, such as sampl jitter, kt/c noise and operational amplifier limitations (fite bandwidth, fite DC a, slew rate and saturation). Althouh very effective simulat wide-band, medium-resolution!" converters the lack of a model for flicker noise and multi-bit quantizers makes this toolbox less attractive for simulat narrow band hih resolution converters. The proposed extension not only fixes this limitation, but troduces a predictive model of the effect of capacitor mismatch the ternal multi-bit D/A converter. I. INTRODUCTION Due to the herent non-learity of the sima-delta (!") modulator loop, the optimization of the basic build blocks has to be carried out with behavioral time-doma simulations [1]. The Matlab/Simulk toolbox (SD Toolbox) presented [1, ] is a ood trade-off between accuracy and speed of the simulations. In this paper two additional blocks are presented. The first allows us to clude the Matlab environment data about the noise power spectral density (PSD) of the operational amplifiers obtaed by a circuit simulator (e.. Spectre or Eldo), clud flicker noise. The second one allows us to estimate the impact of the mismatches amon capacitors the feedback DAC of a multibit!" modulator on the sinal-to-noise and distortion ratio (SNDR). In order to validate the proposed models, we simulated both at behavioral and transistor level the second-order switched-capacitor (SC)!" modulator architecture shown Fi. 1 [4], which features a 1 levels ternal DAC (11 comparators the ADC). II. NOISE MODEL In the orial toolbox (SD Toolbox) all the possible noise sources (maly the contributions of the operational amplifiers and of the voltae references) were supposed to be white. The parameter V n of the noise model (i.e. the noise rms voltae) had to be evaluated us a transistor-level noise simulation the proper clock phase and clud all the load capacitors. The output referred noise PSD obtaed from the simulation had then to be terated over the whole frequency spectrum, thus obta the total noise power V n. The square root of this value, V n, was fally used the model to scale the output of a Gaussian distributed random sinal. This model allows very fast simulations and can be used without any worry, if one of the two follow considerations is satisfied: the flicker noise (1/f) can be nelected the specific field of application (wide band converters); the noise spectrum is folded, due to sampl operation, a number of time sufficient to be considered white. If these two conditions are not satisfied a more accurate model has to be used. SOURCE 1- Discrete Filter 1- Discrete Filter Fiure 1.!" modulator topoloy porposed [4] and used to test behavioral blocks. III. Ga COLORED NOISE MODEL The noise PSD (expressed V /Hz), provided by most transistor-level simulator, can be considered as the spectrum of the sum of N se-waves with arbitrary phase (Fourier theorem), each hav a power equal to the area of a slide of the PSD as lare as F MAX divided by N (i.e. as lare as a b) A/D D/A N # V Noise = a i s! F MAX N it + " & ) % i(, (1) $ ' i=1 This simple consideration is the basis for the proposed noise model, whose flow chart is shown Fi.. Basically, we pass the Matlab environment a detailed description of the noise PSD, elaborate it (basically fold it around the sampl frequency F s ) and calculate the value of V Noise at the end of each clock period (T s ). The first possibility to pass the PSD the Matlab environment is to sample the waveform (Fi. 3) provided by the transistor-level simulator (e.. us the Ocean commands the Cadence environment) and to reconstruct the function Matlab. A simpler possibility is to D/A /05/$ IEEE. 598

3 take advantae of the knowlede about the shape of the noise PSD. Consider that the noise power is additive, the PSD can be considered as the sum of a term due to flicker noise and one due to thermal noise, low-pass filtered by the circuit transfer function: This can simply be accomplished by connect at the output of the noise model block the proper z-doma transfer function. S k 1 =! c+ " 1 N # f $ % & 1 + f fp. () In this way, by provid the coordates of only two pots, the corner frequency (f C, y C ) and the pole frequency (f P, y P ), it is possible to estimate the parameters k 1 and c, accord to as shown Fi. 3.! f y! f f y + f y c =! 3 3 C C C P C P P ( fc! fp ) fp ( + + ) fc fc yc fp yc fp yp k1 =! f f f (! ) C P P (3) Fiure 3. Noise output PSD of an operational amplifier obtaed from a circuit simulator (black) and reconstructed by Matlab (red). The PSD teral on 1 GHz bandwidth is nv, which means V n=33!v. 115 without fold consider fold 10 f Fiure. Flow chart of the proposed colored noise model. Once obtaed the analytic function of the noise PSD, it is possible to defe its Fourier series. In order to reduce the complexity of the model, we calculate the impact of the sampl operation on the noise spectrum the itialization phase, def an equivalent envelope limited the frequency rane [0; F s /]. In this way it is possible to use a smaller number of se-waves or, alternatively, to have a better frequency resolution with the same number of sewaves (Fi. 4). All the code is written us vectoriz alorithms, i.e. carefully avoid the use of for and while loops and replac them with the equivalent vector or matrix operation. This allows to speed-up simulations [6]. Sce with this model we can clude the data com form the circuit simulator, it is also possible to evaluate the impact of techniques as auto-zero or correlated double sampl (CDS) on the performance of the whole converter [5]. Fiure 4. Noise output PSD the band [0 F S] before and after hav considered the fold due to the sampl operation. IV. SIMULATION RESULTS To validate the proposed model, we performed several simulations with Simulk us the model shown Fi. 7 of the nd order modulator of Fi. 1. A sampl capacitor C S of 1 pf was chosen. The circuit was simulated for two different values of the sampl frequency F s (.5 MHz and 1.5 MHz, assum a jitter of 1 of the clock period) with different values of the oversampl ratio (OSR) to hihliht the impact of 1/f noise different operat conditions (Table 1 and Fi. 6). The different versions of the toolbox were compared itializ random enerators with the same seeds to better evaluate the alorithms. As operational amplifier we used a simple differential pair with active load and a bias current of 40!A, hav a dc a of 40 db and a abandwidth (GBW) product of 6 MHz. Its output noise PSD 5983

4 has already been reported Fi.. A transistor level noise simulation ( time doma) of the!" modulator with F s =1.5 MHz and OSR=56 was made to verify the improvement simulation accuracy of the proposed colored noise block. TABLE I. SIMULATED PERFORMANCES F s=.5 MHz OSR=51 Bandwidth=.4 khz Colored Noise Model Colored Noise Model with Autozero SD Toolbox Model Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero OSR=56 Bandwidth=4.9 khz Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero Fiure 5. Noise output PSD modeled by the orial (black) and the proposed block with (red) and without (reen) autozero. The PSD was obtaded avera ten FFTs on a wdow of 15 pots. 0 OSR=64 Bandwidth=19.5 khz Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero SNR = 97.7dB Rbit = bits F s=1.5 MHz OSR=51 Bandwidth=1. khz Fiure 6. PSD of the nd order!" modulator with F s=1.5 MHz and OSR=56. It is clearly visible the colored noise floor. V. MULTI-BIT QUANTIZER MODEL It is well known [5] that a mismatch amon capacitors the ternal DAC of a multi-bit!" modulator causes an crease the noise floor and the harmonic distortion. Performance deradation is proportional to capacitor standard deviation (#), iven by: "! C# k $ % C & =! ( ) W' L [% / m] (4) Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero OSR=56 Bandwidth=.4 khz Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero Transistor-level noise simulation OSR=64 Bandwidth=9.7 khz Ideal SD Toolbox SD Toolbox update SD Toolbox update w/ autozero

5 Sampl Jitter SOURCE OpNoise Jitter kt/c b b kt/c Simulk block SD Toolbox SD Toolbox update OpNoise 1- kt/c b 1- REAL Interator 1- REAL Interator Ga ADC ADC-DAC DAC Vout OUTPUT Noise Fiure 7. Simulk model of the!" modulator simulated with blocks troduced the previous version of SD Toolbox and those proposed this paper Therefore, # is versely proportional to the square root of the capacitor size (the constant k depends on the technoloy and is usually provided by the silicon foundry). Consider that the sampl capacitor value impacts the constrats of almost all basic build blocks (e.. operational amplifiers and voltae references) it has to be determed at the very ben of the desin phase. This makes approaches based on circuit simulator (e.. Montecarlo simulation) effective (not only time consum) capacitor mismatch not considered capacitor mismatch considered SFDR = 96 db th 9 th bw 5E 1E3 E3 3E3 Fiure 8.!" modulator output spectrum with and without capacitor mismatch. The FFT is performed on a wdow of 17 pots. Therefore, we developed a block which models the ADC and DAC of a!" modulator, clud the mismatch effects. This block can be used to evaluate if, iven a sampl capacitor size, the performance deradation due to mismatch can be considered neliible with respect to thermal noise, or if some correction technique, e.. dynamic element match (DEM), has to be applied (Fi. 8). The ternal DAC was supposed to have an odd symmetry (as it happens reality all fully differential circuits and all sle ended circuits carefully desined), which means that the same elements are used to construct both positive and neative values. Under this assumption no even distortion can be troduced by DAC. This shrewdness is fundamental to avoid overrat mismatch effect on the output spectrum. CONCLUSIONS In this paper we presented an extension of the SD Toolbox, which cludes a more eneral noise model with also flicker noise and a multibit quantizer model consider capacitor mismatches. Transistor level simulation have demonstrated that, under specific conditions, the proposed noise model achieves results by far more accurate than the orial one. Moreover, the multibit quantizer model allows us to accurately estimate the sampl capacitance value required for achiev a iven harmonic distortion at the very early stae of the desin. REFERENCES [1] S. Briati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, F. Maloberti, Model sima-delta modulator non-idealities SIMULINK, Proceeds of ISCAS '99, Vol.,, pp , [] P. Malcovati, S. Briati, F. Francesconi, F. Maloberti, F. Cusato, A. Baschirotto, Behavioral model of switched-capacitor sima-delta modulators, IEEE Trans. on Circuits and Systems I, Vol. 50, No. 3, pp , 003. [3] Cateory: Control Systems, File: SD Toolbox [Onle]. Available: [4] J. Silva, U. Moon, J. Steensaard, G. Temes; Wideband lowdistortion delta-sima ADC topoloy, Electronics Letters, Vol. 37, pp , June 001. [5] C. Enz and G. Temes, Circuit techniques for reduc the effects of op-amp imperfections: autozero, correlated double sampl and chopper stabilization, Proc. IEEE, Vol. 84, pp , Nov [6] SIMULINK and MATLAB Users Guides, The MathWorks, Inc., Natick, MA, [7] S. Norsworthy, R. Schreier, G. Temes, Delta-sima data converters: Theory, desin and simulation, IEEE Press, Piscataway, NJ,