Optimizing Power of Switched Capacitor Integrators in Sigma-Delta Modulators

Transcription

1 Feature Optimizing Power of Switched Capacitor Integrators in Sigma-Delta Modulators Curt Karnstedt Abstract This work describes a method that computationally determines the minimum required power and sampling capacitance for a switched capacitor integrator in a sigma delta modulator, given the modulator architecture, coefficients, and desired SNDR target. The design space is quickly explored with discrete time simulations that model the finite gain, settling dynamics, and thermal noise of the integrators. Insight gained from simulation can help the designer choose the number of quantizer levels in a multi-bit architecture or help him or her decide if a higher performance op amp and/or different modulator architecture is needed to attain the required power performance. Digital Object Identifier /MCAS Switch capacitor (SC) integrators are a basic building block of SC Sigma-Delta 1gD2 modulators. While continuous time gd modulators are becoming more popular for their low power in wideband applications, discrete time gd modulators will keep their place in applications where it is desirable to maintain robustness without the need to tune passive elements, or in applications where one ADC needs to work at many different sample rates. In the future we may see more hybrid modulators that combine continuous time integrators and discrete time integrators to get the advantages 64 IEEE CIRCUITS AND SYSTEMS MAGAZINE X/10/$ IEEE FOURTH QUARTER 2010

2 of both. In any case, SC gd modulators will continue to be used for the near term if not long term. When designing a SC gd modulator, it is necessary to run a discrete time system level simulation to verify the modulator s performance. The most basic modulator model defines the difference equations for each integrator, and it allows the designer to examine the modulator s signal-to-quantization noise performance and tonal behavior. A more accurate representation of the modulator can be obtained by creating a unique behavioral model of each integrator, which includes non-idealities such as capacitor thermal noise, op amp noise, slewing, and settling. This allows the designer to optimize the op amps and capacitors in each integrator stage to achieve the desired ADC resolution, without overdesigning them. A good deal of confidence in the design can be gained before simulating modulator blocks in SPICE, and the discrete time simulation runs quickly. The modulator model can be built and simulated using Matlab, Simulink, Verilog-A, etc. Python was used for the examples in this paper. It is a general purpose object oriented language, and system blocks can be created as instances of a master with unique parameters, allowing reuse of the master definition of the block. This is similar to how Simulink or most custom IC design tools work. Once a block is instantiated, its parameters can be easily changed to optimize the system. The Python language has downloadable modules, Numpy and Scipy, which provide matrix manipulation capability and signal processing routines for FFTs, window functions, filter design, and the like. Table 1. Parameters that change from phi1 and phi2. Parameter phi2 phi1 C L Load capacitance C L,phi2 C L,phi1 C O_EQ C I_EQ I o_gamma v 0 beta tau Equivalent output capacitance seen from v a node Equivalent input capacitance seen from v o node (Current delivered to v a node)/(total op amp output current) Gain bandwidth of op amp (radian freq.) Beta of op amp feedback network Settling time constant C L,phi2 1 C L,phi2 1C I 1 C R 1 C P 2 1 C I 1 C R 1 C P C I_EQ,phi2 C I_EQ,phi2 1 C L,phi2 perfect on phi1 and that the entire voltage v i appears across C I and 2v R on C R in the sampling phase. Figure 1 shows the single ended version of the integrator. Figure 2 shows the equivalent circuit model of the op amp. It is a single stage transconductance amplifier, with transconductance g m, output resistance R o, and input differential pair tail current I o. This model fits several types of op amp topologies used in SC circuits. For class AB, slew rate boosted, two stage, or dynamically biased op amps, a different model must be used. The voltage on v I and v R are sampled and held on phi1, and charge is transferred to on phi2. The ideal difference equation for the integrator is C O_EQ g m C I_EQ,phi2 1 C L,phi2 C L,phi1 1 C L,phi1 C P 1 C P C I_EQ,phi2 C I_EQ,phi2 1 C L,phi1 g m C I_EQ,phi1 1 C L,phi1 1 C I 1 C R 1 C P 1 C P 1 1 v 0,phi2 beta phi2 v 0,phi1 beta phi1 C I_EQ Equivalent Circuit Model of the SC Integrator The integrator to be modeled is the commonly used noninverting type and is shown in Figure 1. C I is the sampling cap, C R represents the equivalent capacitance for a DAC or other capacitive feedback path, C P is the parasitic capacitance on the op amp virtual ground node, v a, and C L is the total load capacitance on v o. The settling dynamics of the op amp change from one phase to the next due to the fact that C L, C I_EQ, C O_EQ, and beta change as capacitors are switched in and out, as shown in Table 1. The behavioral model assumes that the sampling is 1 C 1 2 v a v 1 CP v O C L 1 C R 2 v R 2 1 Figure 1. Non-inverting SC integrator. Curt Karnstedt, 4616 Hibiscus Valley Dr, Austin, TX 78739, USA. curt.karnstedt@ic-fusion.com. FOURTH QUARTER 2010 IEEE CIRCUITS AND SYSTEMS MAGAZINE 65

3 + V in g m V in g m V in I o Figure 2. Single stage op amp model. R 0 V 0 Discrete Time Behavioral Model of the SC Integrator It is desired to create a discrete time model that describes the integrator voltages at three time points per phi2-phi1 cycle: the beginning of phi2, the end of phi2, and the end of phi1. This is achievable because the voltage waveforms of the integrator are comprised of exponentials and ramps, and therefore the voltages at any point in time can be calculated as a closed form solution. Listing 1 shows the model output for the voltage v a of an integrator with the same parameters and conditions as that of Table 2, while Listing 2 shows the same kind of information for v o. The equations used to calculate these voltages are described in latter sections. v O 3n4 5 v O 3n v I 3n4C I 2 v R 3n4C R 2 /. (1) A realistic model takes into account the finite op amp gain and bandwidth, op amp slew rate, parasitic capacitances, and noise. Consider an integrator with the parameters in Table 2. With a DC signal of 0.5 V at v i and 0.0 V at v r, an ideal integrator adds 0.4 V to the output on every cycle instantaneously. The plots of Figure 3 and Figure 4 show how the real integrator differs under these conditions. At the beginning of phi2, both v a and v o experience a voltage spike. Afterward, the amplifier slews and then settles linearly to a value that is short of the ideal. Table 2. Integrator parameters. C I 0.4p C L 0.3p v i 0.5 V DC C R 0 I o 2e-4 f s 150 MHz C P 0.2p g m 2e-3 0.5p R o 5e5 mv 300 Voltage v (v a ) v (phi2) phi2 Slewing I o /g m Settling phi1 v (phi1) mv Time (ns) Figure 3. v a for integrator with parameters in Table 2. v a The SC Integrator Model Object A class, the master, was created for the switched capacitor integrator and called sc_int. Stored with this class are the parameters related to the integrator components, such as the op amp parameters and capacitor values, as well as the arrays that represent noise sources. The functions that model the integrator s settling dynamics, such as slewing and settling, are also included. In the following Python statements, instance i1 is created with the default values for sc_int, and unique parameters are assigned to it in the next statement. After i1 is created, it can be connected to other modulator blocks, which are described similarly. i1 = sc_int() # create integrator i1 i1.setparams({ Ao :1e3, Io :5e-4, cr :0.2e-12, ci :0.3e-12, cint :0.4e- 12, cl1 :0.2e-12, W :64e-6, L :0.8e-6}) # define parameters for i1 After a simulation is run, the integrator voltages can be plotted as a function of time: stem t[49500:50000]/1e-6, i1.vo[49500:50000,0] # begin of phi2 stem t[49500:50000]/1e-6, i1.vo[49500:50000,2] # end of phi1 The next sections discuss the details of the behavioral model. Modeling Initial Charge Sharing and State Saturation It is necessary to first model the charge sharing that occurs when the phi2 switch is closed. For these calculations, it is assumed that the switches have no resistance and that the voltages at v a and v o change instantaneously; therefore, the voltage swings calculated here will be the worst case. 66 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2010

4 The following equations describe the charges that exist prior to the closing of the phi2 switch: mv v (v o ) v (phi2) v (phi1) 788 m 792 m qn = sqrt(qnth[n]**2 + qnop[n]**2) qi = ci*vi - cr*vr qa = va[n-1,2]*(cp + co_eq) qn is the RMS sum of the equivalent capacitor thermal and op amp noise charges, which are discussed later. qi is the total charge on the input and reference capacitors. qa is the charge on the v a node left over from the previous cycle. Calculating va just after the phi2 switch is closed: va[n,0] = (qa - qi - qn)/ (ci + cr + cp + co_eq) if va[n,0] < vl: va[n,0] = vl if va[n,0] > vh: va[n,0] = vh va[n,0] is the voltage on v a after charge sharing. If v a goes outside the range limits vh and vl, then it is limited to vh and vl. This models the loss of charge that would occur if v a went outside the power rails. To find vo: Dv o 5Dv a 1 C L Voltage vo[n,0] = (va[n,0] - va[n-1,2]) * cint/ (cint+cl) + vo[n-1,2] if vo[n,0] < vl: vo[n,0] = vl if vo[n,0] > vh: vo[n,0] = vh phi2 158 m 392 m phi1 396 m v o Time (ns) Figure 4. v o for integrator with parameters in Table m the model produces the correct output when the sample period is very large. Only the effects of finite op amp gain will come into play. By setting the sum of the charges in the phi1 phase equal to the sum of the charges for phi2 (obeying the conservation of charge) and solving for v o [n], the following equations result. v o 3n4 5 v o 3n 2 14 a1 2 k A 0 b 1 k # v i_eq 3n4 k 5 C I 1 C R A C. (2) I 1 C R 1 C P Listing 1. v a (Volts) at beginning of phi2 (1), end of phi2 (2), end of phi1 (3), for integrator with parameters in Table 2. A 0 The values of v a and v o at the beginning of phi2 are now known. The voltages are limited by vh and vl, and this is a basic way of modeling the saturation of the integrator states. A real op amp will often have a useful output range less than the supply range, so the designer may want to change vl and vh to be something less than the power supply. A flag can be created which lets the designer know when the voltages go outside the boundaries that are set. Modeling the Effect of Finite Op Amp Gain The next step is to calculate v o at the end of phi2 for the case where the op amp has enough time to settle completely. The designer can use this value to check that Time Step v a,phi2_begin v a,phi2_end v a,phi1_end Listing 2. v o (Volts) at beginning of phi2 (1), end of phi2 (2), end of phi1 (3), for integrator with parameters in Table 2. Time Step v 0,phi2_begin v 0,phi2_end v 0,phi1_end FOURTH QUARTER 2010 IEEE CIRCUITS AND SYSTEMS MAGAZINE 67

5 This calculated value for v o is stored in v o [n, 3]. The value of v o [n 2 1] in the equation above is taken from vo[n 2 1,2], which is the value of v o at the end of phi1 from the previous cycle. v i_eq 5 (ci * vi 2 cr * vr 1 qn)/ (ci 1 cr), and it is the equivalent input voltage. A 0 is the gain of the op amp. Equation (2) is of the form of a lossy integrator. The integrator loses a voltage of v o [n 2 1] * (k/a 0 ) on every cycle, and the integrator inputs are scaled by k and added. If A 0 goes to infinity, the equation for v o [n] has the same form as the ideal equation for the SC integrator (1). Listing 3 shows the updated v o matrix, containing values at beginning of phi2 in the first column and the values for complete settling in the last, with the values in the middle columns to be computed next. Modeling Slewing and Settling Behavior An N 3 2 array called st2 was created, and it stores the slew time and settling time during for phi2 on each time step. Depending on value of v a at the beginning of phi2, the op amp will start slewing or not. If it is slewing, the slew time for phi2, st2[n, 0], is calculated, v Figure 5. Beginning of phi2 (i1.vo[:,0], gold) and end of phi1 (i1.vo[:,2], blue) us and the remainder of the phi2 is devoted to settling and is called st2[n, 1]. if abs(va[n,0]) > Io/gm: st2[n,0] = (abs(va[n,0])-gm/io) *(ci+cr+cp)/(io*io_gamma) # slew time st2[n,1] = tphi st2[n,0] # settling time To get the slew time, the voltage difference Dv between va[n, 0] and 1/2(Io/gm) is computed. 1/2(Io/gm) is the voltage that marks the boundary between slewing and settling on the v a node, and Dv is the absolute voltage that node v a must travel before the op amp begins to settle linearly. The equation Dt 5 C * Dv/I gives the slew time, where I 5 Io_ gamma, the current that is fed back to the v a node from the op amp output. Three possibilities exist for the op amp during phi2: 1) It slews for all of phi2. 2) It settles linearly for all of phi2. 3) It first slews and then settles linearly. The third case is discussed here. v o and v a after slewing are described by the following equations vo[n,1] = vo[n,0] - numpy. sign(va[n,0])*io*st2[n,0]/(ci_eq+cl) va[n,1] = va[n,0] \ numpy.sign(va[n,0])*io*st2[n,0]/(ci_ eq+cl)*beta where numpy.sign( ) returns the sign of its argument. After slewing is complete, va[n, 1] is equal to 1/2(Io/gm). It continues to change as the op amp settles linearly, and both voltages follow a decaying exponential. To calculate them at any point in time, only the starting and final values and the time constant are needed. The starting values are the results for v o and v a after slewing. The final values can be obtained two ways. One is to use the value vo[n, 3] calculated from the equation for finite op amp gain, which is the asymptotic final value for v o. dbfs 100 Listing 3. Column 4 contains the value of v o for complete settling Freq (MHz) Figure 6. Spectrum for modulator with non-idealities (blue) and quantization noise only (gold). Time Step v o,phi2_begin v o,phi2_end v o,phi1_end v o, complete setting [] [] IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2010

6 The final value for v a is 2vo[n, 3]/A 0. Another more general way to find the Dv a and Dv o required for complete settling in any op amp feedback network is to use the following equations. v o,start 1Dv o 5 1v a,start 1Dv a 212A 0 2Dv o 5 Dv a beta solving them yields Dv a 52 A 0 v a,start 1 v o,start A beta Dv a is the voltage that v a must travel from its starting point in order for complete settling to occur. This equation is used to solve for the voltages at the end of phi2. delva = -((Ao*va[n,1]+vo[n,1])/ (Ao+1/beta))*(1.0 \ numpy.exp(-st2[n,1]/tau)) va[n,1] = va[n,1] + delva vo[n,1] = vo[n,1] + delva/beta If st2[n, 1]/tau is very large, the final value for vo[n,1] will match vo[n, 3] exactly, indicating that complete settling has been achieved in phi2. The same equations are used to solve for voltages in the phi1 phase, except that now the capacitor network, beta, and tau are different, which changes the settling dynamics. An N 3 2 array called st1 was created, and it stores the slew time and settling time during for phi1 on each time step. The final values for v a and v o at the end of phi1 are stored in va[n, 2] and vo[n, 2]. Modeling Capacitor Thermal Noise SC integrators are normally designed so that capacitor thermal noise is the main contributor of noise. To calculate it, the noise contributions on phase phi1 and phi2 must be considered. The sampled and held total noise charge on the sampling capacitors at the end of phi1 is q nth,phi1 5 "kt1c I 1 C R 2. k is Boltzmann s constant and T is the temperature. On phi2, the bandwidth of the op amp will limit the wideband noise of the switch resistances, and this reduces the total integrated noise. The additional thermal noise charge delivered to during the phi2 phase will be q nth,phi2 5 "kt1c I 1 C R 2 3beta phi2 v 0,phi2 1C I 1 C R 2R on,eq 4, where R on,eq is the parallel combination of the series switch resistances for C I and C R, assuming that they scale with C I and C R. The term in brackets is the ratio of the op amp bandwidth to the switch thermal noise bandwidth. It is assumed that the radian frequency, beta phi2 * w o,phi2, is smaller than 1C I 1 C R 2R on,eq. With q n,phi1 and q n,phi2 uncorrelated, the total thermal noise charge from capacitors is q nth 5 "kt1c I 1 C R 31 1 beta phi2 v 0,phi2 1C I 1 C R 2R on,eq 4. If the bandwidth limiting nature of the op amp is not taken into account, q nth 5 "12kT1C 1 1 C R 22, which is the same as the noise charge delivered in one cycle by a resistor equal to 1/ 1f s *1C I 1 C R 22. For the differential case, the number of components that contribute noise double, so another factor of 2 is included to get the total noise charge. q nth,diff 5 "2q nth. To represent the noise charge, a random noise sequence is created with an RMS value of q nth,diff. The randn function below produces a Gaussian random noise sequence with an RMS value equal to 1. qnth[n] = numpy.random.randn(n) *qnth_diff. qnth[n] is combined with op amp noise and added to the v a node on each cycle as seen earlier. Modeling Op Amp Noise The noise of the op amp can be represented as two uncorrelated voltage sources in series with the op amp input. One models the thermal noise and the other models the flicker noise. Both can be included in the behavioral model, but this paper focuses on the thermal noise. The equivalent input power spectral density (PSD) depends on the op amp topology and component sizes v nth,i 1f 2 5 v nth,i,diff2pair 1f 2 1 v nth,i,pmos load1f 2 1 v nth,i,nmos load1f 2 1 c 5 4kT a 2 b2 c11 g m,pmos load 3g m g m 1 g m,nmos load g m 1 c d. The extra factor of 2 before the bracket is due to the fact that there are two transistors that contribute noise per diff pair or load. The designer needs to calculate the actual v 2 nth,i1f 2 based on the topology and components of the amplifier. The noise PSD at the output of the integrator is 2 v nth,o 1f 2 5 v 2 nth,i1f 2 beta. 2 FOURTH QUARTER 2010 IEEE CIRCUITS AND SYSTEMS MAGAZINE 69

7 Assuming that the amplifier frequency response has a single pole roll off, the effective noise bandwidth is BW eff 5 v 0 beta p The total output noise is calculated v nth,o 5 v nth,o 1f2 BW eff 5 v nth,i 1f 2 v p beta. C L, C I_EQ, and beta are different for phi1 and phi2, so the output noise will also be different for each phase. To get the RMS value for the noise at the op amp output, the noise power in phi1 and phi2 must be multiplied by 0.5 and summed. This assumes that the duty cycle for phi1 and phi2 is v nth,o 5 v nth,i 1f p a v 0,phi1 1 v 0,phi2 b0.5. beta phi1 beta phi2 Modulator SNDR (db) Ci (pf) l = 0.5 ma, C l = 0.2 pf SNDR > 80 db Op Amp Current (ma) Figure 7. Modulator SNDR for modulator with nine quantizer levels. Modulator SNDR (db) Ci (pf) l = 1.1 ma, C l = 0.2 pf SNDR > 80 db Op Amp Current (ma) Figure 8. Modulator SNDR for modulator with five quantizer levels. w 0 / 12 *pi2 is assumed to be much larger than the sampling frequency. Therefore, sampling v nth,o will cause aliasing, and all of v nth,o will appear in the spectrum from DC to the sampling frequency. To model this, a random sequence with a RMS value of v nth,o is created. vnop[n] = vntho * numpy.random.randn(n). The final step is to convert v nth,o to a charge that is combined with the capacitor thermal noise charge and added to the charge at the v a node on every cycle, as shown earlier. qnop[n] = cint * vntho * numpy.random. randn(n). Putting it Together The following example is for a 3rd order, multi-bit, SCgD modulator. The sample rate is 150 MHz, the bandwidth is 2 MHz, the input signal frequency is 500 khz, and the full-scale input is 1.2 volts. Device parameters have been taken from a 0.13u process. Io and C I of integrator 1 are swept to find the optimal Io and C I for a SNR of 80 db. The ratios of C I to C R and are held constant. 0.2 pf is used for the sampling cap of the next stage. It is assumed that 3beta phi2 * w o,phi2 * 1C I 1 C R 2R on,eq 4, The op amp topology is a folded cascode with a NMOS input diff pair, and its device sizes scale with I o. Input diff pair and load devices are calculated from their desired v d,sat. Op amp output capacitance is calculated accordingly. The capacitors of the CMFB circuit scale with the NMOS load gate capacitance. The total op amp current is 2.2 p Io. The following equations are used to calculate C P and g m : cp 5 Cox * W * L gm 5 sqrt12 * K' * 1W/L2 * 1Io/222. Figure 7 shows that for this modulator architecture and SNR target of 80 db, setting C I to 0.2 pf and the op amp current to 0.5 ma will achieve the desired resolution for 9 quantizer levels. If the number of quantizer levels is reduced to 5, the power increases by just over a factor of two, as indicated in Figure 8. What Is Missing The model does not take into account the transient created by sampling capacitors of the next integrator stage and the common mode feedback capacitors, all of which switch in on phi1 in this topology. This transient can be modeled using the same methodology, where charge sharing happens at the beginning of phi1, and the same slewing and settling equations are used to calculate the voltages at the end of phi1. 70 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2010

8 There are other non-idealities that have not been modeled here. The gain of the fully differential op amp is dependent on its voltage output. The sampling switches inject charge non-linearly as a function of the input voltage. Both of these non-idealities create harmonic distortion in the modulator output. These have been left out of the model because they do not strongly determine the integrator power. The effect of switch resistance on settling has not been modeled, but including it may show that more op amp power is needed to compensate for the modest increase in the settling time constant. Conclusions This paper demonstrates that a behavioral model, which models charge sharing, slewing, settling, and total thermal noise, can be used to optimize the power of a SC integrator employing a single stage, class A op amp. Information gained from such an optimization can be used to decide whether a different modulator architecture or more complex op amp is needed, or it can be used determine the number of quantizer levels needed in a multibit modulator. Once the power has been optimized, the designer can use the optimization result as a baseline to design the integrator with real devices, discovering where additional power may be needed to accommodate other non-idealities that were not addressed. Curt Karnstedt is currently Member of Technical Staff at Equiphon, Inc. in Austin, TX. He has worked for such companies as Texas Instruments and Integrated Device Technology, as well as serving as an independent consultant. He has designed ICs for audio, portable, and power management applications, and his professional interest is in the modeling, design, and optimization of analog integrated circuits and systems. He received the BSEE and MSEE degrees from the Georgia Institute of Technology. References [1] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, [2] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, [3] G. Suárez, M. Jiménez, and F. O. Fernández, Behavioral modeling methods for switched-capacitor SD modulators, IEEE Trans. Circuits Syst., vol. 54, no. 6, pp , June [4] R. D. Rio, F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vazquez, Reliable analysis of settling errors in SC integrators Application to the design of high-speed sigma-delta modulators, in Proc. IEEE Int. Symp. Circuits and Systems, 2000, vol. 4, pp [5] A. Leuciuc and C. Mitrea, On the effect of op amp finite gain in deltasigma modulators, in Proc. IEEE Int. Symp. Circuits and Systems, 2000, pp [6] W. Sansen, Transient analysis of charge transfer in SC filters: Gain and error distortion, IEEE J. Solid State Circuits, vol. SC-22, no. 2, pp , Apr [7] J. H. Fisher, Noise sources and calculation techniques for switched capacitor filters, IEEE J. Solid State Circuits, vol. SC-17, no. 4, pp , Aug [8] C. A. Gobet and A. Knob, Noise analysis of switched capacitor networks, IEEE Trans. Circuits Syst., vol. CAS-30, no. 1, Jan [9] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, Behavioral modeling of switched-capacitor sigma delta modulators, IEEE Trans. Circuits Syst. I, vol. 50, no. 3, Mar IEEE Technology Management Council The IEEE Technology Management Council provides tools to enhance your career and organizational effectiveness. As a member of the IEEE Circuits and Systems Society you are entitled to access all the publications, conferences, and enjoy the offerings of TMC. Visit to join your colleagues today! Professor Gianluca Setti CAS president University of Ferrara Digital Object Identifier /MCAS FOURTH QUARTER 2010 IEEE CIRCUITS AND SYSTEMS MAGAZINE 71