Design and Analysis of a Continuous-Time Common-Mode Feedback Circuit Based on Differential-Difference Amplifier

Transcription

1 Research Journal of Applied Sciences, Engineering and Technology 4(5): , 01 ISSN: Maxwell Scientific Organization, 01 Submitted: September 9, 011 Accepted: November 04, 011 Published: March 01, 01 Design and Analysis of a Continuous-Time Common-Mode Feedback Circuit Based on Differential-Difference Amplifier Alireza Saberkari, Rasoul Fathipour and Hamidreza Saberkari Department of Electrical Engineering, University of Guilan, Rasht, Iran Abstract: The main purpose of this study is to introduce a new continuous-time Common-mode Feedback Circuit (CMFB) based on Differential-Difference Amplifier (DDA) in order to achieve high speed, high loopgain, and simultaneously low distortion characteristics. Two control voltages with opposite variations used in the proposed CMFB make the loop-gain and speed enhancement of the circuit. Additionally, reducing the dc level and input signal amplitude of the CMFB by using source follower circuits helps to increase the effective voltage of differential pairs and hence the linearity performance of the circuit. HSPICE simulation based on 0.35 :m CMOS process is done in order to evaluate the performance of the proposed CMFB circuit and the results indicate that the proposed CMFB is faster than the typical one and has lower odd and even harmonics in comparison with the conventional CMFB. Key words: Common-mode feedback, differential-difference amplifier, high speed, low distortion, operational amplifier, transconductance INTRODUCTION The Common-mode Feedback Circuits (CMFB) are utilized to regulate the output Common-mode (CM) voltage level of fully differential operational amplifiers by adjusting their output CM current. There are several methods to implement a CMFB circuit that among of them using the Differential-difference Amplifier (DDA) is more prevalent due to the fact that it exhibits large transconductance and does not resistively load the main amplifier output (Silva-Martinez et al., 199; Czarnul et al., 1994; Luh et al., 000; Kwan and Martin, 1991; Zhang and Hurst, 006). Symmetrical differential pairs used in this structure obtain the output CM voltage level of the main amplifier, Voc, and compare it with the reference voltage, Vcm. The resulted error is returned to the main amplifier to adjust its bias current. Figure 1 shows the typical DDA-CMFB, which is called CMFB1 in this paper, and the main amplifier. There are some issues to be fulfilled when designing a good CMFB circuit (Choksi and Carley, 003). In most applications, the slew rate and unity-gain frequency of the CM loop should be comparable to that of the differential loop to avoid output signal distortion resulting from clipping due to slow settling of the output CM voltage. Also, the gain of the CM loop should be sufficiently large to obtain the CM voltage within the desired accuracy. The number of parasitic poles in the CM loop should be minimized. Furthermore, the CM loop should be adequately compensated by ensuring a good phase margin and a fast settling step response (Choksi and Carley, 003; Johns and Martin, 1996). In this study, a high speed, high loop-gain, and low distortion continuous-time DDA-CMFB is introduced by applying some modifications on the conventional CMFB circuit (CMFB1). LOOP-GAIN AND SPEED ENHANCEMENT Without the CMFB in the main operational amplifier shown in Fig. 1b when the total current of transistors M3 and M4 differs from that of M5, two cases may occur. First, the total current of M3 and M4 is more than that of M5. In this case, the output capacitors are charged and the voltage level of output nodes is increased until M3 and M4 enter to the triode region and their currents are decreased. In second case, when the total current of M3 and M4 is less than that of M5 the output capacitors are discharged and the voltage level of output nodes is decreased until M1, M, and M5 enter to the triode region. The CMFB1 shown in Fig. 1a is responsible for the accurate regulation of the current of M5 equal to the total current of M3 and M4. For this purpose, the output CM voltage level is sensed by two differential pairs (M9- M1) and compared with the reference voltage. Then the proportional current, Icms, is generated and mirrored to the tail current of the main amplifier. However, this mechanism is done through one path in the CMFB1 circuit and the CM Control signal (CMC) is applied to the gate of M5. In order to increase the loopgain and speed of the feedback loop, two control signals with opposite variations are used in the proposed CMFB (CMFB), as shown in Fig. a which one of them is applied to the gate of M5 (CMC1) and another one is fed Corresponding Author: Alireza Saberkari, Department of Electrical Engineering, University of Guilan, Rasht, Iran 45

2 Fig. 1: Typical DDA-CMFB circuit (CMFB1), the main operational amplifier Fig. : Modified CMFB for speed and loop-gain enhancement (CMFB), the main operational amplifier to the gate of M3 and M4 (CMC) of the main amplifier. Hence in the main amplifier shown in Fig. b, if the current of M5 is less than that of M3 and M4, one path increases the current of M5 and simultaneously anther path decreases the current of M3 and M4 and vise-versa. LINE ARITY ENHANCEMENT If it is assumed that the transistors of differential pairs (M9-M1) in CMFB1 operate in the active region and the difference of the main amplifier output CM voltage and reference voltage could be treated as small signal input, the following relation can be derived: I I I g ( V V ) 14 cms 8 m oc cm (1) where, g m is the transconductance of transistors M9-M1, V oc is the output CM voltage level of the main amplifier, and V cm is the reference voltage. Even if this voltage becomes large to force the transistors to be out of their linear region, Eq. (1) can be expressed as bellow (Gray et al., 001): pcox W I14 Icms I8 L 11 V Voc Vcm 4V od ov ( ) V od Voc Vcm V ( ) od 4 V 8 V 4 V od ov 4 V od ov.. () where, V ov is the effective voltage of differential pairs (M9-M1) and V od is the output differential-mode voltage of main amplifier. If V od / << V ov, Eq. () reduces to (1). 453

3 Voc-Vcm (mv) Rv (Kohm) Fig. 3: Error voltage versus variable resistor As it is obvious from Eq. (), for V oc V cm, l cms has terms that include even-order harmonics of V od. Hence, the even-order harmonics create in the frequency spectrum of I cms and therefore in V oc that degrade the overall linearity. As a primary solution for this issue, decreasing the error voltage (V oc -V cm ) is a simple way to reduce the nonlinear terms which can be realized by a variable resistor as shown in the CMFB circuit. In balance conditions and without any error voltage, the following relation can be extracted from Fig. : W ( 1 VDS5) L 5 W ( 1 VDS14) L 14 W W ( 1 VSD3) L L 3 W W ( 1 VSD16) L 16 L ( 1 VDS15) ( 1 VDS13) (3) If Eq. (3) is not valid due to the error voltage, changing the variable resistor will change the drain-source voltage of transistor M15 and hence Eq. (3) will be valid Fig. 4: Modified CMFB for linearity enhancement (CMFB3) Fig. 5: The proposed DDA-CMFB as well as the main amplifier 454

4 again. The error voltage variation of the CMFB circuit versus the variable resistor is shown in Fig. 3. However, the prefect cancellation of the error voltage is not possible due to the device mismatch, finite gain in the CMFB loop, thermal effect, and etc. An alternative way is that the effective voltage of differential pairs V ov is increased in order to reduce the nonlinearity. But this method makes it difficult that the transistors M7 and M8 stay in the active region. In order to determine the greatest effective voltage for transistors M9-M1 in balance conditions, assume that M9 is at the edge of cut-off region and all of the currents of M7 pass through M10. In this case V ov10 = %V ov where V ov is the effective voltage in balance conditions. If the minimum drain-source voltage required for transistors M7 and M8 remain in the active region is 50 mv and the output dc voltage level of the main amplifier is set to 1.8 V, the following relation can be derived: 18. ( V V ) V 50 TH, P ov DD mv (4) where, V TH,P is the threshold voltage of PMOS transistor. Assuming V TH,P = 750 mv and V DD = 3.3 V for a 0.35 :m CMOS process, V ov equals to 360 mv. Hence, in order to decrease the nonlinearity and according to V od / << V ov, V od, should be very small that causes a significant limitation on the output swing of the main amplifier. According to Eq. (4), V ov can be increased by decreasing the output dc level of the main amplifier. Also if the input signal amplitude of the DDA-CMFB is decreased in such a way that the output of the main amplifier remains constant, V ov /V od will be increased and thereby the linearity of the circuit will be improved. To realize this idea, three source follower circuits with small resistors at their source terminal can be utilized. But, small resistors will increase the power dissipation of the circuit. A simple solution for this problem is to take advantage of relatively large resistors and dividing them into two resistors, as shown in Fig. 4. By choosing appropriate values for the resistors, reduction of the dc level and signal amplitude can be done at the input of the DDA-CMFB. In Fig. 4, transistor M15 acts as a current source and provides the possibility of increasing the gain without any increase of V ov14. Also the loop-gain reduction due to the reduction of CMFB input signal amplitude is compensated. CIRCUIT CHARACTERIZATION With regard to the above discussion, the transistor level schematic of the overall proposed DDA-CMFB circuit as well as the main amplifier is shown in Fig. 5. In order to evaluate the performance of the proposed CMFB, the circuit is designed and simulated in HSPICE based on 0.35 :m CMOS process Path 1 Path K 10K 100K 1M 10M 100M 1G 10G Fig. 6: Loop-gain of the proposd DDA-CMFB 1.8v 1.6v 1.4v 1.v 1.0v 0.8v 0.6v Proposed CMFB 0.4v CMFB 1 0.v 0 10ns 0ns 30ns 40ns 50ns 1.8v 1.6v 1.4v 1.v 1.0v Proposed CMFB 0.8v CMFB 1 0.6v 0.4v 0.v 0 10ns 0ns 30ns 40ns 50ns Fig. 7: Transient response of CMFB1 and the proposed CMFB to a step voltage with 1 ns rise and fall time Figure 6 shows the loop-gain of the proposed circuit that includes two control paths. As can be seen, the magnitude and phase of two paths are completely matched for frequencies between 0 to fr (unity-gain frequency) and so the overall loop-gain which equals to the sum of the loop-gain of each path is twice of that in the conventional CMFB (CMFB1). In order to comparison the speed of the CMFB1 and the proposed CMFB, a V step voltage with rise and fall time of 1 ns is fed to the Vcm. Figure 7 shows the transient response of two circuits with 1pF load capacitors. As it is obvious, the modified circuit has faster response to the reference voltage variations. Figure 8 shows the FFT spectrum of Icms and Voc for the CMFB1 and the proposed CMFB. In both circuits V oc -V cm = 36 mv and V od(peak) = 800 mv, but V ov is 360 and 935 mv for the CMFB1 and the proposed 455

5 Icms(uA) k k 3k 4k 5k 6k 7k 8k 9k 10k 11k1k Icms (ua) Fig. 8: FFT spectrum of CMFB1, the proposed CMFB Icms(uA) k k 3k 4k 5k 6k 7k 8k 9k 10k 11k1k Icms(uA) Fig. 9: FFT spectrum with % device mismatch for CMFB1, the proposed CMFB CMFB, respectively. FFT spectrum reveals that the proposed circuit has better linearity performance in comparison with the typical CMFB due to the greater effective voltage of its differential pairs. 456

6 The point that should be mentioned is that when transistors of differential pairs in the CMFB are matched, only even-order harmonics of Vod appear in Icms and Voc as shown in Fig. 8. However due to the device mismatch, both odd and even harmonics of Vod affect the Icms and Voc (Zhang and Hurst, 006). Figure 9 shows the FFT spectrum of Icms and Voc with worst case mismatch of % in each differential pair of the CMFB1, source followers and differential pairs of the proposed CMFB. The FFT spectrum indicates better linearity performance of the proposed CMFB with device mismatch. CONCLUSION A high speed, high loop-gain, and low distortion DDA-CMFB is presented which consists of two control voltages with opposite variations in order to increase the loop-gain and speed of the circuit. On the other hand, reducing the dc level and input signal amplitude of the CMFB by using source follower circuits increases the effective voltage of differential pairs and improves the linearity of the circuit. HSPICE simulation based on 0.35 :m CMOS process has been done in order to evaluate the performance of the proposed CMFB circuit and the results indicate that the proposed CMFB is faster and has lower odd and even harmonics in comparison with the conventional CMFB. REFERENCES Choksi, O. and L.R. Carley, 003. Analysis of switchedcapacitor common-mode feedback circuit. IEEE Trans. Circ. Syst. II, 50(1): Czarnul, Z., S. Takagi and N. Fujii, Common-mode feedback circuit with differential-difference amplifier. IEEE T. Circ. Syst. I, 41(3): Gray, P.R., P.J. Hurst, S.H. Lewis and R.G. Meyer, 001. Analysis and Design of Analog Integrated Circuits. 4th Edn., Wiley, New York. Johns, D.A. and K. Martin, Analog Integrated Circuit Design. 1st Edn., Wiley, New York. Kwan, T. and K. Martin, An adaptive analog continuous-time cmos biquadratic filter. IEEE J. Solid-State Circ., 6(6): Luh, L., J. Choma and J. Draper, 000. A continuous-time Common-mode Feedback Circuit (CMFB) for highimpedance current-mode applications. IEEE T. Circ. Syst. II, 47(4): Silva-Martinez, J., M.S.J. Steyaert and W. Sansen, 199. Design Techniques for high-performance Full-CMOS OTA-RC continuous-time filters. IEEE J. Solid-State Circ., 7(7): Zhang, M.M. and P.J. Hurst, 006. Effect of nonlinearity in the cmfb circuit that uses the differentialdifference amplifier. Proc. IEEE Int. Symp. Circ. Syst. (ISCAS 06), pp: