SWITCHED CAPACITOR CIRCUITS
|
|
- Amos Mitchell
- 5 years ago
- Views:
Transcription
1 EE37 Advanced Analog ircuits Lecture 7 SWITHED APAITOR IRUITS Richard Schreier richard.schreier@analog.com Trevor aldwell trevor.caldwell@utoronto.ca ourse Goals Deepen Understanding of MOS analog circuit design through a top-down study of a modern analog system The lectures will focus on Delta-Sigma ADs, but you may do your project on another analog system. Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to recognize. EE37 7-
2 Date Lecture Ref Homework RS Introduction: MOD & MOD S&T -3, A Matlab MOD RS Example Design: Part S&T 9., J&M 0 Switch-level sim RS 3 Example Design: Part J&M 4, S&T B Q-level sim T 4 Pipeline and SAR ADs J&M,3 Pipeline DNL ISS No Lecture RS 5 Advanced ΔΣ S&T 4, 6.6, 9.4, B TMOD; Proj Reading Week No Lecture RS 6 omparator and Flash AD J&M T 7 S ircuits Raz, J&M T 8 Amplifier Design T 9 Amplifier Design T 0 Noise in S ircuits S&T Project Presentations T Matching & MM-Shaping RS Switching Regulator Project Report EE NLOTD: Schmitt Trigger Problem: Input is noisy or slowly varying V IN V OUT? t t Noisy Input lean Output How do we turn this into a clean digital output? EE37 7-4
3 Highlights (i.e. What you will learn today). Motivation for S ircuits. Basic sampling switch and charge injection errors 3. Fundamental S ircuits Sample & Hold, Gain and Integrator 4. Other ircuits Bootstrapping, S MFB EE Why Switched apacitor? Used in discrete-time or sampled-data circuits Alternative to continuous-time circuits apacitors instead of resistors apacitors won t reduce the gain of high output impedance OTAs No need for low output impedance buffer to drive resistors Accurate frequency response Filter coefficients determined by capacitor ratios (rather than R time constants) and clock frequencies apacitor matching on the order of 0.% - when the transfer characteristics are a function of only a capacitor ratio, it can be very accurate R time constants vary by up to 0% EE37 7-6
4 Opamps Basic Building Blocks Ideal usually assumed Some important non-idealities to consider include:. D Gain: sets the accuracy of the charge transfer, how grounded the virtual ground is. Unity-gain freq, Phase Margin & Slew Rate: determines maximum clock frequency 3. D Offsets: circuit techniques to combat this and /f noise orrelated Double Sampling, hopping apacitors Large absolute variation, good matching Large bottom plate capacitor adds parasitic cap EE Switches Basic Building Blocks MOSFET switches are good large off resistance (GΩ), small on resistance (00Ω -5kΩ, depending on transistor sizing) MOSFET switches have non-linear parasitic capacitors Non-Overlapping locks locks are never on at the same time Required so that charge is never lost/shared lock Generator previously discussed T EE37 7-8
5 Basic Sampling Switch MOSFET used as sample-and-hold When LK is HIGH, V OUT follows V IN through the lowpass filter created by R ON and R ON varies depending on V IN, V OUT, and V DD V IN V DD V OUT R ON When LK is LOW, V OUT holds the value on V SS V IN V OUT EE On-Resistance Variation With an NMOS sampling switch, as V IN approaches V DD -V TH, R ON increases dramatically In smaller technologies, as V DD decreases the swing on V IN is severely limited R ON = W μnox ( VDD VIN VTH) L R ON V DD -V TH Sampling switch must be sized for worst case R ON so that the bandwidth is still sufficient V IN EE37 7-0
6 On-Resistance Variation PMOS switches suffer from the same problem as V IN approaches V T omplementary switch can allow rail-to-rail input swings Ignoring variation of R ON,n R ON,p V TH with V IN, R ON,eq is R ON,n constant with V IN if R ON,p W W μnox = μpox L L V TH V DD -V TH V DD V IN EE37 7- Settling Accuracy Two situations to consider ) Discrete-time signal When analyzing a signal within the switchedcapacitor circuit (for example, at the output of the first OTA) ) ontinuous-time signal When analyzing a signal that is sampled at the input EE37 7-
7 Settling Accuracy DT Discrete-Time Signal Settling Error = e -T/4R For N-bit accuracy in T/4 seconds T RON < 4N ln This is the maximum R ON (for a given ) Example: Assume GHz to 4 GHz variation of Input sinusoidal signal at 50 MHz π RON For f S =00MHz, N= bits with discrete-time signal (typically you are limited by the OTA) EE Settling Accuracy T ontinuous-time Signal R ON acts as a low-pass filter and introduces amplitude and phase change Variations in the input signal size cause variations in R ON, causing distortion in the sampled signal Both the amplitude and phase vary which one causes distortion? EE37 7-4
8 Amplitude Error Less significant error Due to variation in magnitude of low-pass filter At 50 MHz (with same R ON variation as DT case), maximum possible error is 0.% EE Distortion in sampled T input Input ~50 MHz, sampled at 00MHz Distortion at 57dB, or ~9 bits This is larger than the maximum possible error due to amplitude variation dbfs EE Normalized Frequency
9 Phase Error More significant error Due to variation in phase of low-pass filter At 50 MHz (with same R ON variation as DT case), maximum possible error is a few percent - error is less than that EE harge Injection When a transistor turns off, the channel charge Q H goes into the circuit Doesn t exactly divide in half - depends on impedance seen at each terminal and the clock transition time Q = WL ( V V V ) H ox DD IN TH harge into V IN has no impact on output node Doesn t create error in the circuit harge into causes error ΔV in V OUT V IN Q H Q H V OUT Δ V = Q H ( ) WL V ox DD V IN V TH = EE37 7-8
10 harge Injection In previous analysis, charge injection introduces a gain and offset error This is still linear and could be tolerated or corrected VOUT = VIN ΔV WLox WLox( VDD VTH ) = VIN + But V TH is actually a function of ~ V IN Introduces non-linear term that cannot be corrected in the circuit EE harge Injection vs. Speed harge injection Proportional to transistor size (WL) Speed R ON inversely proportional to aspect ratio (W/L) Figure of Merit Product of speed (/τ) and charge injection (/ΔV) WLox ( τδ V) = ( VDD VIN VTH ) μnox( W/ L)( VDD VIN VTH) μn = L EE37 7-0
11 lock Feedthrough Overlap capacitance allows clock to couple from the gate to drain/source terminals hange in voltage ΔV independent of the input signal Error is an offset voltage which is cancelled with differential operation V LK 0 OV V IN OV V OUT Δ V = ov + ov V LK EE37 7- harge Error ancellation Differential operation ancels offset errors, depending on the matching between differential circuits Applies to signal dependent portion of charge injection error, and clock feedthrough error omplementary Switches Error cancelled for input level WL n n ox( VLK VIN VTHN ) = WL p p ox( VIN VTHP ) lock feedthrough cancelled depending on similarity of overlap capacitance for PMOS and NMOS switches EE37 7-
12 harge Error ancellation Dummy Switch Use second transistor to remove charge injection by main transistor Inverted clock operates on dummy switch harge from M: qm = WL ox( VK VIN VTH)/ harge from M: qm = WL ox( VK VIN VTH) If charge splits equally in M (not quite true), then with M half the size of M, q = q M M EE Sample and Hold Amplifier Input dependent charge from S onto When S turns off, charge q adds to V OUT is then equal to V IN +q/ where q has a non-linear dependence on V IN We can improve on this by making V OUT independent of sampling switch charge EE37 7-4
13 Two phases S/H Amplifier Phase : S and S closed, V IN sampled on Phase : S 3 closed, is tied to V OUT Phase harge on is V IN S opens, injecting signal indep. charge at node X Then S opens, injecting signal dependent charge q onto + p EE Phase S/H Amplifier Node X is a virtual ground and charge on p is zero harge on is still V IN S 3 injects charge on X that must be discharged due to virtual ground node it does not disturb charge on V OUT =V IN S / S 3 are non-overlapping, S slightly ahead of S EE37 7-6
14 Gain of the S/H Finite OTA gain reduces gain of sampler On Phase, charges to V IN On Phase, node X goes from 0 to V X = -V OUT /A harge comes from, changing q to V IN + p V X V OUT -(V IN + p V X )/ = V X V OUT VIN = p + A + p VIN + A EE Speed of the S/H In sampling mode (Phase ) At node X, R X ~ /G m, τ ~ (R on +/G m ) In amplification mode (Phase ) Replace charge on by voltage source V IN (like switching in voltage source at start of Phase ) After analysis, τ = ( L p + p + L )/G M Reduces to τ ~ L /G M if p is small R on V IN V IN R on X G M V X R O V OUT p X G M V X R O V OUT L EE37 7-8
15 Basic Amplifier Sampling phase when S and S closed Input signal sampled onto Amplifying phase when S 3 closed harge on transferred to so that the final output is VOUT = VIN EE Basic Amplifier S must open before S for the charge injection to be signal independent harge from S opening is deposited on, but is not signal dependent harge from S opening causes glitch in V OUT When S 3 closes, V OUT goes to final value, regardless of what happened between S opening and S 3 closing EE
16 Precision Gain- Sampling phase when S, S, S 3 closed Input signal sampled onto and Amplifying phase when S 4, S 5 closed harge on is transferred to, doubling the charge on Final output is V IN since = S 4 S S 3 V IN S S 5 V OUT EE Precision Gain- How is it more precise? The feedback factor in both gain circuits is + + p In the precision Gain- circuit, =, while the basic amplifier has =, resulting in a smaller feedback factor and a slower circuit The gain error is inversely proportional to the feedback factor, so the precision circuit is more accurate for a given amplifier gain A V + OUT + p VIN A EE37 7-3
17 Resistor Equivalence of S Average current through switched-capacitor φ : Q = V φ : Q = V Q Q ( V V) IAVG = = T T Equivalent current through a resistor (f IN << f S ) V V IEQ = REQ T R = = f EQ EE37 S 7-33 Switched-apacitor Integrator s s V I V O Two non-overlapping clock phases control s,s Phase : Sampling phase input is sampled onto capacitor Phase : Integrating phase additional charge is added to previous charge on EE
18 Switched-apacitor Integrator -VO[n] +VO[n] -VO[n]+VI[n] +VO[n]-VI[n] Final charge on L.S. of is +V O [n+] + V [ n+ ] = + V [ n] V[ n] O O I zvo( z ) = VO( z ) VI( z ) VO ( z) = V z EE37 I 7-35 Parasitic Sensitive Parasitic capacitances p, p3 and p4 have no impact on transfer function p in parallel with, changes transfer function V ( + p) O ( z ) = V z I EE
19 Parasitic Insensitive p3 p4 V I p p V O Transfer function is non-inverting, delaying V V O I ( z) = z EE Parasitic Insensitive Parasitics have no impact on transfer function Better linearity since non-linear capacitors are unimportant Top plate on virtual ground node Minimizes parasitics, improves amplifier speed and resolution, reduces noise coupled to node Two extra switches needed More power to drive the switches for the same onresistance EE
20 Delay-Free Integrator Same structure, still parasitic insensitive Transfer function is inverting, delay-free VO z ( z) = V z I EE Bootstrapping At low supply voltages, signal swing is limited Maximum distortion determines the tolerable variation in R ON, and this limits the signal swing Want to increase V GS on the sampling switch an do this by increasing the supply voltage for the sampling switch, but this requires slower thick oxide devices Alternatively, add a constant voltage to the input signal and use that as the gate voltage keep V GS constant, reducing the variation in R ON EE
21 Bootstrapped ircuit Basic operation φ : is charged to V DD and gate of sampling switch is discharged to V SS (turned off) φ : V IN is added to voltage across, sampling switch turns on, gate voltage of the sampling switch is V IN + V DD V SS V DD S S Ideally, there is S 3 S 4 always V GS = V DD for the sampling switch S 5 V IN V OUT V SS EE Bootstrapped ircuit must be sized so that charge sharing between gate capacitance of switch is not significant VG = VIN + VDD + Rise time controlled by size of S 4, fall time controlled by size of S 5 G Extra transistors required to limit gate-source voltages to V DD and prevent overstress See Dessouky, JSS Mar.00 EE37 7-4
22 Switched-apacitor MFB Two parts to the circuit First, sense the common mode of the output Second, compare the common mode to the expected common mode, and adjust the bias accordingly Sensing ould use resistors they are either too small and reduce the gain, or they can get prohibitively large ould use capacitors they don t reduce the gain, but the voltage across them is undefined The voltage across them can be refreshed every clock cycle EE Switched-apacitor MFB One alternative Phase : precharge capacitors to ideal value Phase : sense the difference and adjust the bias accordingly But there may be large changes in the tail current bias EE
23 Switched-apacitor MFB Solution: Part of the tail current source can be controlled by a constant bias voltage Will this work? V B V M V M V IN + V IN - V B P V B EE37 ½ size ½ size 7-45 Switched-apacitor MFB Alternatively, use capacitors so that only a fraction of the charge is shared to adjust the bias voltage Typically, is 4-0 times EE
24 NLOTD: Schmitt Trigger EE What You Learned Today. Errors introduced with simple sampling switch RON variation, charge injection. Main S ircuits S/H, Gain and Integrators Parasitic Insensitive Signal-independent charge injection 3. Bootstrapped ircuit 4. Switched apacitor MFB EE
Lecture 3 Switched-Capacitor Circuits Trevor Caldwell
Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,
More informationChapter 13: Introduction to Switched- Capacitor Circuits
Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor
More informationSwitched Capacitor Concepts & Circuits
Switched apacitor oncepts & ircuits Outline Why Switched apacitor circuits? Historical Perspective Basic Building Blocks Switched apacitors as Resistors Switched apacitor Integrators Discrete time & charge
More informationNOISE IN SC CIRCUITS
ECE37 Advanced Analog Circuits Lecture 0 NOISE IN SC CIRCUITS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen Understanding of CMOS analog circuit
More informationINF4420 Switched capacitor circuits Outline
INF4420 Switched capacitor circuits Spring 2012 1 / 54 Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators 2 / 54 Introduction Discrete time analog
More informationINF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen
INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators
More informationINF4420. Outline. Switched capacitor circuits. Switched capacitor introduction. MOSFET as an analog switch 1 / 26 2 / 26.
INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uil.no) 1 / 26 Outline Switched capacitor introduction MOSFET as an analog switch 2 / 26 Introduction Discrete time
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationOperational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input
More informationSummary Last Lecture
EE247 Lecture 16 D/A onverters (continued) DA reconstruction filter AD onverters Sampling Sampling switch considerations Thermal noise due to switch resistance lock jitter related non-idealities Sampling
More informationEE 508 Lecture 28. Integrator Design. Alaising in SC Circuits Elimination of redundant switches Switched Resistor Integrators
EE 508 Lecture 28 Integrator Design Alaising in S ircuits Elimination of redundant switches Switched Resistor Integrators Review from last time The S integrator 1 1 I 0eq= f LK Observe this circuit has
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationECE626 Project Switched Capacitor Filter Design
ECE626 Project Switched Capacitor Filter Design Hari Prasath Venkatram Contents I Introduction 2 II Choice of Topology 2 III Poles and Zeros 2 III-ABilinear Transform......................................
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF AIFORNIA ollege of Engineering Department of Electrical Engineering and omputer Sciences Homework 6 Solution EES 47 H. Khorramabadi Due Tues. November 3, 00 FA 00. A basic NMOS track and
More informationPreliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
More informationSummary of Last Lecture
EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch
More informationDesign of Pipeline Analog to Digital Converter
Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analog-to-digital converter (ADC) architecture is the most popular topology
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationCommon-Source Amplifiers
Lab 2: Common-Source Amplifiers Introduction The common-source stage is the most basic amplifier stage encountered in CMOS analog circuits. Because of its very high input impedance, moderate-to-high gain,
More informationCHAPTER 5 DESIGN OF TRACK-AND-HOLD AMPLIFIER AND MULITIPLYING DIGITAL TO ANALOG CONVERTER
67 HAPTER 5 DESIGN OF TRAKANDHOLD AMPLIFIER AND MULITIPLYING DIGITAL TO ANALOG ONVERTER 5. INTRODUTION This chapter presents the design of the trackandhold and multiplying digitaltoanalog converter functional
More informationOperational Amplifier as A Black Box
Chapter 8 Operational Amplifier as A Black Box 8. General Considerations 8.2 Op-Amp-Based Circuits 8.3 Nonlinear Functions 8.4 Op-Amp Nonidealities 8.5 Design Examples Chapter Outline CH8 Operational Amplifier
More informationTuesday, March 22nd, 9:15 11:00
Nonlinearity it and mismatch Tuesday, March 22nd, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 22nd of March:
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
More informationECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 11: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Exam 1 is on Wed. Oct 3
More informationA new class AB folded-cascode operational amplifier
A new class AB folded-cascode operational amplifier Mohammad Yavari a) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran a) myavari@aut.ac.ir
More informationDifference between BJTs and FETs. Junction Field Effect Transistors (JFET)
Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More informationIN the design of the fine comparator for a CMOS two-step flash A/D converter, the main design issues are offset cancelation
JOURNAL OF STELLAR EE315 CIRCUITS 1 A 60-MHz 150-µV Fully-Differential Comparator Erik P. Anderson and Jonathan S. Daniels (Invited Paper) Abstract The overall performance of two-step flash A/D converters
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 8: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam 1 is
More informationLow-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationLecture 2: Non-Ideal Amps and Op-Amps
Lecture 2: Non-Ideal Amps and Op-Amps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical Op-Amps Linear Imperfections: Finite open-loop gain (A 0 < ) Finite input resistance
More informationTest Your Understanding
074 Part 2 Analog Electronics EXEISE POBLEM Ex 5.3: For the switched-capacitor circuit in Figure 5.3b), the parameters are: = 30 pf, 2 = 5pF, and F = 2 pf. The clock frequency is 00 khz. Determine the
More informationApplication Note. Switched-Capacitor A/D Converter Input Structures. by Jerome Johnston V I V I + V OS _
查询 an30 供应商 捷多邦, 专业 PB 打样工厂,24 小时加急出货 AN30 Application Note Switched-apacitor A/D onverter Input Structures MOS has become popular as the technology for many modern A/D converters. MOS offers good analog
More informationA Successive Approximation ADC based on a new Segmented DAC
A Successive Approximation ADC based on a new Segmented DAC segmented current-mode DAC successive approximation ADC bi-direction segmented current-mode DAC DAC INL 0.47 LSB DNL 0.154 LSB DAC 3V 8 2MS/s
More informationAmplifiers Frequency Response Examples
ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationDesign of High-Speed Op-Amps for Signal Processing
Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS
More informationOutline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45
INF440 Noise and Distortion Jørgen Andreas Michaelsen Spring 013 1 / 45 Outline Noise basics Component and system noise Distortion Spring 013 Noise and distortion / 45 Introduction We have already considered
More informationHomework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26
Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics:
More informationChapter 9: Operational Amplifiers
Chapter 9: Operational Amplifiers The Operational Amplifier (or op-amp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,
More informationCommon Gate Stage Cascode Stage. Claudio Talarico, Gonzaga University
Common Gate Stage Cascode Stage Claudio Talarico, Gonzaga University Common Gate Stage The overdrive due to V B must be consistent with the current pulled by the DC source I B careful with signs: v gs
More informationVoltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University
Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University Voltage Biasing Considerations In addition to bias currents, building a complete
More informationIntegrated Circuit Amplifiers. Comparison of MOSFETs and BJTs
Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )
More informationCHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE
CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined
More informationSummary of Last Lecture
EE247 Lecture 2 ADC Converters (continued) Successive approximation ADCs (continued) Flash ADC Flash ADC sources of error Sparkle code Meta-stability Comparator design EECS 247 Lecture 2: Data Converters
More informationExperiment 1: Amplifier Characterization Spring 2019
Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using
More informationQ1. Explain the Astable Operation of multivibrator using 555 Timer IC.
Q1. Explain the Astable Operation of multivibrator using 555 Timer I. Answer: The following figure shows the 555 Timer connected for astable operation. A V PIN 8 PIN 7 B 5K PIN6 - S Q 5K PIN2 - Q PIN3
More informationECE315 / ECE515 Lecture 7 Date:
Lecture 7 ate: 01.09.2016 CG Amplifier Examples Biasing in MOS Amplifier Circuits Common Gate (CG) Amplifier CG Amplifier- nput is applied at the Source and the output is sensed at the rain. The Gate terminal
More informationEE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1
EE47 Lecture 6 D/A Converters (continued) Self calibration techniques Current copiers (last lecture) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations
More information6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers
6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott High
More informationECE4902 B2015 HW Set 1
ECE4902 B2015 HW Set 1 Due in class Tuesday November 3. To make life easier on the graders: Be sure your NAME and ECE MAILBOX NUMBER are prominently displayed on the upper right of what you hand in. When
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationEE247 Lecture 6. Frequency tuning for continuous-time filters
EE247 Lecture 6 Summary last lecture ontinuoustime filters Opamp MOSFET filters Opamp MOSFETR filters filters Frequency tuning for continuoustime filters Trimming via fuses Automatic onchip filter tuning
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationA Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS
A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology
More informationDesign Switched Capacitor Filter Sub Circuit Using Tanner EDA Tool
Advance in Electronic and Electric Engineering ISSN 2231-1297, Volume 3, Number 3 (2013), pp. 271-178 Research India Publications http://www.ripublication.com/aeee.htm Design Switched Capacitor Filter
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationA 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC
A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC M. Åberg 2, A. Rantala 2, V. Hakkarainen 1, M. Aho 1, J. Riikonen 1, D. Gomes Martin 2, K. Halonen 1 1 Electronic Circuit Design Laboratory Helsinki University
More informationChapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,
More informationField Effect Transistors
Field Effect Transistors LECTURE NO. - 41 Field Effect Transistors www.mycsvtunotes.in JFET MOSFET CMOS Field Effect transistors - FETs First, why are we using still another transistor? BJTs had a small
More informationEE247 Lecture 17. EECS 247 Lecture 17: Data Converters 2006 H.K. Page 1. Summary of Last Lecture
EE47 Lecture 7 DAC Converters (continued) DAC dynamic non-idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter ADC Converters
More informationC H A P T E R 5. Amplifier Design
C H A P T E 5 Amplifier Design The Common-Source Amplifier v 0 = r ( g mvgs )( D 0 ) A v0 = g m r ( D 0 ) Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.
More informationAnalog Integrated Circuit Design Exercise 1
Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture
More informationChapter 4: Differential Amplifiers
Chapter 4: Differential Amplifiers 4.1 Single-Ended and Differential Operation 4.2 Basic Differential Pair 4.3 Common-Mode Response 4.4 Differential Pair with MOS Loads 4.5 Gilbert Cell Single-Ended and
More informationDESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationSelf-Biased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas
Self-Biased PLL/DLL ECG721 60-minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation Self-Biasing Technique Differential Buffer
More informationd. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
More informationApplied Electronics II
Applied Electronics II Chapter 3: Operational Amplifier Part 1- Op Amp Basics School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Getachew
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationECE315 / ECE515 Lecture 9 Date:
Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three
More informationA Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP
10.4 A Novel Continuous-Time Common-Mode Feedback for Low-oltage Switched-OPAMP M. Ali-Bakhshian Electrical Engineering Dept. Sharif University of Tech. Azadi Ave., Tehran, IRAN alibakhshian@ee.sharif.edu
More informationSummary Last Lecture
EE247 Lecture 6 Summary last lecture ontinuoustime filters Opamp MOSFET filters Opamp MOSFETR filters filters Frequency tuning for continuoustime filters Trimming via fuses Automatic onchip filter tuning
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor
More informationDesign and Simulation of Low Voltage Operational Amplifier
Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor
More informationTopology Selection: Input
Project #2: Design of an Operational Amplifier By: Adrian Ildefonso Nedeljko Karaulac I have neither given nor received any unauthorized assistance on this project. Process: Baker s 50nm CAD Tool: Cadence
More informationA Compact Folded-cascode Operational Amplifier with Class-AB Output Stage
A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationLesson number one. Operational Amplifier Basics
What About Lesson number one Operational Amplifier Basics As well as resistors and capacitors, Operational Amplifiers, or Op-amps as they are more commonly called, are one of the basic building blocks
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationAnalog I/O. ECE 153B Sensor & Peripheral Interface Design Winter 2016
Analog I/O ECE 153B Sensor & Peripheral Interface Design Introduction Anytime we need to monitor or control analog signals with a digital system, we require analogto-digital (ADC) and digital-to-analog
More informationMicroelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
More informationElectronic Circuits for Mechatronics ELCT 609 Lecture 7: MOS-FET Amplifiers
Electronic Circuits for Mechatronics ELCT 609 Lecture 7: MOS-FET Amplifiers Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Enhancement N-MOS Modes of Operation Mode V GS I DS V DS Cutoff
More informationDifferential Amplifiers
Differential Amplifiers Benefits of Differential Signal Processing The Benefits Become Apparent when Trying to get the Most Speed and/or Resolution out of a Design Avoid Grounding/Return Noise Problems
More informationOp Amp Technology Overview. Developed by Art Kay, Thomas Kuehl, and Tim Green Presented by Ian Williams Precision Analog Op Amps
Op Amp Technology Overview Developed by Art Kay, Thomas Kuehl, and Tim Green Presented by Ian Williams Precision Analog Op Amps 1 Bipolar vs. CMOS / JFET Transistor technologies Bipolar, CMOS and JFET
More information6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication
More informationMOS TRANSISTOR THEORY
MOS TRANSISTOR THEORY Introduction A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the
More informationECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers
ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background
More informationMicroelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
More informationMOS IC Amplifiers. Token Ring LAN JSSC 12/89
MO IC Amplifiers MOFETs are inferior to BJTs for analog design in terms of quality per silicon area But MO is the technology of choice for digital applications Therefore, most analog portions of mixed-signal
More informationEE5310/EE3002: Analog Circuits. on 18th Sep. 2014
EE5310/EE3002: Analog Circuits EC201-ANALOG CIRCUITS Tutorial 3 : PROBLEM SET 3 Due shanthi@ee.iitm.ac.in on 18th Sep. 2014 Problem 1 The MOSFET in Fig. 1 has V T = 0.7 V, and μ n C ox = 500 μa/v 2. The
More informationHW#3 Solution. Dr. Parker. Spring 2014
HW#3 olution r. Parker pring 2014 Assume for the problems below that V dd = 1.8 V, V tp0 is -.7 V. and V tn0 is.7 V. V tpbodyeffect is -.9 V. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V
More informationCurrent Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1
Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol
More informationA Low Power Small Area Multi-bit Quantizer with A Capacitor String in Sigma-Delta Modulator
A Low Power Small Area Multi-bit uantizer with A Capacitor String in Sigma-Delta Modulator Xuia Wang, Jian Xu, and Xiaobo Wu Abstract An ultra-low power area-efficient fully differential multi-bit quantizer
More information4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter
4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter Jinrong Wang B.Sc. Ningbo University Supervisor: dr.ir. Wouter A. Serdijn Submitted to The Faculty of Electrical Engineering, Mathematics
More informationLecture 20 Transistor Amplifiers (II) Other Amplifier Stages. November 17, 2005
6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 20 1 Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages November 17, 2005 Contents: 1. Common source amplifier (cont.) 2. Common drain
More informationOperational Amplifier with Two-Stage Gain-Boost
Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization, Lisbon, Portugal, September 22-24, 2006 482 Operational Amplifier with Two-Stage Gain-Boost FRANZ SCHLÖGL
More information