A 285-fs rms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 216 ISSN(Print) ISSN(Online) A 285-fs rms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique Sungwoo Kim, Sungchun Jang, Sung-Yong Cho, Min-Seong Choo, Gyu-Seob Jeong, Woorham Bae, and Deog-Kyoon Jeong Abstract An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fs rms integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mw. The figure-of-merit of the ILRPLL is db. Index Terms Charge-stored complementary switch (CSCS), frequency synthesizer, injection-locked oscillator (ILO), phase-locked loop (PLL) I. INTRODUCTION In high-performance clock synthesizers, an injectionlocked oscillator (ILO) has become an attractive solution because of its superior jitter performance compared to conventional integer-n phase-locked loops. However, the ILO commonly suffers from two issues [1]. First, the phase noise and the spur level performance degrades as Manuscript received Jun. 8, 216; accepted Sep. 26, 216 Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University, Gwanak-ro, Gwanak-gu, Seoul, Korea ( ) dkjeong@snu.ac.kr the frequency mismatch f ERR between the free-running f OUT and the injection frequency f REF increases. Second, the injection lock range f LR becomes narrow for a large multiplication factor N. In other words, achieving low jitter becomes more challenging as N increases. To detect this frequency mismatch, a fine resolution time-to-digital converter (TDC) is employed in [2] at the cost of increased power consumption. In addition, using a phase detector (PD) with a replica delay cell, as proposed in [3], suffers from the problem of device mismatches. Moreover, the absence of startup circuits in [2] and [3] requires the oscillation frequency to be set within the injection lock range initially. [1] and [3] achieve an excellent figure-of-merits (FoMs) of less than 24 db with a small N since achieving the high performance in ILOs is challenging with a higher N [4]. However, reducing N is not adequate for practical designs using crystal oscillators whose operating frequency is often limited only up to 2 MHz. In this paper, an injection-locked ring phase-locked loop (ILRPLL) with N = 64 is presented. The ILRPLL employs a PLL to initialize the oscillation frequency and a frequency calibration loop (FCL) for nullifying frequency mismatch. Additionally, a device mismatch calibration loop (MCL) runs in the background. A charge-stored complementary switch (CSCS) injection technique is proposed as well to achieve a wide lock range even for a large N. The remaining parts of this paper is organized as follows. Section II describes the proposed ILRPLL architecture. After the experimental results are presented

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, Normal-operation state FCL/MCL REF DCC, PFD PWC DLF Acc. ΔΣ ER F 1 PLL_DONE 1 UP/DN ER M CNT[2] Acc. ΔΣ RST_PLSB CLK_PLSB EN_PLS ON_PLS FCW MCW CNT ILRO CNT[1:] DIV4 RST RSTCNT CNT DIV4 RSTB FCW: Frequency Control Word MCW: Mismatch Control Word Fig. 1. Block diagram of the proposed ILRPLL. DIV64 Initial state PLL in Section III, Section IV concludes the work. FCW II. ARCHITECTURE OUT The block diagram of the proposed ILRPLL is illustrated in Fig. 1. It is composed of a phase frequency detector (PFD), a digital loop filter (DLF), an injectionlocked ring oscillator (ILRO), the FCL, the MCL, and a duty-cycle corrector (DCC). The ILRO consists of a pseudo-differential two-stage ring-type digitally controlled oscillator (DCO) using the merged injection technique, as shown in Fig. 2. In addition, the DCC maintains the 5% duty cycle for achieving equally spaced injection at rising and falling edges. Fig. 3 shows the operational sequence of the ILRPLL. At startup, it cannot be assured that f OUT is within f LR due to relatively narrow f LR compared to the frequency range of the ILRO under process, supply voltage and temperature (PVT) variations. To ensure the injection locking operation, in the initial state, the PLL operates with the injection, which locks the ILRO. However, with the PLL locked, PLL_DONE = 1, f OUT is prone to stay away from the targeted N f REF, because the PLL cannot detect the frequency error f ERR with the ILRO locked [5]. When PLL_DONE =1, the MCL runs before the FCL operates so that the device mismatches are minimized. The device mismatches include the two path mismatches to the pulse width comparator (PWC), the capacitance/ current mismatches in the PWC. Finally, when the MCW settles at some value to minimize the device mismatches, the FCL operates to remove f ERR over the PVT variations. CSCS B Fig. 2. Schematic of ILRO. f OUT MCW PLL ON MCL OFF FCL OFF Startup Initial state OFF ON 1. Charge-stored Complementary Switch Injection Technique Dummy OUTB ON Unit cell N f REF The lock range analysis proposed in [6] with a phase domain response (PDR) is valid for both weak and strong injections. If f ERR is nonzero, the injection signal causes an output phase shift. The lock range is determined by f LR Time Time Normal-operation state Fig. 3. ILRPLL operation sequence. Minimized mismatch

3 862 SUNGWOO KIM et al : A 285-FS RMS INTEGRATED JITTER INJECTION-LOCKED RING PLL WITH CHARGE-STORED B the range of possible phase shifts: the maximum phase shift, P max, and the minimum phase shift P min, while the ILO maintains in a lock state. Thus, it can be expressed as f N1 Fig. 4. Schematic of CSCS. I C,DC C CS ( - ) f P P f P max min pp LR = =, (1) 2p N 2p N where P pp is the peak-to-peak phase shift of the PDR. Therefore, the lock range can be maximized by increasing P pp and decreasing N. If the reference signals are injected at both rising and falling edges, it brings an effect of halving the N. A single switch injection technique shorting the differential clock signals is generally employed. Nonetheless, the design of the pulse generator (PG) N2 producing the suitable injection pulse is challenging [2]. As an alternative to the use of the PG, a complementary switch (CS) injection technique can be employed [7]. However, it is difficult to obtain a large P pp because the injection current flows only during a short transition time. In order to increase the injection current, the chargestored complementary switch (CSCS) injection technique is proposed as described in Fig. 4. The charge-storing capacitor C CS is placed between the center nodes of the two switches to hold an additional charge. Fig. 5(a) shows the operation of the CSCS at the transition moment. When N1 is connected to B, the charge Q stored in C CS is discharged to B, which makes B to go the level of. Consequently, it results in pushing the output phase, as shown in Fig. 5(b). In order to verify the CSCS, the PDR is determined through simulation as shown in Fig. 6(a). As shown in Fig. 6(b), f LR of the CSCS method is proportional to C CS and it shows about the lock range of MHz at C CS = 3 ff, which is 3 times wider than that of the CS method. In addition, the measured lock range of prototype chip is MHz. As a compromise, the optimum value for C CS is set to 3 ff to obtain the targeted phase noise performance with a minimum power overhead. Therefore, with the aid of the CSCS injection technique, an enhanced : '1' : '1' Q Q N1 N2 N1 N2 C CS C CS B: '' B N1 N2 (a) B: '' I C,DC f ERR = f ERR <, pulling phase f ERR >, pushing phase Fig. 5. CSCS injection technique (a) operation, (b) timing diagram. (b)

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, Phase shift [ ] No C CS 1 ff 3 ff 5 ff P pp Lock range [MHz] Measured lock range Input phase [ ] C CS [ff] 6 (a) (b) Fig. 6. (a) PDR, (b) calculated lock range. REF RSTB RSTCNT DIV4 Half Period CNT[2:] EN_PLS ON_PLS CLK_PLSB RST_PLSB Pulling phase V EN V ON UP/DN Frequency Error UP (ER F) Mismatch Error UP (ER M) Fig. 7. Timing diagram of FCL and MCL. lock range can be achieved. 2. Frequency/Mismatch Calibration Loop The key concept of detecting f ERR in [2] is based on the phenomenon that the pulse-width difference is proportional to f ERR when the reference clock is injected into the oscillator. By comparing the two pulse widths, f ERR can be detected and compensated. Our approach is to simply detect the polarity of f ERR using a PD, as in [3] and [8], which eliminates the use of a power-hungry TDC. However, the PD alone cannot compare two successive pulses simultaneously and it suffers from the offset issues. As a remedy, the PWC converts the pulse width into voltage and detects the polarity of f ERR [8]. The illustrative timing diagram of the FCL and the MCL operation and the detailed implementation of the PWC are shown in Fig. 7 and 8, respectively. The PWC generates the up/down signal UP/DN by comparing EN_PLS and ON_PLS, which are generated from the divided-by-4 clock DIV4. The dividing factor of 4 is chosen to allow a sufficient time-to-voltage conversion gain and a low power operation. The counter (CNT) identifies the pulse width and RSTCNT that are generated from the external reset RSTB, and resets CNT to before the rising edge of. The pulse width of EN_PLS in CNT = is proportional to f ERR and the width of ON_PLS in CNT = 1 represents the oscillator s free-running frequency. Detecting f ERR is performed every half period of REF. Injecting at both rising and falling edges has the effect of halving N. It is important to note that nonzero value of f ERR makes the EN_PLS in CNT = deviate from the ON_PLS in CNT = 1, and consequently, the PWC generates a polarity of difference. After the PWC makes the decision at rising edge of CLK_PLSB, the V EN and V ON are reset at rising edge of RST_PLSB. Then, 1-bit information of the f ERR is delivered to the DLF.

5 864 SUNGWOO KIM et al : A 285-FSRMS INTEGRATED JITTER INJECTION-LOCKED RING PLL WITH CHARGE-STORED MCW EN_PLS ON_PLS VEN UP/DN RST_PLSB VON CLK_PLSB Fig. 8. Schematic of PWC. Block Power [mw] ILRO 4.86 DLF.68 31um I2C&DLF 21um 8um ILRO PWC 14um 11um 14um Fig. 1. Measured phase noise. DCC PWC,DCC, DIV, PFD Total 4.34dBc Fig. 9. Chip photomicrograph and power breakdown. Furthermore, both the pulse widths of EN_PLS in CNT = 4 and ON_PLS in CNT = 5 refers to the oscillator s free-running frequency. Comparing the two same pulse width, the device mismatches are detected. The mismatches include the mismatches of capacitance and the charge pump in the PWC. In the remaining half period, the PWC decides the polarity of the mismatches and calibrates the mismatches. Therefore, the implemented FCL and MCL can track and compensate for frequency deviation over PVT variations. III. EXPERIMENTAL RESULTS The ILRPLL is fabricated in a 65-nm CMOS technology. The active die area of the ILRPLL chip is.64 mm2. The chip photomicrograph and the power breakdown are shown in Fig. 9. The ILRPLL operates at GHz and consumes 7.16 mw from a 1.2-V supply with a 52-MHz reference clock. The measured phase noise at this frequency with N = 64 is shown in Fig. 1. The phase noise of the free running DCO without the injection is measured with a dbc/hz at the 1-MHz offset frequency. With the reference clock injection enabled and the PLL locked, the integrated jitter from 1 khz 4 MHz is 555 fsrms, which Fig. 11. Measured spectrum in initial state. is in the initial state. Without the FCL and the MCL, ferr is not zero and unpredictable due to the PLL operation with the ILOs, resulting in poor jitter performance. In the normal-operation state, the PLL is turned off and the calibration loops start to operate. The measured phase noise is dbc/hz at the 1-MHz offset frequency and the measured jitter is 285 fsrms, which means that the implemented calibration loops are working for the minimization of ferr. As shown in Fig. 11 and 12, the reference spur level measurements are 4.3 dbc and 5.2 dbc for the initial state and the normal-operation state, respectively. Even with a slight degradation in jitter performance, the spur level increases seriously. Because of this reason, the calibration loops are essential to achieve the high performance. The performance of the implemented ILRPLL is summarized and compared with the state-of-the-art ILOs in Table 1. Compared to the ring-type architectures in [1] and [7], it is noticeable that the proposed ILRPLL exhibits a better FoM, even with a large multiplication ratio.

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, Table 1. Performance summary This work [1] [3] [7] Technology [nm] Output Freq. [GHz] Multiplication ratio RMS jitter [fs] 285 (1k-4 MHz) 7 (1k-4 MHz) 185 (1k-4 MHz) 484 (1k-4 MHz) Power [mw] FoM [db] FoM = 1log[(σ rms/1s)2 (P/1 mw)] V. CONCLUSIONS A low-jitter ILRPLL with the multiplication ratio of 64 fabricated in 65-nm CMOS technology is proposed. The prototype chip operates at GHz while consuming 7.16 mw, and it achieves the FoM of db. This work has two main contributions to the ILRPLL design. First, it proposes a novel injection technique to enhance the injection strength with doubled reference frequency injection and charge storing capacitor. Second, the implemented calibration loops successfully address the performance degradation issue of the ILOs achieving an outstanding performance. ACKNOWLEDGMENTS This paper was result of the research project supported by SK hynix Inc. and Inter-university Semiconductor Research Center (ISRC) of Seoul National University. REFERENCES 5.21dBc Fig. 12. Measured spectrum in normal-operation state. [1] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, A compact, lowpower and low-jitter dual-loop injection locked PLL using all-digital PVT calibration, IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 5 6, Jan [2] B. M. Helal, C.-M. Hsu, K. Johnson, and M. H. Perrott, A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop, IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp , May 29. [3] S. Choi, S. Yoo, and J. Choi, A 185-fsrmsintegrated-jitter and 245dB FOM PVT-robust ring-vco-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector, in 216 IEEE International Solid-State Circuits Conference (ISSCC), 216, pp [4] J. Lee and H. Wang, Study of subharmonically injection-locked PLLs, IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp , May 29. [5] A. Elkholy, M. Talegaonkar, T. Anand, and P. Kumar Hanumolu, Design and analysis of lowpower high-frequency robust sub-harmonic injection-locked clock multipliers, IEEE Journal of Solid-State Circuits, vol. 5, no. 12, pp , Dec [6] D. Dunwell and A. C. Carusone, Modeling oscillator injection locking using the phase domain response, IEEE Trans. Circuits Syst. I, vol. 6, no. 11, pp , Nov [7] S.-Y. Cho, S. Kim, M.-S. Choo, J. Lee, H.-G. Ko, S. Jang, S.-H. Chu, W. Bae, Y. Kim, and D.-K. Jeong, A 5-GHz subharmonically injection-locked alldigital PLL with complementary switched injection, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC st, 215, pp

7 866 [8] SUNGWOO KIM et al : A 285-FSRMS INTEGRATED JITTER INJECTION-LOCKED RING PLL WITH CHARGE-STORED H. Kim, Y. Kim, T. Kim, H. Park, and S. Cho, A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS, in 216 IEEE International Solid-State Circuits Conference (ISSCC), 216, pp Sungwoo Kim received the B.S. degree in electronic engineering from the Kyungpook National University, Daegu, Korea, in 29, and the M.S. degrees from the Seoul National University, Seoul, Korea, in 211, where he is currently working toward the Ph.D. degree. His research interests include phaselocked loop and injection-locked oscillator for highspeed communication. Sungchun Jang received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 28, 21 and 215, respectively. He joined SK hynix, Icheon, Korea, in 216. His research interests include high-speed I/O circuits and alldigital PLL/DLL design. Sung-Yong Cho received the B.S degree in electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 212. He is currently working toward the Ph.D. degree in electrical engineering at Seoul National University, Seoul. His research is focused on high-speed I/O circuits and architectures. Min-Seong Choo received the B.S. degree in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 212. He is currently working toward the Ph.D. degree in the same university. His research interests include high-speed I/O circuits using injection locking techniques. Gyu-Seob Jeong received the B.S. degree in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 212. He is currently working toward the Ph.D. degree in the same university. His research interests include silicon photonics, high-speed I/O circuits. Woorham Bae received the B.S. and Ph.D. degrees in electrical and computer engineering from Seoul National University, Seoul, Korea, in 21 and 216, respectively. He is currently a Postdoctoral Researcher at the Inter-University Semiconductor Research Center, Seoul National University. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, and non-volatile memory systems. Dr. Bae received the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 216, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 216, the IEEE Solid-State Circuits Society STG Award at the Asian Solid-State Circuits Conference in 215, and the Best Poster Award at the IC Design Education Center Chip Design Contest, International SoC Design Conference, in 214. Deog-Kyoon Jeong received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1981 and 1984, respectively, and the Ph.D. degree in electrical where he was a Member of Technical Staff and worked on engineering and computer sciences from the University of California, Berkeley, in From 1989 to 1991, he was with Texas Instruments, Dallas, TX, the modeling and design of BiCMOS gates and the singlechip implementation of the SPARC architecture. He joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, as an Assistant Professor in He is currently a Professor in the School of Electrical Engineering, Seoul National University. His main research interests include highspeed I/O circuits, VLSI systems design, microprocessor architectures, and memory systems.