All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) ISSN(Online) All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0 Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park Abstract A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an allsynthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5- phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies mm 2, consumes 4.8 mw at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively. Index Terms Multi-phase, ring oscillator, digitally controlled oscillator (), phase-locked loop I. INTRODUCTION Phase-locked loops (PLL) are widely used to increase the data rate in chip-to-chip communication. The PLL frequency is being increased as the data rate is increased, but the increase a PLL s frequency; cause almost proportional increase in its power. Also the maximum frequency of PLL is limited by the process technology. To increase the data rate at the transmitter or the sampling rate at the receiver without increasing the PLL frequency, multiphase PLLs are used. In a PLL with a 5- stage ring oscillator-based voltage controlled oscillator (VCO), 5-phase clocks are generated by taking the output signals of 5 inverters of the ring oscillator. To achieve high data rate, uniform phase spacing must be maintained Manuscript received Nov. 30, 2015; accepted Feb. 11, 2016 Department of Electronic and Electrical Engineering from POSTECH, Korea hjpark@postech.ac.kr among multiphase output clocks [1]. Initially, analog charge-pump PLLs [2] were used for chip-to-chip communication because of the zero phase offset between the input and output clocks. However, as with process technology is scaled down, charge-pump PLLs have the disadvantages of large area and gate leakage current of the loop filter capacitor [3]. A type-i PLL can be used to reduce the area of the loop filter capacitor [4]. Digital PLLs can solve these two problems by eliminating the loop filter capacitor. Meanwhile, PLLs are used as a components in large digital chips such as central processing units and digital signal processors; the digital chip is mostly implemented by using logic synthesis to enhance the portability between different process technologies. All-synthesizable PLLs are developed to follow this trend [5-8]. However, all these PLLs generate a single output clock. In this work, a 5- phase all-synthesizable PLL is proposed for use with a 5x blind-oversampling clock-data-recovery circuit of a USB2.0 receiver. To maintain a constant phase spacing between adjacent 5-phase clocks, careful constraints are applied to the positions of elements that comprise the ring oscillator-based digitally controlled oscillator () during the placement and routing procedure. Section II explains the architecture of the proposed allsynthesizable 5-phase PLL. Section III shows the details of the placement and routing procedure. Section IV shows the measurement results. Section V concludes this work. II. PROPOSED ARCHITECTURE The proposed all-synthesizable 5-phase PLL is implemented by adding a coarse phase detector_2

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, REF_CLK FDR DIV16 Σ Frequency Detector(FD) _CLK[4] фtarget 11 Coarse Phase Dector_1 (CPD1) Coarse Phase Detector_2 (CPD2) Fine Phase Detector (FPD) DIV_CLK фerror фpd CNT RST FSM Digital Loop Filter(DLF) фcpd1 11 фcpd2 5 фfpd 6 LUT1 LUT2 β α Z -1 CPD2_OUT[4:0] FD_OUT[2:0] DLF_OUT[13:0] SAMPLER SAMPLER <4:0> (CPD2) to a conventional counter-based digital PLL (Fig. 1). The PLL is based on a conventional counter-based digital PLL. The PLL consists of frequency detector (FD), digital loop filter (DLF), coarse phase detector_1 (CPD1), coarse phase detector_2 (CPD2), fine phase detector (FPD), and digital controlled oscillator (). The three phase detectors are enabled simultaneously in this work. The CPD1 adjusts the time difference between the rising edge time of one of the 5-phase PLL output clocks to that of the input reference clock (REF_CLK) within one period of the PLL output clocks. The CPD2 adjusts the time difference to within one-fifth period of the PLL output clocks by using the 5-phase clocks. The FPD adjusts the time difference to within 60 ps. It was implemented by an 8-stage conventional TDC. The length of TDC is halved by the operation of the CPD2. The proposed PLL accepts a 20 MHz input clock (REF_CLK) and frequency divider ratio (FDR) of 24 as input and generates 5-phase 480 MHz output clocks (_CLK[4:0]); the rising edges of _CLK[4] and REF_CLK are aligned. The addition of the CPD2 reduces the chip area of the FPD by half. The FPD is implemented with a time-to-digital converter (TDC) that takes a significant chip area because the delay range of TDC must cover a half period of the output clock (_CLK). Initially after the power-on reset, the _CLK frequency is set to the minimum frequency and a finite-state machine (FSM) output (FD_OUT[2:0]) is reset to 0 (Fig. 1). TDC 6 8 B2T C[6:0] F[62:0] Fig. 1. Proposed all-synthesizable 5-phase PLL. F[63] Σ _CLK[4] _CLK[4:0] _CLK[4] _CLK[4:0] A frequency detector (FD) counts the number of periods of _CLK[4] during 8 periods of REF_CLK and increases the FSM output by 1 if the counter output value is smaller than 192, which corresponds to 8 times the FDR value (24). The FD declares frequency lock and holds the FSM output if the counter output value reaches 193. Then, the relative frequency offset of _CLK from the target frequency (24 times the REF_CLK frequency) is smaller than 1/192 (5209 ppm). After the frequency lock is declared, the two coarse PDs (CPD1, CPD2) and the fine PD (FPD) are enabled. These three PDs, a digital loop filter (DLF) and a part of the block form a phase loop (Fig. 1). The DLF consists of a proportional path and an integral path. The input control code consists of an MSB part FD_OUT[2:0] and an LSB part DLF_OUT[13:0]. The MSB part is converted into a 7-bit MSB thermometer code C[6:0] and the LSB part is converted into a 64-bit LSB thermometer code F[63:0]; the gain for one-bit MSB thermometer code is 40 times the gain for one-bit LSB thermometer code. The phase loop (CPD1, CPD2, FPD, DLF, and part of the block) works during the entire PLL operation to adjust f PD toward f target (Fig. 1) which is proportional to the phase of REF_CLK: f target = mod (FDR x f REF_CLK x t, 2 11 ), (1) where f REF_CLK is the frequency of REF_CLK and t is time. The f PD is the sum of f CPD1, f CPD2 and f FPD (the outputs of CPD1, CPD2 and FPD). f CPD1 corresponds to the phase of _CLK[4]: f CPD1 = mod (f _CLK x t, 2 11 ), (2) where f _CLK is the frequency of _CLK[4]. Similarly, f CPD2 and f FPD can be represented by f CPD2 = mod (f _CLK x t, 1 ) (3) f FPD = mod (f _CLK x t, 2/9) (4) Although f _CLK is close to FDR * f _CLK after the frequency lock is declared, a large time difference ΔT can occur between the waveforms of f target and f _CLK[4] at the start of phase loop operation (Fig. 2). ΔT can take any value between 0 and 2 11 T _CLK,

3 354 KIHWAN SEONG et al : ALL-SYNTHESIZABLE 5-PHASE PHASE-LOCKED LOOP FOR USB ΔT target PD _CLK[4] E CLK _CLK[3] _CLK[2] _CLK[1] _CLK[0] 0 error REF_CLK Time Fig. 2. Operation of coarse phase detector_1 (CPD1). CPD2_OUT[4:0] (a) where T _CLK is one period of _CLK[4]. f CPD1 ranges from 0 to with a resolution of 1; f CPD2 ranges from 0 to 0.8 with a resolution of 0.2, and f FPD ranges from 0 to 7/36 with a resolution of 1/36. The phase loop reduces the difference between f target and f PD by making ΔT smaller than T _CLK /36. Phase error f error is constant with time if f _CLK = FDR * f _CLK (Fig. 2). CPD2 identifies the phase error f CPD2 between _CLK[4] and REF_CLK with a resolution of 0.2 T _CLK by using the 5-phase output clocks [9]. This is performed by converting the sampled output CPD2_OUT[4:0] to a 5-bit code (Fig. 3). The was implemented with a 5-stage ring oscillator that consist of three parallel branches: a freerun path, a coarse path and a fine path (Fig. 4); each stage consists of tri-state inverter cells connected in parallel. Because the is required to generate 5- phase 480 MHz clock signals under all process corners, the numbers of parallel tri-state inverters for the free-run, coarse and fine paths are set to 32 x 10 x 7, 32 x 7 and 32 x 2, respectively. The oscillation frequency of an N-stage ring oscillator that consists of tri-state inverter cells can be derived as f OSC p = 2 k N stage CGS + C CL f f where f TN = 100 GHz and f TP = 40 GHz are, respectively the f T values of the nmosfet and the pmosfet of the tri-state inverter cell, k 0.7, C GS and C GD are the total TN GD TP (5) (b) Fig. 3. Operation of coarse phase detector_2 (CPD2) (a) timing diagram of CDP2, (b) look-up table1 (LUT1). RESET RESETB CB[6:0] C[6:0] FB[63:0] F[63:0] D D D D D C C C C C F F F F F _CLK[4] _CLK[1] _CLK[3] _CLK[0] _CLK[2] Fig. 4. Block diagram of digital controlled oscillator. FREE RUN COARSE FINE gate capacitance including all the parallel tri-state inverters connected at a stage output of a ring oscillator, C L is the load capacitance of a stage output. C L includes the interconnect capacitance as well as drain and source junction capacitance. In this work, (C GD + C GS )/ C L

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, after the placement and routing. According to the linearity simulation of the output frequency w.r.t the control code, the maximum {INL, DNL} values of the coarse and fine paths are {-0.11, 0.05} and {-1.3, 0.35} LSBs, respectively. The loop filter parameters (α, β) determine the bandwidth and damping factor of PLL [9]; α is fixed at 2.0 and β is set to 2-5 or 2-6 in this work. The PLL bandwidth and the damping factor are 125 KHz and 0.5 with β = 2-6 and they are 250 KHz and 0.35 with β = 2-5. The FPD uses 8 flip-flops to form a conventional TDC with a detection range of 2/9 T _CLK ; the 8-bit TDC output is converted into an 8-bit code (f FPD ) for the resolution of T _CLK /36 with the MSB 2-bits of f FPD filled with 0 s. Table 1. Timing difference [ps] between rising edges of adjacent-phase clocks (a) without, (b) with constraints f4-3 f3-2 f2-1 f1-0 f 0-4 (a) III. PLACEMENT AND ROUTING To maintain a constant time difference between the rising edges of two adjacent-phase clocks, the same interconnect loading must be maintained for all five inverters that comprise the 5-stage ring oscillator (Fig. 5). To minimize the interconnect loading of each inverter of the ring oscillator, the layout of unit inverter (Fig. 5) is directly connected in tandem with each other on a straight line. The size of the unit inverter layout is 24 mm x 50 mm excluding the 10 mm-wide power ring. Two constraints (Fig. 5) are applied during the placement and routing stage. Fig. 5 limits the horizontal and vertical dimensions of the ring oscillator to 160 mm and 70 mm, respectively, including the power rail. Fig. 5 defines the locations at which each inverter output is connected to a buffer circuit. To maintain the same loading at each inverter output node, the metal 6 (M6) layout of the output node of each inverter was extended to all five inverters of ring oscillator, then connected to the metal 3 (M3) output node of the corresponding inverter through vias. This process was performed after the placement and routing. The post-layout simulation shows that the two placement and routing constraints (Fig. 5) reduce the maximum time difference between rising edges of adjacent-phase clocks from 22 ps to 1 ps at the output clock frequency of 480 MHz (Table 1); this result verifies that the two constraints guarantee the same interconnect loading of each inverter in Fig. 5. (b) Fig. 5. Layout synthesis techniques (a) circuit schematics, (b) layout of unit inverter stage, (c) constraints on core width and height, (d) allocation of cell locations. IV. MEASUREMENT RESULTS The proposed all synthesized 5-phase phase locked loop was designed and fabricated in a 65-nm CMOS process. The PLL chip core consumes 4.8 mw at a supply voltage of 1.2 V. The measured 5-phase output clocks showed average maximum f error < 1% (4 ps) at 480 MHz (Fig. 6); this is in fair agreement with the Monte-Carlo simulation results of the -0.99% f error +1.02%. The peak-to-peak and rms jitter were 45 ps and 8.6 ps, respectively (Fig. 7). The measured in-band phase noise is -95 dbc/hz and -99 dbc/hz for PLL bandwidths of 125 KHz and 250 KHz, respectively (Fig. 7). The active chip area is mm 2 (Fig. 8). This work with (d)

5 356 KIHWAN SEONG et al : ALL-SYNTHESIZABLE 5-PHASE PHASE-LOCKED LOOP FOR USB2.0 Table 2. Performance summary and comparison 416ps 416ps 416ps 413ps 419ps 400ps 500mV Fig. 6. Measured 5-phase output clocks for 480 MHz. FOM = Power [ mw ] JitterRMS Area[ mm 2 ] all-synthesizable PLLs with single-phase output demonstrates lower jitter and smaller size except [6], which uses injection locking. V. CONCLUSION (a) A 5-phase PLL was implemented for the first time by using the all-synthesis technique. To match the loading of each inverter output of the 5-stage ring oscillator, the unit inverter cells are located in contact with each other on a straight line with the same output loading. This configuration was achieved by applying tight constraints during the placement and routing procedure. The PLL chip implemented in a 65-nm CMOS process occupies mm2, consumes 4.8 mw at output frequency of 480 MHz and supply voltage of 1.2 V. The maximum time difference between two adjacent phase clocks was measured to be 6 ps at 480 MHz. The measured rms and peak-to-peak output jitters were 8.6 ps and 45 ps, respectively. (b) ACKNOWLEDGMENTS Fig. 7. (a) Measured rms and peak-to-peak jitter for 480 MHz (49,298 hits), (b) measured phase noise. This work was supported by the National Research Foundation of the Ministry of Science, ICT and Future Planning (MSIP), Korea, under the contract numbers of NRF-2014R1A2A1A and IDEC. REFERENCES [1] Fig. 8. Chip photo and layout. Pyoungwon Park, Jaejin Park, Hojin Park, Seonghwan Cho, An All-Digital Clock Generator

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, Using a Fractionally Injection-Locked Oscillator in 65nm CMOS, IEEE ISSCC Dig. Tech. Paper, pp , [2] Yongsam Moon, A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current- Bypass Technique, J. Semicond. Technol. Sci., vol. 14, no. 3, pp , June [3] Chao-Ching Hung and Shen-Iuan Liu, A leakagesuppression technique for phase locked systems in 65nm CMOS, IEEE ISSCC Dig. Tech. Papers, pp , [4] Yuanfeng Sun, Jun Li, Zhuo Zhang, Min Wang, Ni Xu, Hang Lv, Woogeun Rhee, Yongming Li, Zhihua Wang, A GHz Boosted-Gain Type-I PLL with <15% Loop Filter Area, IEEE RFIC, pp , [5] Wooseok Kim, Jaejin Park, Jihyun Kim, Taeik Kim, HoJin Park, and DeogKyoon Jeong, A 0.032mm 2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz Tuning Range, IEEE ISSCC Dig. Tech. Paper, pp , [6] Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa, A mm 2 780μW Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase Coupled Oscillator Using Edge-Injection Technique, IEEE ISSCC Dig. Tech. Paper, pp , [7] Muhammad Faisal and David D. Wentzloff, An Automatically Placed-and-Routed ADPLL for the MedRadio Band using PWM to Enhance Resolution, IEEE RFIC, pp , [8] Werner Grollitsch, Roberto Nonis and Nicola Da Dalt, A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS, IEEE ISSCC Dig. Tech. Paper, pp , [9] Robert Bogdan Staszewski, Porast Balsara, Alldigital frequency synthesizer in deep-submicron cmos Kihwan Seong received the B.S. degree in the Department of Electronic and Electrical Engineering from KyungPook National University, Korea, in 2009 and M.S. degree in Electronic Engineering from Pohang University of Science and Technology (POSTECH), Korea, in 2011, respectively. He is currently pursuing the Ph.D. degree in the Department of Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea. His interests include high-speed interface circuits and all-digital synthesizable circuits. Won-Cheol Lee received the B.S. degree in the Department of Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea, in He is currently pursuing the M.S and Ph.D. degree in the Department of Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea. His interests include all-digital synthesizable circuits Byungsub Kim received the B.S. degree in Electronic and Electrical Engineering (EEE) from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2000, and the M.S. (2004) and Ph.D. (2010) degrees in Electrical Engineering and Computer Science (EECS) from Massachusetts Institute of Technology (MIT), Cambridge, USA. From 2010 to 2011, he worked as an analog design engineer at Intel Corporation, Hillsboro, OR, USA. In 2012, he joined the faculty of the department of Electronic and Electrical Engineering at POSTECH, where he is currently working as an assistant professor. He received several honorable awards. In 2011, Dr. Kim received MIT EECS Jin-Au Kong Outstanding Doctoral Thesis Honorable Mentions, and IEEE 2009 Journal of Solid-State Circuits Best Paper Award. In 2009, he received Analog Device Inc. Outstanding Student Designer Award from MIT, and was also a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 IEEE Internal Solid-State Circuits Conference.

7 358 KIHWAN SEONG et al : ALL-SYNTHESIZABLE 5-PHASE PHASE-LOCKED LOOP FOR USB2.0 Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea, in 1993, 1995, and 1999, respectively. From 1999 to 2005, he worked as a senior engineer at Samsung Electronics, Korea. From 2003 to 2005, he was a post-doctoral researcher with the University of Southern California, Los Angeles. From 2011 to 2012, he was a visiting scholar with the University of Michigan, Ann Arbor. In 2005, he joined POSTECH, where he is currently an Associate Professor. He has served in the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC), Symposium on VLSI Circuits, and Asian Solid- State Circuits Conference. He is a co-recipient of the Takuo Sugano Award at ISSCC His research interests include high-speed serial/parallel links, PLLs, data converters and power module for plasma generation. Hong-June Park received the B.S. degree from the Department of Electronic Engineering, Seoul National University, Seoul, Korea, in 1979, the M.S. degree from the Korea Advanced Institute of Science and Technology, Taejon, in 1981, and the Ph.D. degree from the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, in He was a CAD engineer with ETRI, Korea, from 1981 to 1984 and a Senior Engineer in the TCAD Department of INTEL from 1989 to In 1991, he joined the Faculty of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Gyeongbuk, Korea, where he is currently Professor. His research interests include CMOS analog circuit design such as high-speed interface circuits, ROIC of touch sensors and analog/digital beamformer circuits for ultrasound medical imaging. Prof. Park is a senior member of IEEE and a member of IEEK. He served as the Editor-in-Chief of Journal of Semiconductor Technology and Science, an SCIE journal ( from 2009 to 2012, also as the Vice President of IEEK in 2012 and as the technical program committee member of ISSCC, SOVC and A-SSCC for several years.