MODELING THE PHASE STEP RESPONSE OF BANG-BANG DIGITAL PLLS

Transcription

1 MODELING THE PHASE STEP RESPONSE OF BANG-BANG DIGITAL PLLS Moataz Abdelfattah Supervised by: AUC Prof. Yehea Ismail Dr. Maged Ghoniema Intel Dr. Mohamed Abdel-moneum (Industry Mentor)

2 Outline Introduction Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

3 Outline Introduction What is BB-PLLs Motivation Scope of work & Methodology Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

4 What is a PLL? A circuit responsible for generating clock signal for electronic devices Crystal Oscillator PLL Clock A Clock B Very slow - Low phase noise Very fast - Low phase noise

5 PLL Operation Reference Phase Detector Loop Filter Controlled Oscillator Output Clock Frequency Divider Negative feedback system Compares reference to a divided version of output clock Guarantees purity through ve FB

6 PLL Types Trend: Past Analog Design Future Digital Design Analog Digital Features: Analog: High Accuracy Digital: Scalable Challenges: Technology scales down Analog design difficult!!

7 Digital PLLs Digital PLL: Bang-Bang Non linear, low performance, low power TDC - linear, good performance, high power Phase Detector Output BB Loop Filter Controlled Oscillator Phase Error Frequency Divider Nonlinear PD TDC Loop Filter Controlled Oscillator Phase Detector Output Phase Error Frequency Divider Linear PD

8 BB-PLL Pros Cons Applications Pros Low Power Simple Implementation (simple phase detector) Cons Non-linear loop dynamics (due to non-linear phase detector): No well defined design methodology Unreliable response Apps Traditionally: CDR Recently: Microprocessors, Wireless Transceivers, SoCs

9 Outline Introduction What is BB-PLLs Motivation Scope of work & Methodology Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

10 Thesis Motivation Recent interest in low power designs: Interest in BB-PLLs use in high performance apps (microprocessors and wireless applications) Non-linearity of BB-PLLs prevent their use in high performance Apps.: Need to solve problems caused due to non-linearity Not much work in the literature on solving BB-PLLs problems

11 Problems Due to Nonlinearity 1. System Modeling 2. Unreliable Response

12 Problem 1 - Modeling Nonlinear no TF analysis PLL System Response Linear PLL Design Methodology BB-PLL Design Parameters Desired Response

13 Problem 2 Nonlinear Response BW Phase error magnitude CPPLL BBPLL 1 1 Independent of input phase error Depending on input phase error

14 Problem 2 Nonlinear Response CPPLL BBPLL ref ref FB FB Ph Err Ph Err Control Control Control Voltage proportional to input error Control Word not proportional to input error

15 Phase Error Mag. Phase Error Mag. Problem 2 Nonlinear Response BW Phase error magnitude CPPLL BBPLL Control (Ip) Control (digital word)

16 Literature On problem 1 (Modeling): Only one model is proposed by Razavi in 2003 [1] Model valid only for small Phase Error Magnitudes (PEMs) Model is specific for error patterns at CDR applications On Problem 2 (Nonlinear Response): Different solutions proposed Circuit techniques to regulate the BW through digital algorithms Literature shortage in Modeling Thesis focus on Modeling

17 Outline Introduction What is BB-PLLs Motivation Scope of work & Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

18 Scope of Work Modeling Finding a solution mainly for problem 1 Goal: Well Defined Design Methodology Insights Nonlinear Response Techniques enhance response

19 Methodology Mathematical Representation of the time domain phase step response Predict BW, Stability For different PEMs Verify Model through comparison with circuit implementation Propose Techniques to enhance linearity (problem 2)

20 Outline Introduction Proposed Modeling Methodology Model Parameters Model Derivation BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

21 Modeling (objective? How?) Objective? Predicting BW Predicting Stability Estep 0.1 Phase Error How? Phase Step Response Settling Stability Settling time BW Clock Cycles

22 Modeling (How to predict stability?) Phase Err. Phase Error (ns) Feedback Period (ns) Frequency Err. Maximum Frequency Error Minimum Frequency Error Reference Cycles Number of Cycles (i)

23 Phase Error Mag. Phase Error Mag. Modeling (predicting BW what is BW?) BW: How fast PLL can track jitter CPPLL BBPLL Constant BW Variable BW

24 Phase Error (ns) Modeling (How to predict BW?) m1 m Reference Cycles

25 Modeling (predicting BW & Stability) Input phase error (E) Objective System of Equations

26 Outline Introduction Proposed Modeling Methodology Model Parameters Model Derivation BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

27 Phase Error (ns) Modeling Methodology 0.12 Phase step error loop acts to compensate Phase at zero crossings equals zero Phase due to step err. = phase due to loop action Mathematical Representation of both phase components (step & loop action) Reference Cycles Equate at zero crossings

28 Modeling (BB-ADPLL Operation) Proportional Coeff. Conventional PI DLF Frequency Control digital Word BB-PD + FCW DCO Feedback Frequency Divider Integral Coeff.

29 Modeling (DLF Operation) BB-PD BB_Out + FCW DCO BB_Out Polarity Change -1-1 Proportional Contribution Per BB decision FCW Integral Contribution Per BB decision

30 Modeling Methodology Conventional PI DLF Phase due to loop action: BB-PD + DCO Proportional path Feedback Frequency Divider DCO phase change due to one change in the FCW (DCO resolution) 0.1 Integral Path FCW = x

31 Phase Error (ns) Modeling Methodology m Reference Cycles

32 Modeling Methodology FCW = x

33 Modeling Methodology

34 Modeling (outcome) CPPLL Design Methodology BBPLL Desired Response Desired Response for suitable range of PEM TF Eqns Set Design Parameters Set Design Parameters

35 Outline Introduction Proposed Modeling Methodology BB-ADPLL System System Architecture & Performance Model Verification Proposed Techniques for Enhanced System Response Conclusion & Future Work

36 BB-ADPLL Pin Diagram REF_clk reset N BB-ADPLL DCO_clk

37 BB-ADPLL FC Slow/Fast BSA reset Pipeline 5 Register 5 (D1) Thermometer Decoder (5x21) Coarse 21 Frequency Acquisition Loop REF_clk BB ± 1 DLF1 6 reset D C O DCO_clk Buffer out_clk M U X Pipeline Register (D2) FCW 6 Thermometer Decoder (6x35) Fine 35 1/D Update_Clock DLF2 6 Phase Acquisition Loop Feedback Signal 1/N Custom Design RTL

38 BB-ADPLL (DCO) FCW[76:66] FCW[65:55] FCW[54:44] FCW[43:33] FCW[32:22] FCW[21:11] FCW[10:0] M0p M0n M1n M2n M3n Fine Coarse

39 Frequency (GHz) DCO Frequency Range Frequency Resolution 6 5 Frequency Coarse Fine Step 4 (GHz) Step (MHz) (MHz) Coarse Code 1.5 (Min) (Max) Average

40 PLL Results Locked at 3 GHz Re-lock Time Phase step introduced here

41 PLL Results Frequency Lock Time (us) RMS Jitter (ps) Peak-to-Peak Jitter (ps) 2 GHz GHz GHz COMPARISON This Work ISSCC 2012 [2] Measurement Frequency 3 GHz 3 GHz Supply 1.05 V V. RMS Jitter 0.88 ps 0.8 ps Silicon No Yes

42 Outline Introduction Proposed Modeling Methodology BB-ADPLL System System Architecture & Performance Model Verification Proposed Techniques for Enhanced System Response Conclusion & Future Work

43 Model Verification model sim model sim Update Cycles Update Cycles PEM = 600ps PEM = 1200ps

44 Model Verification 6 5 model sim model sim Update Cycles Update Cycles PEM = 2400ps PEM = 5000ps

45 Model Verification PEM (ps) Accuracy % ns 360 ns 75% ns 880 ns 88.6% ns 1120 ns 87.5% ns 2190 ns 94.3%

46 Model Accuracy

47 Outline Introduction Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Technique 1 Technique 2 Conclusion & Future Work

48 Proposed Technique 1 PI Digital Loop Filter BB-PD Non-linear Gain + DCO Counter Gain Linearization Frequency Divider

49 Proposed Technique 1 Phase Error Magnitude Phase Error Magnitude time time FCW time time (a) (b)

50 Proposed Technique 1 New DLF Architecture In FCW......

51 Phase Error (ns) Phase Error (ns) Proposed Technique 1 New DLF Operation FCW FCW Conventional DLF Reference Cycles Reference Cycles Reference Cycles t1 Reference Cycles

52 Technique 1 verification t1 (ns) Conventional Proposed Ideal (linear) PEM (ns)

53 Outline Introduction Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Technique 1 Technique 2 Conclusion & Future Work

54 Phase Error (ns) Proposed Technique 2 At first zero crossing: Phase Error = 0 Freq. Error = Ef1 Add circuitry to estimate Ef1 : Ef1 = (α m1 + β) FCW = x Reference Cycles At first zero crossing: Subtract Ef1 from FCW At first zero crossing: Phase Error = 0 Freq. Error 0 Relock Time Reduced

55 Technique 2 verification PEM (ps) Percentage Reduction ns 215 ns 55.2 % ns 406 ns 53.8 % ns 457 ns 59.1 %

56 Outline Introduction Proposed Modeling Methodology BB-ADPLL System Proposed Techniques for Enhanced System Response Conclusion & Future Work

57 Conclusion BB-PLL: low power nonlinearity Nonlinearity: modeling problem Model predict system response in terms of design parameters provides design methodology Model insights proposed techniques to enhance system linearity (SL enhanced by 35%, Re-lock time enhanced by 55%)

58 Future Work Physical Design (further verification of model) Enhance accuracy (Re-develop model with less assumptions)

59 References [1] J. Lee, K. S. Kundert, and B. Razavi, Analysis and modeling of bangbang clock and data recovery circuits, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp , Sep [2] N. August, H. Lee, M. Vandepas, R. Parker, A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS, ISSCC Dig. Tech. Papers, pp , Feb., 2012.

60 Publications From This Work Accepted Abdelfattah M., Lotfy A., Abdel-moneum M., Kurd N., Ghoneima M., Taylor G., Ismail Y. Modeling the Response of Bang-Bang Digital PLLs to Phase Error Perturbations, IEEE in proceedings of CICC Abdelfattah M., Lotfy A., Abdelsalam M., Abdel-moneum M., Kurd N., Ghoneima M., Taylor G., Ismail Y. A Novel DLF Architecture for Digital Bang-Bang PLLs IEEE in proceedings of SOCC Under Preparation A Novel Technique to Reduce the Lock Time of BB-DPLLs (Conference) Abdelfattah M., Lotfy A., Abdel-moneum M., Kurd N., Ghoneima M., Taylor G., Ismail Y. Modeling the Phase Step Response of Bang-Bang Digital PLLs to Phase Error Perturbations, submitted to TCAS I.

61 QUESTIONS