Phase-Locked Loop Engineering Handbook for Integrated Circuits

Transcription

1 Phase-Locked Loop Engineering Handbook for Integrated Circuits Stanley Goldman ARTECH H O U S E BOSTON LONDON artechhouse.com

2 Preface Acknowledgments xiii xxi CHAPTER 1 Cetting Started with PLLs Definition and Operation Phase-Lock Loop Literature Books Articles Background Books WebSites Loop Classifications Example Applications History Doppler Radar Satellite Communications Cellular Phones Telecommunications Systems 11 Questions 12 References 13 CHAPTER 2 System Analysis VCO Mathematical Description Phase Detector Mathematical Relationship PLL Transfer Function and Control-Systems Theory Error Tracking Type 2, Second-Order Active Loop-to-Servo Terminology Loop Stability: Bode Plot Analysis Loop Stability: Root-Locus Analysis Charge Pump Synthesis Example of Loop-Component Values Summary 32 Questions 33 References 33 VII

3 VIII Contents CHAPTER 3 System Requirements Noise Basics Sources of Noise Noise Models Equivalent Input Noise Noise Figure Bipolar Versus CMOS Noise Comparison Phase-Noise and Oscillator Theory FM Theory Relationship of Phase Noise to FM Different Measures of Phase Noise Oscillator Design and Phase-Noise Modeling Negative-Resistance Oscillator Model Power Slopes of Oscillators Resonator Effects on Oscillator Phase Noise Allan Variance and Residual FM Calculations Phase Noise in PLLs Jitter in PLLs Causes of Jitter Phase-Noise Analysis on Jitter Analysis of Spurious Signals on Jitter Spurious-Noise-Reduction Techniques Time-Domain Solution Importance of Solving for the Time-Domain Response Time-Domain Solution Using La Place Transforms Relationship of Error Function to Closed Loop Output Responses to Unnormalized Input Steps Ramp Phase Solution Parabolic Phase Solution Acquisition of Lock Derivation of the Second-Order, Nonlinear, Ordinary Differential Equation Simplifying and Normalizing the Nonlinear Equation Difference Equation for Making the Phase-Plane Trajectory Plot Unnormalized Solution Measured Step Responses Inside and Outside the Separatrix Spurious Signals Intermodulation Products Minimizing the Generation of Reference Sidebands Noise-Reduction Techniques Summary 154 Questions 155 References 159 Appendix 3A: Single-Ended Explanation of Offset Currents 161

4 IX CHAPTER 4 Components, Part 1 Dividers and Oscillators Dividers Programmable Divider Pulse Swallowing Fractional Divide-by-N Voltage-Controlled Oscillators Operation of a Ring Oscillator Differential Ring Oscillators Multivibrators LC Resonant Oscillators LC Multivibrators Reference Oscillators Oscillator Circuits, Stability, and Startup Time Equations for Oscillation Stability of Oscillation Startup Time Summary 231 Questions 232 References 233 CHAPTER 5 Components, Part 2 Detectors and Other Circuits Phase Detectors Linear Model Phase Detector Figure of Merit Balanced Mixer Gilbert Multiplier Exclusive-OR Phase Detector RS Phase Detector (Two States) Phase/Frequency Detector Conclusion Lock Detection Quadrature Lock Detection Tune-Voltage Window Comparator Time-Window Edge Comparison Cycle-Slip Detector Cycle-Slip Detector Versus Time-Window Comparator Acquisition Aids Open-Loop Sweep Closed-Loop Sweep Discriminator Aided Charge Pumps Design Considerations for Opamps in a PLL Architecture Selection, Comparison to Basic Two-Stage Opamp 288

5 5.5.2 Basic Opamp Folded Cascode Differences Between Charge Pump and Operational Ampiifier Compensation Error Tracking of Charge Pump and Active Compensation Phase-Noise Suppression Phase-Error Tracking for Changing Input Frequency Summary 302 Questions 304 References 306 CHAPTER 6 Loop-Compensation Synthesis Revisited Ranking Requirements for PLLs Loop-Component Synthesis Active Compensation and Maximum Capacitor Value Sampling-Delay Synthesis Magnitude Response and Gain Constant of the Open-Loop- Gain Function Solving for PLL Component Values PLL Design with Sampling-Delay Examples Fast Switching Time Minimum Bandwidth of a PLL VCO Phase-Noise Limit Component Limits of Standard APLL Maximum-Divide-Ratio Example for Loop-Component Synthesis Optimum PLL Design for Low-Phase-Noise Performance PLL Phase-Noise Equations Damping-Factor Effect PLL Bandwidth Effect Equations to Compute Optimum PLL Bandwidth Summary 349 Questions 350 References 352 CHAPTER 7 Test and Measurement Hold-In Range, Lock Range, and Spurious Signals Switching Time Closed-Loop Bandwidth Measurement of Phase Noise Direct-Spectrum Measurements Carrier-Suppression Measurements Mixer as a Phase Detector in a Measurement System Carrier-Suppression Measurement Model Generating a Calibration Signal 370

6 XI Phase-Noise Measurement Equipment Phase-Noise Measurements with the HP Variations of the Carrier-Suppression Technique Testing for Jitter Oscilloscope Jitter Measurements TIA and Spectrum Analyzer Jitter Measurements Minimum Noise-Floor Measurements of TIA, Oscilloscope, and Digital Time Scope Isolation Measurements Between PLLs in Silicon Time-Jitter Test Setups Noise Immunity to Injected Signals Injected Signals into the Reference Input Injected Signals on Supply Power-On Switching Time Oscillator Open-Loop Test Test Equipment Troubleshooting PLLs Integrated Circuit Functional Check Requirement Compliance Checks Simulation 400 Questions 401 References 403 CHAPTER 8 Simulation Transistor Level Behavioral Modeling of PLL with PSPICE Example Behavioral Model of the 270-MHz PLL Model for Error Tracking Identifying Numerical Errors Difference-Equation Modeling of PLLs Review of Difference-Equation Derivation Extending the Difference Equations for Computer Simulation Example PLL Unique Nonlinear Conditions Simulated by the Difference Equation 431 Questions 443 References 444 CHAPTER 9 Applications and Extensions Design Trade-Offs in Frequency Generation with PLLs Classification Direct Synthesis Indirect Synthesis 450

7 9.1.4 Direct-Indirect Hybrids Application of Topologies Design Trade-Offs Architecture Design Example Monolithic Synthesizer Example Clock Recovery Properties of NRZ and RZ Data Edge Detection Clock-Recovery Architectures Phase Detectors for Clock Recovery Clock-Recovery Tests Effect of Phase Noise on A/D Converters Conversion of Phase Noise to Jitter Relationship of Time Jitter to Dynamic Range Phase Noise Versus Effective Bits Effective Bits at High Frequencies Effect of FM Sideband on Effective Bits All-Digital PLLs Operation of a Simple ADPLL Sampling and Stability ADPLL by Pulse Addition and Removal Summary 526 Questions 527 References 527 APPENDIX A Letter Symbols 529 APPENDIX B Glossary 533 About the Author 541 Index 543