Sudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal
|
|
- Griselda Harvey
- 5 years ago
- Views:
Transcription
1 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May Design and Performance Analysis of a Phase Locked Loop using Differential Voltage Controlled Oscillator Sudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal Abstract This paper is based on Phase locked-loop (PLL) using Differential Ring VCO in 350 nm CMOS Technology and illustrates the design process of various blocks of the PLL. The PLL is a closed loop system that compares the phase of an output signal with an input reference signal. PLLs are widely used in order to generate well-timed on-chip clocks to be used in high-performance digital systems. The entire circuit is implemented and simulated using Spice File and the tuning characteristics of the VCO was also verified from which the gain of the VCO was calculated. The estimated lock time of the PLL was found to be 10.02ns and the locking frequency was found to be 693 MHz and the gain of the VCO was estimated to be MHz/V. Index Terms Phase Locked Loop, Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator, Loop Filter, Locked State, Unlocked State. 1 INTRODUCTION 2 PLL ARCHITECTURE A Phase locked loop (PLL) is a closed loop frequency system that locks the phase of the output signal The major components of the PLL are: (1) The Phase to the reference signal. The term lock refers to a constant Frequency Detector (PFD), (2) The Charge Pump(CP), (3) or zero phase difference between two signals. The basic The Loop Filter (LPF), and (4) The Voltage controlled block diagram of the PLL is shown in the Figure 1. It is a Oscillator (VCO). The input to the PLL is a reference signal closed loop control system in which the output signal is whose value depends upon the user. The Phase Frequency synchronized with the input signal in terms of frequency Detector (PFD), compares the reference signal, and the and phase. The signal from the feedback path is compared feedback path, and generates an error signal. with the input reference signal, until the two signals are locked. If there happens to be a phase difference, then it is 2.1 Phase Frequency Detector called the unlocked state, and the signal is sent to each A phase frequency detector (PFD), is a device which component in the loop to correct the phase difference. compares the phase of two input signals and provides a signal in the form of phase error. It has two inputs which PFD CP LPF VCO correspond to two different input signals, usually one from a Differential Ring voltage controlled oscillator and other is a reference source. It has two outputs which instruct the subsequent circuitry on how to adjust to lock onto the N phase [1]. fig 1. The Basic Block Diagram of a PLL Sudatta Mohanty is currently pursuing masters degree program in VLSI Design nd Embedded Systems in ITER, S O University, Bhubaneswar, India, sudatta.mohanty2@gmail.com Madhusmita Panda is currently holding the position of an Assistant Professor in the Department of Electronics and Communication Enginneering in ITER, S O University, Bhubaneswar, India, madhusmitapanda@soauniversity.ac.in Dr Ashis kumar Mal is currently working in the Department of Electronics and Communication Enginneering in NIT Durgapur, West Bengal, India, akmal@ece.nit.dgp.ac.in fig 2. AND Gate based PFD
2 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May fig 5. Block Diagram of a basic PFD-CP fig 3. Schematic of AND gate based PFD The Charge Pump shown in Fig. 3 has only one output, so it is termed as a "single-ended Charge Pump". This Charge Pump consists of a current source, and two switches with inputs directly connected to the outputs of the PFD. The switches control the current from the Charge Pump (Icp) where it is sourced in proportion to the input phase error. The Current is sourced through S1 which is controlled by the Up output of the PFD which is therefore termed as the "UP current" (IUP ) with S1being termed as the Up switch. The Current then passes through switch S2 which is controlled by the "Down" output of the PFD [3]. This sink current is thereby termed as the Down current (IDN) with S2 acting as the Down switch. The Up and Down currents are respectively defined by a current source and current sink to make them constant in order to achieve a desirable loop performance. The combination of S1 and its current source is termed as the Up network and the combination of S2 and its current sink is termed the Down network. fig 4. Output of AND gate Based PDF when Ref leads Fin The phase frequency detector (comparator) produces an error output signal based on the phase difference between the phase of the feedback clock and the phase of the reference clock. 2.3 Loop Filter Loop filter is an important component in PLL, as it affects and determines the loop stability. It also provides the necessary control voltage that is required to adjust the frequency of the VCO. The Figure below shows the RC network, which includes a resistor in series with the filter capacitor. Each time the charge pump drives the R and C1 combination, a current is injected into the filter, and the control voltage experiences a jump.[2] To suppress this effect, a second capacitor (C2) is added in parallel with the resistor. 2.2 Charge Pump The Charge Pump produces a charge which is proportional to the error signal. The function of the charge pump is to take the digital Up and Down pulses from the PFD and convert them into an analog control voltage [2]. fig 6. A 3rd order loop filter
3 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May delay cell generates a wide frequency range and low phase noise VCO.. An ideal VCO is a circuit whose output frequency is linear function of its control voltage and this output frequency is represented by the following equation [10] pg 510: w out = w o + K vco V cont. (1) Where w o represents the intercept corresponding to V cont. = 0. and K vco denotes the gain or sensitivity of the circuit which is expressed in rad/s/v. fig 7. Schematic of the Proposed Charge Pump/LPF Figure 8 shows the output of the charge pump /LPF when the up signal is produced. When the up signal is produced from the PFD, then the control voltage of the VCO keeps on increasing and when the down signal is produced, then the control voltage of the VCO keeps on decreasing and when there is no phase difference, then the control voltage remains constant. Fig 10. Block Diagram of a VCO The tunable range of the VCO can be determined from the characteristics curve shown below: 2.4 Voltage Contolled Oscillator The voltage controlled oscillator is one of the most important building blocks of the PLL. There are many different implementations of VCOs. One of them is a ring oscillator based VCO. The proposed design for VCO in PLL is based on the Ring VCO, which is used in the clock generation Fig 11. Linear Characteristics curve of VCO subsystem. The main reason of using the ring oscillator is its ability to integrate easily and due to this integrated nature, The tuning range of VCO can calculated from the graph the ring oscillator is used in clock recovery data process for which is given as: serial circuit communication [5]. Tuning range = w2-w1 (2) Where w2 = Maximum Frequency and w1= Minimum Frequency and Gain of the VCO is given as: fig 9. Schematic view of ring oscillator A ring oscillator comprises of a number of delay stages, with the output of the last stage fed back as the input to the first. To achieve oscillation, the ring oscillator must provide a phase shift of 2π and it should have a unity voltage gain at the oscillation frequency. Each delay stage must provide a phase shift of π/n. Where N is the no of delay stages. The delay cell is a differential pair with loading and bias controls. The self biased techniques are used to reduce jitter and process variations. This arrangement for extended frequency range VCO results in a large gain of the VCO. The above negative feedback scheme combined with advanced K VCO w 2 w 1 V 2 V 1 (3) Fig 12. Formulated Characteristics of VCO
4 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May fig 13. The VCO Circuit The output of the above circuit should be differential in nature. As the differential circuits do not yield rail-to-rail outputs, so the differential output has to be converted into a single-ended output. fig 15.A simple DFF Circuit fig 14. Output of the VCO circuit The output in the above figure shows the oscillations of the VCO. It can be noted from the figure that, when the input is constant, the output frequency is also constant and when there are variations in the input signal, then the putput frequency also varies. 2.5 Frequency Divider It is one of the most important blocks of the PLL circuit. It is normally used for scaling purposes. It divides the VCO frequency in order to generate a frequency which is comparable with reference frequency. It scales down the frequency of the VCO output signal [5]. The output of the VCO is fed back to the input of the PFD via the frequency divider circuit. A simple D flip flop can act as a frequency divider circuit. The figure of a simple DFF based divide by 2 frequency divider circuit is shown below[5]. fig 16.Schematic of a simple DFF/ a Frequency Divider circuit In figure 16, the schematic of a simple divide-by 2 frequency divider is shown. Here four two-input nand gates are used. The truth table of the DFF is given in Table 1: Table1 Clk D Q QBar
5 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May fig 17.Output of a simple DFF/ a Frequency Divider circuit From the output given in figure 17, it can be clearly noted that,, the output is yielded significantly as per the truth table given in Table 1. fig 19. PLL Output in Locked State. The combined PLL circuit is shown in the figure below The above figure shows the combined output of the PLL circuit in the Locked state after its complete simulation. As stated above, the locked condition means, there is zero phase difference between the reference and the input frequency signals thus yielding in a constant charge pump output [10]. Table 2 The Performance Analysis of the entire PLL circuit is shown in Table 2 below: fig 18. The PLL Circuit The combined circuit of the PLL shown in figure 18 is simulated using Tanner EDA tool whose output in the locked condition is shown in figure 19. Sl No Parameters Simulated Results 1 Vdd 1v 2 Technology 350nm 3 Lock Time 10.02ns 4 Locking Frequency 693 MHz 5 Gain of VCO 120.5MHz/V Table 2 shows the simulated results of the combined PLL circuit where the locking frequency, lock time, and gain of the VCO are listed for better analysis.
6 International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May CONCLUSION The presented work describes the operation of the PLL and its different components. The simulation studies revealed the behavior of the individual components which were found to be as expected. In this paper, a better lock time was presented. The lock time of the PLL was found to be 10.01ns. The lock time of the PLL mainly depends on the PFD architecture used along with the parameters of the charge pump and the loop filter. So, by properly choosing the PFD architecture and adjusting the charge pump current and loop filter component values, a better lock time can be achieved. 4 REFERENCES [1] Yashpal Sen, Nitin Jain, Design and Implementation of Phase Locked Loop Using Current Starved Voltage Controlled Oscillator, Advance in Electronic and Electric Engineering. ISSN , Volume 4, 2014, pp Research India Publications. [2] M.Mano, G.Selva Priya, K. RekhaSwati Shri, Design and I,mplementation of Modified Charge Pump for Phase Locked Loop, International Journal of Emerging Technology and Advanced Engineering, ISSN , ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December [3] S. B. Rashmi, Siva S. Yellampalli, Design of Phase Frequency Detector and Charge Pump for High Frequency PLL, International Journal of Soft Computing and Engineering, vol.2, May 2012 Issue-2, pp [4] V.Lule, V.Nasre, Area efficient 0.18um CMOS phase frequency detector for high speed PLL, International Journal of Engineering Scientific and Research Publication, Volume 2, Feb.2012 pp 1-3 [5] Bibhu Prasad Panda, Design and analysis of an efficient Phase Locked Loop for Fast Phase and Frequency Acquistion, A thesis submitted by the department of Electronics and Communication Engineering, NIT Rourkela, [6] S.Williams,H.Thompson,M.Hufford,E.Naviask, An improved CMOS ring oscillator PLL with Less than 4ps RMS Accumulated Jitter, Proceedings of 2004 Custom Integrated Circuits Conference,SanJose, USA, [7] Yalcin, A.E., P. John, A 5.9-GHz voltage controlled ring oscillator in 0.18 um CMOS technology, IEEE J. Solid-State Circuit, 2004: pp [8] Roland.E.Best, Phase locked loop design and application, Mcgraw Hill publications, 5th edition [9] R.J.Baker, H.W.Li, D.E.Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press Series on Microelectronic Systems, 2002 [10] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Edition, 2002 [11] SijieZheng and Lili He, The Mixed-Signal Design of PLL with CMOS Technology, Department of Electrical Engineering San Jose State University...
Analysis of phase Locked Loop using Ring Voltage Controlled Oscillator
Analysis of phase Locked Loop using Ring Voltage Controlled Oscillator Abhishek Mishra Department of electronics &communication, suresh gyan vihar university Mahal jagatpura, jaipur (raj.), india Abstract-There
More informationAnalysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition
Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda 1 Department of Electronics and Communication Engineering, School of Electrical
More informationDesign and Implementation of Phase Locked Loop using Current Starved Voltage Controlled Oscillator in GPDK 90nM
International Journal of Advanced Research Foundation Website: www.ijarf.com, Volume 2, Issue 7, July 2015) Design and Implementation of Phase Locked Loop using Starved Voltage Controlled Oscillator in
More informationPhase Locked Loop Design for Fast Phase and Frequency Acquisition
Phase Locked Loop Design for Fast Phase and Frequency Acquisition S.Anjaneyulu 1,J.Sreepavani 2,K.Pramidapadma 3,N.Varalakshmi 4,S.Triven 5 Lecturer,Dept.of ECE,SKU College of Engg. & Tech.,Ananthapuramu
More informationDesigning of Charge Pump for Fast-Locking and Low-Power PLL
Designing of Charge Pump for Fast-Locking and Low-Power PLL Swati Kasht, Sanjay Jaiswal, Dheeraj Jain, Kumkum Verma, Arushi Somani Abstract The specific property of fast locking of PLL is required in many
More informationDesign of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 03, 2015 ISSN (online): 2321-0613 Design of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationFFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase Locked Loop
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase
More informationAmerican International Journal of Research in Science, Technology, Engineering & Mathematics
American International ournal of Research in Science, Technology, Engineering & Mathematics Available online at http://www.iasir.net ISSN (Print): 2328-3491, ISSN (Online): 2328-3580, ISSN (CD-ROM): 2328-3629
More informationDesign of CMOS Phase Locked Loop
2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Design of CMOS Phase Locked Loop Kaviyadharshini Sivaraman PG Scholar, Department of Electrical
More informationTaheri: A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop
Engineering, Technology & Applied Science Research Vol. 7, No. 2, 2017, 1473-1477 1473 A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop Hamidreza Esmaeili Taheri Department of Electronics
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationDelay-Locked Loop Using 4 Cell Delay Line with Extended Inverters
International Journal of Electronics and Electrical Engineering Vol. 2, No. 4, December, 2014 Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters Jefferson A. Hora, Vincent Alan Heramiz,
More informationLow Power Phase Locked Loop Design with Minimum Jitter
Low Power Phase Locked Loop Design with Minimum Jitter Krishna B. Makwana, Prof. Naresh Patel PG Student (VLSI Technology), Dept. of ECE, Vishwakarma Engineering College, Chandkheda, Gujarat, India Assistant
More informationEnergy Efficient and High Speed Charge-Pump Phase Locked Loop
Energy Efficient and High Speed Charge-Pump Phase Locked Loop Sherin Mary Enosh M.Tech Student, Dept of Electronics and Communication, St. Joseph's College of Engineering and Technology, Palai, India.
More informationDesign of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop
Design of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop Shaik. Yezazul Nishath School Of Electronics Engineering (SENSE) VIT University Chennai, India Abstract This paper outlines
More informationVCO Based Injection-Locked Clock Multiplier with a Continuous Frequency Tracking Loop
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 13, Issue 4, Ver. I (Jul.-Aug. 2018), PP 26-30 www.iosrjournals.org VCO Based Injection-Locked
More informationA 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS
A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key
More informationA New Phase-Locked Loop with High Speed Phase Frequency Detector and Enhanced Lock-in
A New Phase-Locked Loop with High Speed Phase Frequency Detector and Enhanced Lock-in HWANG-CHERNG CHOW and NAN-LIANG YEH Department and Graduate Institute of Electronics Engineering Chang Gung University
More informationDesigning Nano Scale CMOS Adaptive PLL to Deal, Process Variability and Leakage Current for Better Circuit Performance
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume 1, Issue 3, June 2014, PP 18-30 ISSN 2349-4042 (Print) & ISSN 2349-4050 (Online) www.arcjournals.org Designing
More informationDESIGN AND ANALYSIS OF EFFICIENT PHASE LOCKED LOOP FOR FAST PHASE AND FREQUENCY ACQUISITION
DESIGN AND ANALYSIS OF EFFICIENT PHASE LOCKED LOOP FOR FAST PHASE AND FREQUENCY ACQUISITION A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI
More informationPHASE LOCKED LOOP DESIGN
PHASE LOCKED LOOP DESIGN by Kristen Elserougi, Ranil Fernando, Luca Wei SENIOR DESIGN PROJECT REPORT Submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical
More informationDESIGN OF FREQUENCY SYNTHESIZER
DESIGN OF FREQUENCY SYNTHESIZER A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIRMENTS FOR THE DEGREE OF MASTER OF TECHNOLOGY IN VLSI DESIGN & EMBEDDED SYSTEM By GAURAV KUMAR Roll No: 212EC2135 DEPARTMENT
More informationDESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS Nilesh D. Patel 1, Gunjankumar R. Modi 2, Priyesh P. Gandhi 3, Amisha P. Naik 4 1 Research Scholar, Institute of Technology, Nirma University,
More informationAvailable online at ScienceDirect. International Conference On DESIGN AND MANUFACTURING, IConDM 2013
Available online at www.sciencedirect.com ScienceDirect Procedia Engineering 64 ( 2013 ) 377 384 International Conference On DESIGN AND MANUFACTURING, IConDM 2013 A Novel Phase Frequency Detector for a
More informationISSN:
507 CMOS Digital-Phase-Locked-Loop for 1 Gbit/s Clock Recovery Circuit KULDEEP THINGBAIJAM 1, CHIRAG SHARMA 2 1 Department of E&CE, Nitte Meenaskhi Institute of Technology, Yelahanka, Bangalore-560064,
More informationResearch on Self-biased PLL Technique for High Speed SERDES Chips
3rd International Conference on Machinery, Materials and Information Technology Applications (ICMMITA 2015) Research on Self-biased PLL Technique for High Speed SERDES Chips Meidong Lin a, Zhiping Wen
More informationNRZ DPLL CMOS Frequency Synthesizer Using Active PI Filter
NRZ DPLL CMOS Frequency Synthesizer Using Active PI Filter Krishna Kant Singh 1, Akansha Mehrotra 2 Associate Professor, Electronics & Computer Engineering, Dronacharya College of Engineering, Gurgaon,
More informationSynchronous Mirror Delays. ECG 721 Memory Circuit Design Kevin Buck
Synchronous Mirror Delays ECG 721 Memory Circuit Design Kevin Buck 11/25/2015 Introduction A synchronous mirror delay (SMD) is a type of clock generation circuit Unlike DLLs and PLLs an SMD is an open
More informationOptimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
More informationIntroduction to CMOS RF Integrated Circuits Design
VI. Phase-Locked Loops VI-1 Outline Introduction Basic Feedback Loop Theory Circuit Implementation VI-2 What is a PLL? A PLL is a negative feedback system where an oscillatorgenerated signal is phase and
More informationDESIGN OF A MODULAR FEEDFORWARD PHASE/FREQUENCY DETECTOR FOR HIGH SPEED PLL
DESIGN OF A MODULAR FEEDFORWARD PHASE/FREQUENCY DETECTOR FOR HIGH SPEED PLL Raju Patel, Mrs. Aparna Karwal M TECH Student, Electronics & Telecommunication, DIMAT, Chhattisgarh, India Assistant Professor,
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationStudy and Implementation of Phase Frequency Detector and Frequency Divider 45nm using CMOS Technology
Study and Implementation of Phase Frequency Detector and Frequency Divider 45nm using CMOS Technology Dhaval Modi Electronics and Communication, L. D. College of Engineering, Ahmedabad, India Abstract--This
More informationA Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage
International Journal of Engineering & Technology IJET-IJENS Vol:14 No:04 75 A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage Mohamed A. Ahmed, Heba A. Shawkey, Hamed A. Elsemary,
More informationA CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati 1 B.K.Arun Teja 2 K.Sai Ravi Teja 3
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 06, 2015 ISSN (online): 2321-0613 A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati
More informationDESIGN AND ANALYSIS OF PHASE FREQUENCY DETECTOR USING D FLIP-FLOP FOR PLL APPLICATION
International Journal of Electronics Engineering Research. ISSN 0975-6450 Volume 9, Number 9 (2017) pp. 1389-1395 Research India Publications http://www.ripublication.com DESIGN AND ANALYSIS OF PHASE FREQUENCY
More informationA Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell
A Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell Devi Singh Baghel 1, R.C. Gurjar 2 M.Tech Student, Department of Electronics and Instrumentation, Shri G.S. Institute of
More informationEE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Announcements
EE290C - Spring 04 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 11 Components Phase-Locked Loops Viterbi Decoder Borivoje Nikolic March 2, 04. Announcements Homework #2 due
More informationDesign of a Frequency Synthesizer for WiMAX Applications
Design of a Frequency Synthesizer for WiMAX Applications Samarth S. Pai Department of Telecommunication R. V. College of Engineering Bangalore, India Abstract Implementation of frequency synthesizers based
More informationA GHz Wideband Sub-harmonically Injection- Locked PLL with Adaptive Injection Timing Alignment Technique
A 2.4 3.6-GHz Wideband Sub-harmonically Injection- Locked PLL with Adaptive Injection Timing Alignment Technique Abstract: This paper proposes a wideband sub harmonically injection-locked PLL (SILPLL)
More informationECE1352. Term Paper Low Voltage Phase-Locked Loop Design Technique
ECE1352 Term Paper Low Voltage Phase-Locked Loop Design Technique Name: Eric Hu Student Number: 982123400 Date: Nov. 14, 2002 Table of Contents Abstract pg. 04 Chapter 1 Introduction.. pg. 04 Chapter 2
More informationECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 11: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Exam 1 is on Wed. Oct 3
More informationAll Digital Phase Locked Loop Architecture Design Using Vernier Delay Time-to- Digital Converter
ISSN:1991-8178 Australian Journal of Basic and Applied Sciences Journal home page: www.ajbasweb.com All Digital Phase Locked Loop Architecture Design Using Vernier Delay Time-to- Digital Converter 1 T.M.
More informationLow Power, Wide Bandwidth Phase Locked Loop Design
Low Power, Wide Bandwidth Phase Locked Loop Design Hariprasath Venkatram and Taehwan Oh Abstract A low power wide bandwidth phase locked loop is presented in the paper. The phase frequency detector, charge
More informationLecture 7: Components of Phase Locked Loop (PLL)
Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 8: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam 1 is
More informationComparison And Performance Analysis Of Phase Frequency Detector With Charge Pump And Voltage Controlled Oscillator For PLL In 180nm Technology
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver. I (Jul - Aug. 2015), PP 22-30 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Comparison And Performance Analysis
More informationISSN: International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 2, February 2012
A Performance Comparison of Current Starved VCO and Source Coupled VCO for PLL in 0.18µm CMOS Process Rashmi K Patil, Vrushali G Nasre rashmikpatil@gmail.com, vrushnasre@gmail.com Abstract This paper describes
More informationLecture 23: PLLs. Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 23: PLLs Announcements Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class Open book open notes Project
More informationLETTER A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
196 LETTER A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation Ching-Yuan YANG a), Member and Jung-Mao LIN, Nonmember SUMMARY In this letter, a 1.25-Gb/s 0.18-µm
More informationHigh-Speed Serial Interface Circuits and Systems
High-Speed Serial Interface Circuits and Systems Design Exercise4 Charge Pump Charge Pump PLL ɸ ref up PFD CP LF VCO down ɸ out ɸ div Divider Converts PFD phase error pulse (digital) to charge (analog).
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationPhase Locked Loop Design as a Frequency Multiplier
Phase Locked Loop Design as a Frequency Multiplier A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By GEORGE TOM
More informationA Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop
A Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop Seong-Jin An 1 and Young-Shig Choi 2 Department of Electronic Engineering, Pukyong National University
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report
More informationA 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider. Hamid Rategh, Hirad Samavati, Thomas Lee
A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider Hamid Rategh, Hirad Samavati, Thomas Lee OUTLINE motivation introduction synthesizer architecture synthesizer building
More informationPhase Locked Loop using VLSI Technology for Wireless Communication
Phase Locked Loop using VLSI Technology for Wireless Communication Tarde Chaitali Chandrakant 1, Prof. V.P.Bhope 2 1 PG Student, Department of Electronics and telecommunication Engineering, G.H.Raisoni
More informationThe Use and Design of Synchronous Mirror Delays. Vince DiPuccio ECG 721 Spring 2017
The Use and Design of Synchronous Mirror Delays Vince DiPuccio ECG 721 Spring 2017 Presentation Overview Synchronization circuit Topologies covered in class PLL and DLL pros and cons Synchronous mirror
More informationECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 20: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 2 is on Friday Nov. 9 One double-sided 8.5x11
More information[Prajapati, 3(3): March, 2014] ISSN: Impact Factor: 1.852
[Prajapati, 3(3): March, 2014] IN: 2277-9655 IJERT INTERNATIONAL JOURNAL OF ENGINEERING CIENCE & REEARCH TECHNOLOGY Low Power and Low Dead Zone Phase Frequency Detector in PLL Jaimini Prajapati *1, Kiran
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 6, June ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 6, June-2013 1 Design of Low Phase Noise Ring VCO in 45NM Technology Pankaj A. Manekar, Prof. Rajesh H. Talwekar Abstract: -
More informationGeared Oscillator Project Final Design Review. Nick Edwards Richard Wright
Geared Oscillator Project Final Design Review Nick Edwards Richard Wright This paper outlines the implementation and results of a variable-rate oscillating clock supply. The circuit is designed using a
More informationHigh Speed PFD with Charge Pump and Loop Filter for Low Jitter and Low Power PLL
High Speed PFD with Charge Pump and Loop Filter for Low Jitter and Low Power PLL 1 Kruti P. Thakore, 2 Harikrishna C. Parmar, 3 Dr.N.M. Devashrayee 1 Dept. of EC, L.D.R.P. Institute of Technology, Gandhinagar,
More informationA CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor
Technology Volume 1, Issue 2, October-December, 2013, pp. 01-06, IASTER 2013 www.iaster.com, Online: 2347-6109, Print: 2348-0017 A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor Bollam
More informationA Comparative review and analysis of different phase frequency detectors for Phase Locked Loops
A Comparative review and analysis of different phase frequency detectors for Phase Locked Loops Anu Tonk Department of Electronics & Communication Engineering, F/o Engineering and Technology, Jamia Millia
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 12: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report #2 due Apr. 20 Expand
More informationDesign of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique
Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique Juliet Abraham 1, Dr. B. Paulchamy 2 1 PG Scholar, Hindusthan institute of Technology, coimbtore-32, India 2 Professor and HOD,
More informationA Performance Comparision of OTA Based VCO and Telescopic OTA Based VCO for PLL in 0.18um CMOS Process
A Performance Comparision of OTA Based VCO and Telescopic OTA Based VCO for PLL in 0.18um CMOS Process Krishna B. Makwana Master in VLSI Technology, Dept. of ECE, Vishwakarma Enginnering College, Chandkheda,
More informationFRACTIONAL-N FREQUENCY SYNTHESIZER DESIGN FOR RFAPPLICATIONS
FRACTIONAL-N FREQUENCY SYNTHESIZER DESIGN FOR RFAPPLICATIONS MUDASSAR I. Y. MEER Department of Electronics and Communication Engineering, Indian Institute of Technology (IIT) Guwahati, Guwahati 781039,India
More informationFractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
More informationDESIGN OF A 4GHz PROGRAMABLE FREQUENCY SYNTHESIZER FOR IEEE a STANDERD
DESIGN OF A 4GHz PROGRAMABLE FREQUENCY SYNTHESIZER FOR IEEE-802.11a STANDERD A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology In VLSI Design & Embedded
More informationDESIGNING PHASE FREQUENCY DETECTOR USING DIFFERENT DESIGN TECHNOLOGIES
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online), AND TECHNOLOGY
More informationA 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application
Journal of Chongqing University (English Edition) [ISSN 1671-8224] Vol. 12 No. 2 June 2013 doi:10.11835/j.issn.1671-8224.2013.02.008 To cite this article: HU Zheng-fei, HUANG Min-di, ZHANG Li. A 1.2-to-1.4
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 7: Phase Detector Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam
More informationINF4420 Phase locked loops
INF4420 Phase locked loops Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline "Linear" PLLs Linear analysis (phase domain) Charge pump PLLs Delay locked loops (DLLs) Applications Introduction
More informationICS PLL BUILDING BLOCK
Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled
More informationIntegrated Circuit Design for High-Speed Frequency Synthesis
Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency
More informationConcepts of Oscillators
Phase-Locked Loops Concepts of Oscillators Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering Overview Readings B. Razavi, Design of Integrated Circuits for Optical Communications,
More informationA 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.287 ISSN(Online) 2233-4866 A 10-Gb/s Multiphase Clock and Data Recovery
More informationISSN:
High Frequency Power Optimized Ring Voltage Controlled Oscillator for 65nm CMOS Technology NEHA K.MENDHE 1, M. N. THAKARE 2, G. D. KORDE 3 Department of EXTC, B.D.C.O.E, Sevagram, India, nehakmendhe02@gmail.com
More informationAn Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
More informationCMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL
IEEE INDICON 2015 1570186537 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 60 61 62 63
More informationFPGA IMPLEMENTATION OF POWER EFFICIENT ALL DIGITAL PHASE LOCKED LOOP
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) ISSN 0976
More information320MHz Digital Phase Lock Loop. Patrick Spinney Department of Electrical Engineering University of Maine
320MHz Digital Phase Lock Loop Patrick Spinney Department of Electrical Engineering University of Maine December 2004 Abstract DPLLs (Digital Phase Locked Loop) are commonly used in communications systems.
More informationDesign of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator
Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000, pp. 803 807 Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator Yeon Kug Moon Korea Advanced
More informationA 5Gbit/s CMOS Clock and Data Recovery Circuit
A 5Gbit/s CMOS Clock and Data Recovery Circuit Author Kok-Siang, Tan, Sulainian, Mohd Shahian, Soon-Hwei, Tan, I Reaz, Mamun, Mohd-Yasin, F. Published 2005 Conference Title 2005 IEEE Conference on Electron
More informationSelf-Biased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas
Self-Biased PLL/DLL ECG721 60-minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation Self-Biasing Technique Differential Buffer
More informationDedication. To Mum and Dad
Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative
More informationTHE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL
THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,
More informationDESIGN ANALYSIS OF PLL COMPONENTS A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
DESIGN ANALYSIS OF PLL COMPONENTS A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Bachelor of technology In Electronics &Instrumentation Engineering By Ranjit Dash Roll
More informationAnalysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop
Analysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop J. Handique, Member, IAENG and T. Bezboruah, Member, IAENG 1 Abstract We analyzed the phase noise of a 1.1 GHz phaselocked loop system for
More informationCLOCK AND DATA RECOVERY (CDR) circuits incorporating
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1571 Brief Papers Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits Jri Lee, Member, IEEE, Kenneth S. Kundert, and
More informationA Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 8, AUGUST 2002 1021 A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle Hsiang-Hui Chang, Student Member, IEEE, Jyh-Woei Lin, Ching-Yuan
More informationAn Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band
More informationDESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTA ADC FOR SIGNAL PROCESSING APPLICATION
ISSN: 2395-1680 (ONLINE) DOI: 10.21917/ijme.2016.0033 ICTACT JOURNAL ON MICROELECTRONICS, APRIL 2016, VOLUME: 02, ISSUE: 01 DESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTA ADC
More informationICS663 PLL BUILDING BLOCK
Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO)
More informationTHE serial advanced technology attachment (SATA) is becoming
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 979 A Low-Jitter Spread Spectrum Clock Generator Using FDMP Ding-Shiuan Shen and Shen-Iuan Liu, Senior Member,
More information