A 82.5% Power Efficiency at 1.2 mw Buck Converter with Sleep Control

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 ISSN(Print) ISSN(Online) A 82.5% Power Efficiency at 1.2 mw Buck Converter with Sleep Control Chung Hwan Son and Sangjin Byun Abstract This paper presents a DC-DC buck converter which uses a sleep control to improve the power efficiency in a few mw light load condition. The sleep control turns off analog controller building blocks to reduce the static power losses during the offduty period of pulse width modulation. For verification, a buck converter has been implemented in a 0.18 mm CMOS process. The power efficiency has been improved from 76.7% to 82.5% with a 1.2 mw load. The maximum power efficiency is 95% with a 9 mw load. Index Terms Buck converter, sleep control, current sensor, CMOS integrated circuits I. INTRODUCTION Depending on the system applications, buck converters are required to operate in various load conditions from mw to W [1-6]. When a buck converter should supply only a few mw power to a low power system, the static power loss becomes relatively important while the percentage of the conduction loss and the switching loss is decreased in the total power loss [4, 7]. In this paper, we propose a sleep control function for a light load buck converter to improve the power efficiency by reducing the static power loss during the off-duty period of pulsewidth modulation (PWM). This paper is organized as follows. Section II explains the architecture and the operation of the buck converter. In Section III, the circuits of the implemented building blocks are described. Measurement results and conclusions are given in Section IV. II. ARCHITECTURE Fig. 1 shows the architecture of the implemented buck converter with the proposed sleep control function. This buck converter consists of an oscillator, an error amplifier, a comparator, a PWM controller, a dead time buffer, two PMOS/NMOS power transistors, an over current protector and a loop compensator. With the proposed sleep control, some of the analog building blocks are turned off periodically by the PWM signal to minimize the static power losses while not affecting the operation of the buck converter. In this buck converter, the error amplifier, the comparator and the current sensor have been designed to be turned on and off according to the PWM signal. However, the oscillator cannot be turned off at any time because it has to generate V CLK to synchronize the buck converter. In [8, 9], the sleep control has been also proposed to enhance the power efficiency of a buck converter in a Manuscript received May. 8, 2016; accepted Aug. 11, 2016 Div. of Electronics and Electrical Engineering, Dongguk University, Seoul, Korea sjbyun@dongguk.edu Fig. 1. System architecture of the buck converter with sleep control.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, Fig. 2. Sleep control timing diagram. light load condition. But the sleep control was applied to only the comparator. The reason why the sleep control has not been applied to the error amplifier is that the error amplifier has generally a large loop compensation filter at the output so that it cannot be turned on and off periodically. However, in this paper, we have located the loop compensation block at the input of the error amplifier such that we can also turn off the error amplifier periodically during the off-duty period. Fig. 2 shows the timing diagram to explain how the sleep control can reduce the static power loss and does not affect the operation of the buck converter at all. First, the PWM signal, V PWM, is set high by the clock signal, V CLK, which is generated from the oscillator. V PWM activates the error amplifier, the comparator and the current sensor to start their operations. Then, the output of the error amplifier, V ERROR, is compared with the ramp signal, V RAMP, in the comparator. If the increasing V RAMP becomes larger than V ERROR, V PWM is set low as shown in Fig. 2. Because the task of both the error amplifier and the comparator is only to indicate the exact timing when V PWM should go to low, they don t need to operate and can be powered off during the off-duty period. Thus, if the duty ratio is D%, the static power losses of the analog building blocks with the sleep control can be reduced by (100-D)%. Specifically, the power losses of the error amplifier and the comparator have been reduced from 62.9 mw to 12.6 mw and from 83.3 mw to 16.7 mw, respectively, when the duty ratio is 20%. Fig. 3. Error amplifier, Comparator. III. BUILDING BLOCKS Fig. 3 shows the circuits of the error amplifier and the comparator. V ON/OFF is the inverted signal of V PWM. Because V PWM should drive the dead time buffer, V ON/OFF has been used instead of V PWM to reduce the loading effect of V PWM. In Fig. 3, V ON/OFF can turn on and off the error amplifier and the comparator by switching the transistors M 1 and M 6, respectively. The simulated switching times from sleep to activation are both less than 1.5 nsec for the error amplifier and the comparator. Additionally, in Fig. 3, V ON/OFF pulls up V Z by using the additional transistor, M 12, when V ON/OFF is high. By doing so, the comparator output, V COMP, can always go to low even when the internal node at V Z becomes high impedance when V ON/OFF =1. The current sensor operates also based on the sleep control. Fig. 4 and shows the conventional and proposed current sensors which detect the current flowing through the PMOS power transistor, M P of Fig. 1. Because the inductor current, I L, increases only when M P flows the current, the current sensor just needs to detect the current flowing through M P while V PWM is high. Contrary to that the conventional current sensor still dissipates the static power even when it does not sense

3 844 CHUNG HWAN SON et al : A 82.5% POWER EFFICIENCY AT 1.2 MW BUCK CONVERTER WITH SLEEP CONTROL Fig. 5. Measured waveforms of V IN, V OUT, and V X, I L. Fig. 4. Conventional, Proposed current sensors. during the off-duty period [10-12], the proposed current sensor operates and dissipates the static power only when V PWM is high. In Fig. 4, M 13, M 17 and M 18 are the CMOS switches that are controlled by V P which is the driving signal of the PMOS power transistor, M P, and is logically equivalent to V ON/OFF. If V P =1, M 17 and M 18 are turned off and M 13 is turned on. Then, the gate voltage of M 15 is pulled up to V IN by M 13 such that the current sensor does not dissipate the static power at all. However, if V P =0, only M 13 is turned off and all the other transistors of the current sensor are turned on. Then, an almost constant current flows through M 16 and R 1 because the variation of V X is very small compared to V IN. V Y can follow V X because V Y =V X -V GS16 +V GS15. That is, the current flowing through M 14, M 15 and R 2 increases as V X decreases. Now, M 14 can copy the scaled current of the PMOS power transistor, M P, accurately because V Y =V X if the current flowing through M 14, M 15 and R 2 increases and becomes equal to the current flowing through M 16 and R 1 and if we design M 15 and M 16, and R 1 and R 2 match to each other, respectively. The sensing threshold is determined by the W/L ratio of M 14 to M P and the value of R 2. IV. MEASURED RESULTS AND CONCLUSION The proposed buck converter with the sleep control function has been implemented in a 0.18 mm CMOS process. The die area is 0.38 mm 2 including I/O pads. The input voltage range is 2.5V~4.5V, the output voltage range is 0.6 V~1.8 V and the output current range is 2 ma~40 ma. The measured switching frequency is 1.2 MHz and the off-chip inductor and capacitor values are 100 mh and 1 mf, respectively. Fig. 5 shows the measured input voltage, output voltage, inductor current and V X. To measure the small inductor current, I L, the conducting wire was wound 5 turns to enhance the sensitivity of the current probe. Fig. 5 shows that the operation of the buck converter is not affected at all by the sleep control function. By using the sleep control, the power efficiency has been improved from 76.7% to 82.5% with a 1.2 mw load as shown in Fig. 6. However, the power efficiency is less improved at a higher load condition as shown in Fig. 6 because the percentage of the conduction loss and the switching loss

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, improve the power efficiency of the buck converter. By turning off the error amplifier, the comparator and the current sensor during the off-duty period, the power efficiency of the implemented buck converter has been improved from 76.7% to 82.5% with a 1.2 mw load. ACKNOWLEDGMENTS This work was supported by Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (NRF-2012R1A1A ). Fig. 6. Power efficiency versus output current. REFERENCES [1] [2] Fig. 7. Measured load transient response. [3] [4] Fig. 8. Chip micrograph. increases in the total power loss as the output load current increases. The maximum power efficiency is 95% with a 9 mw load. Fig. 7 shows the load transient response when the load current changes between 4 ma and 40 ma. The measured load regulation is 0.22 mv/ma. Fig. 8 shows the chip micrograph. In conclusion, the sleep control has been proposed to [5] [6] J. Wang, J. Xu, G. Zhou and B. Bao, Pulse-TrainControlled CCM Buck Converter With Small ESR Output-Capacitor Industrial Electronics, IEEE Transactions on, Vol.60, No.12, pp , Dec., E. N. Y. Ho and P. K. T. Mok, Design of PWM Ramp Signal in Voltage-Mode CCM Random Switching Frequency Buck Converter for Conductive EMI Reduction, Circuits and Systems I, IEEE Transactions on, Vol.60, No.2, pp , Feb., P. Y. Wu, S. Y. S. Tsui and P. K. T. Mok, Areaand Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation, Solid-State Circuits, IEEE Journal of, Vol.45, No.8, pp , Aug., M. K. Alghamdi and A. A. Hamoui, A SpuriousFree Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣModulator Controller With a Scalable Sampling Frequency, Solid-State Circuits, IEEE Journal of, vol. 47, no. 4, pp , Apr., S. Cliquennois, A. Donida, P. Malcovati, A. Baschirotto, and A. Nagari, A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop, Solid-State Circuits, IEEE Journal of, vol. 47, no. 7, pp , Jul., G. Zhou, S. He, X. Zhang, and S. Zhong, Critical output-capacitor ESR for stability of V2 controlled buck converter in CCM and DCM, Electronics

5 846 CHUNG HWAN SON et al : A 82.5% POWER EFFICIENCY AT 1.2 MW BUCK CONVERTER WITH SLEEP CONTROL Letters, vol. 50, no. 12, pp , Jun., [7] R. Nowakowski and N. Tang, Efficiency of synchronous versus nonsynchronous buck converters, Analog Applications Journal, 4Q, ti.com/lit/an/slyt358/slyt358.pdf [8] S. Bandyopadhyay, Y. K. Ramadass and A. P. Chandrakasan, 20 μa to 100 ma DC-DC Converter With V Battery Supply for Portable Applications in 45 nm CMOS, Solid- State Circuits, IEEE Journal of, vol. 46, no. 12, pp , Dec., [9] K. Kwan and P. Kim, Converter with crossover frequency responsive to switching frequency, U. S. Patent B2, Jul., [10] Y.-H. Lee, Y.-Y. Yang, S.-J. Wang, K.-H. Chen, Y.-H. Lin, Y.-K. Chen and C.-C. Huang, Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency, Solid-State Circuits, IEEE Journal of, vol. 46, no. 4, pp , Apr., [11] C.-W. Chen and A. Fayed, A Low-Power Dual- Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS, Solid-State Circuits, IEEE Journal of, vol. 50, no. 9, pp , Sep., [12] C. Huang and P. K. T. Mok, An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency, Solid-State Circuits, IEEE Journal of, vol. 48, no. 11, pp , Nov., Chung Hwan Son was born in Seoul, Korea, on He received the B.S. degree and M.S. degree in the Department of Electronic Engineering from Dongguk University, Korea, in 2009 and 2011, respectively. He is currently working toward the Ph.D. degree in the Division of Electronic and Electrical Engineering from Dongguk University, Korea. His interests include power management circuits, analog and mixed-signal integrated circuits. Sangjin Byun was born in Seoul, Korea, in January, He received B.S., M.S., and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1997, 1999 and 2004, respectively. From 2001 to 2004, he was with Berkana Wireless (which was merged by Qualcomm), Seoul, Korea, and from 2004 to 2008, he was with Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea. In 2008, he joined Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Korea, where he is currently an Associate Professor. His research interests include theoretical analysis and circuit technique for analog integrated circuits.