Digital PWM IC Control Technology and Issues

Transcription

1 Digital PWM IC Control Technology and Issues Prof. Seth R. Sanders Angel V. Peterchev Jinwen Xiao Jianhui Zhang EECS Department University of California, Berkeley

2 Digital Control Advantages implement advanced control schemes multi-mode control (high/low power modes) adaptive algorithms spread-spectrum switching for EMI reduction flexibility and programmability integrate supervisory functions - fault detection, management, and reporting communicate with other digital devices - voltage scaling immunity to analog component variations and noise largely automated digital design flow 2

3 Digitally-Controlled Buck Converter digital PWM controller power train load V ref V in V d ADC PID DPWM V x L V adc V dpwm quantizers C I o V d discrete duty ratio V in V x V out = DV in 0 DT T 3

4 Quantization Resolution Issues Microprocessor VRM example V in V out V dpwm N dpwm 12 V 1 V 5 mv 11 bits IC Digital PWM (DPWM) implementation with f sw = 1 MHz requires 2 11 x 1 MHz = 2 GHz clk in counter-comp. scheme 2 11 = 2048 stages in a ring-oscillator-mux scheme Analogous requirement on A/D sampling process 4

5 Limit Cycling Possible limit cycling in steady state at freq. < fsw Hard to predict amplitude and frequency Output noise, EMI V o 1 LSB error bin 0 error bin transient DPWM levels ADC levels -1 LSB error bin Resolution (DPWM) < Resolution (ADC) 5

6 Limit Cycling Avoided Resolution (DPWM) > Resolution (ADC) Use integral term in control law V o 1 LSB error bin 0 error bin transient -1 LSB error bin DPWM levels ADC levels 6

7 No-Limit-Cycle Conditions 1. Resolution (DPWM) > Resolution (ADC) 2. Integral control is used 3. Nyquist stability criterion satisfied (quantization modeled with describing function) 7

8 Digital Dither (2-bit) 8

9 Experimental Example Vo (V) time (ms) time (ms) N dpwm = 7 bit hardware N dpwm = 7 bit + 3 bit dither N adc = 9 bit N adc = 9 bit V in = 5 V, V ref = 1.5 V, f sw = 250 khz 9

10 CMOS Hardware Ckt Cells: (1) DPWM VDD I bias 32-tap Differential Ring T s DT s D 5 5-bit MUX PWM Ring-MUX scheme 5-bit DPWM hardware + 5-bit digital dither 1 µa at 600 khz PFM sampling frequency sq. mm in 0.25 micron CMOS 10

11 (2) Ring-ADC Architecture VDD Analog Block Counter Digital Block Σ V o V ref M Counter D e M Counter Σ f 1 f 2 VSS V I f De Windowed quantization range Insensitive to switching noise Digital block synthesizable Counter Automatic monotonicity Wide Vo operating range 16 mv/step, 80 mv window, 0.15mm 2 in 0.25 µm CMOS 11

12 Application Example: Handset Power Management V in : V Buck converter system L V x V o V o : V, tolerance 2-3% I o : ma Battery C Cellular phone chip set Ctrl Controller V ref I o Ctrl (PWM) Ctrl (PFM) 12

13 Dual-mode System Diagram V in Buck converter IC V ref V o Comparator Ring ADC D e PFM control Logic PID Digital dither PWM control D DPWM MUX Ring osc. system clock Simplfied Power train V x L C V o MODE GND Dual mode controller Digital Pulse Width Modulator (DPWM) Power switches, drivers 13 On-chip power management input voltage to 5.5 V

14 PFM Mode Diagram & Switching Behavior V ref D PF M 0 Ctrl V in V x L V o Sample DPWM C Sample V o V ref Ctrl Converter discontinuous conduction Fixed on-time control Zero-DC-bias comparator for low power 14

15 Load Transient Response PWM Mode, 500µs/div I o 150mA 50mA Vin= 3.2 V, Vo= 1.2 V. Load step 100 ma V o, 20mV/div, AC coupled PFM Mode, 10µs/div I o 100mA V o, 20mV/div, AC coupled 12mV 0.1mA PWM mode: both steady-state voltages in ADC zero-error bin PFM mode: voltage ripple ma 15

16 Efficiency Efficiency: PWM and PFM Modes Output current Io (ma) V in = 4.5 V V o = 1.5 V PWM PFM PWM efficiency drops off at low I o PFM efficiency high at low I o Composite efficiency high over wide I o range 16

17 Chip Micrograph Active area 2 mm mm Power train Controller 2.6 mm 17

18 Advanced Functions: Multi-mode & On-Line Optimizing Control variable switching frequency control switch control switch PID control synchronous rectifier T eff T on Discontinuous Conduction Mode synchronous rectifier Continuous adaptive powerminimization control 18

19 Discontinuous Conduction Mode at Light Load Efficient operation over wide load range critical to battery life in mobile applications Turn synch. rectifier off when inductor current crosses zero Higher efficiency due to reduced rms current control switch synch. rectifier inductor current avg load current 0 19

20 Synch. Rect. Turn-off Timing 20

21 Synch. Rect. Turn-off Timing (light load data range) cont. cond. mode discont. cond. mode synch. rect. on synch. rect. off local minimum due to resonant switching force synch. rect. off 21

22 Synch. Rect. Turn-on Timing 22

23 Synchronous Rectifier Timing Adaptation Synch. rect. timing as function of load current is adjusted to minimize power loss 23

24 Summary See www-power.eecs.berkeley.edu for pubs and more details; Fundamental issues addressed: quantization resolution, sampling, limit cycling Low-power, robust CMOS analog-digital interface More than 3-fold quiescent current reduction for portable applications Power management function integrated in lowvoltage CMOS process Enables tunable, programmable compensator, direct communication with digital systems, etc 24