Converter IC for Cellular Phone. Mode Digitally-Controlled Buck. A 4 µa-quiescent-current Dual- Applications. Jianhui Zhang Prof.

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1 A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications Jinwen Xiao Angel Peterchev Jianhui Zhang Prof. Seth Sanders Power Electronics Group Dept. of EECS U. C. Berkeley

2 Outline Motivation Dual-mode controller Analog and digital interface Internal power management Experimental results Contributions 2

3 Motivation Immunity to analog component variations and noise Low quiescent current to extend standby time Computation capability for advanced control schemes (e.g. adaptive control) Enables programmable compensator, direct communication with digital systems Benefit from technology scaling, easier to migrate to new technology 3

4 Cellular Phone Power Management Buck converter system V in : V V x L V o V o : V I o : ma Battery C Cellular phone chip set Controller V ref 4

5 Dual-mode System Block Diagram V ref V o Comparator Ring ADC D e Logic PID Buck converter IC PFM control Digital dither PWM control D DPWM MUX Ring osc. system clock V in Simplfied Power train V x MODE GND High integration level on low voltage process Ultra-low quiescent current in PFM Dedicated analog-digital interface elements L V o C 5

6 PFM Mode Diagram & Switching Behavior D PF V ref M Sample 0 Ctrl DPWM V in V x L V o C Sample V o V ref Ctrl Converter discontinuous conduction Fixed on-time control Zero-DC-bias comparator for low power 6

7 PFM Mode Comparator M M clk 8 3 M 4 M 9 clk V on V op clk M 10 M 5 M 6 M 11 X Y clk V ip V in M 1 M P 2 clk M 7 Y.-T. Wang and B. Razavi An 8-bit 150MHz CMOS A/D Converter 7

8 PWM Mode ADC Considerations Windowed quantization range Tolerance to switching noise Digital implementation Wide Vo operating range Automatic monotonicity 8

9 DPWM Module Ring-MUX Scheme I bias VDD 32-tap Differential Ring DT s T s D 5-bit MUX PWM 5 5-bit DPWM hardware + 5-bit dither 1 1 μa at 600 khz PFM sampling frequency Oscillator as global clock generator 1. A. Peterchev Quantization resolution and limit cycling in digitally controlled PWM converters 9

10 Ring Oscillator with Subthreshold Bias Linear dependency of ring-oscillator frequency on bias current VDD I bias 7.0E E E E+06 Frequency (Hz) 3.0E+06 4.E-07 5.E-07 6.E-07 7.E-07 8.E-07 9.E-07 Current-starved 4- stage differential ring oscillator Bias Current (A) 10

11 Ring ADC Architecture V o VDD Analog Block V ref M Counter Counter Σ Digital Block D e M Counter Σ f 1 f 2 VSS Counter Sampling freq=500 khz, 80 mv quantization range, VDD=1.5 V Measured current: μa, area = 0.15 mm 2 on 0.25μm CMOS 11

12 PWM Mode: Compensation Network Integrator From ring-adc Fully on De Prop. & D Dither Derivative en Fully off Go to DPWM Comb Clamp Logic en Pin: EN en Soft start Soft_start counter 12

13 Power Train and Internal Power Management V in Internal voltage regulator V m =V in /2 I r I p -I n C m I ctr PWM, PFM controller Gate drive Gate drive I p I n= I p /2 M P1 M P2 M N2 M N1 SW Cascode power train with gate drives Cascoded power switches Voltage compatibility of controller circuitry Scavenges power from gate drive discharge total saving I p 13

14 Transient Response: PWM Mode Vin= 3.2 V, Vo= 1.2 V. 150mA Io 50mA Vo 20mV/div 500μs/div <16mV, within zero error bin 14

15 Transient Response: PFM Mode Vin= 3.2 V, Vo= 1.2 V. 100mA Io 0.12mA Vo, 20mV/div, AC coupled 10μs/div 15

16 Steady-state Response: PWM Mode Vin= 3.2 V, Vo= 1.2 V, fs = 500 khz. Load=100mA Switching node, 2V/div Vo, 20mV/div, AC coupled 500ns/div 16

17 Efficiency: PWM and PFM Modes Efficiency Output current Io (ma) PWM efficiency drops off at low I o PFM efficiency high at low I o Composite efficiency high over wide I o range PWM PFM V in = 4.5 V V o = 1.5 V. 17

18 Summary of Chip Performance Technology 0.25-μm CMOS (Max. supply 2.75 V) Input voltage range V Output voltage range V External LC filter L=10 μh, C=47 μf Maximum output current 400 ma PFM mode sampling frequency 600 khz PFM mode quiescent current 4 μa vs. 15 μa state-of-art PWM mode switching frequency MHz PWM mode DC output voltage precision ±0.8% PWM mode output voltage ripple 2 mv Active chip area 2 mm 2 18

19 Chip Micrograph Active area 2 mm mm Controller 2.6 mm Power train

20 Contributions Efficient digital control for mass market power management More than 3-fold quiescent current reduction Low-power and robust analog-digital interface Power management unit on low-voltage CMOS process Enables programmable compensator, direct communication with digital systems, etc 20

21 PWM Mode: Quantization Resolutions Problem: Steady state oscillation limit cycles 1 error bin 0 error bin -1 error bin ADC LSB s DPWM LSB s Solution: Multiple DPWM bins in ADC zero error bin 1 error bin 0 error bin -1 error bin Peterchev 03 Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters 21