WITH the growth of data communication in internet, high

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1 136 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 A 0.18-m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier I.-Hsin Wang, Student Member, IEEE, and Shen-Iuan Liu, Senior Member, IEEE Abstract A 1.25-Gbps automati- gain-control (AGC) amplifier is presented and it has been fabricated in m CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 db from 10 to 18.5 db, and its measured group delay is about ns. For the bit-error rate of 10 12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mv, respectively. It achieves input dynamic range of 24.7 db. The power dissipation is 43.2 mw from a single 1.8-V supply voltage. The chip area is 0.82 mm 0.56 mm includes I/O pads. Index Terms Automatic gain control (AGC), CMOS, variable gain amplifier (VGA). Fig. 1. Typical optical receiver front-end. I. INTRODUCTION WITH the growth of data communication in internet, high data capacity networks become more and more popular. For example, Ethernet passive optical network (EPON) is one of the important solutions for these applications. It is based on wavelength division multiplex (WDM) in optical fiber and data rate up to 1.25 Gbps [1], [2]. Fig. 1 shows the typical EPON receiver front-end. At the receiving end, the signal strengths vary significantly due to different lengths of optical fibers. Usually, an automatic gain control (AGC) [3] [5] amplifier is used to achieve a signal with constant amplitude for the succeeding clock and data recovery circuit. In this brief, a 1.25-Gbps AGC amplifier is presented for the applications in EPON receivers. In this brief, a new architecture for an AGC amplifier is proposed to achieve a constant settling time. The pseudo- exponentially controlled variable gain amplifier (VGA) is presented. It will have a constant settling time for this proposed AGC amplifier. The brief is organized as follows. Section II describes the proposed AGC amplifier architecture. The corresponding circuit designs will be presented in Section III. The measurement results will be given in Section IV. Finally, the conclusions are given in Section V. II. AGC AMPLIFIER ARCHITECTURE AGC amplifiers are widely applied in digital data communication [2], [3], [5]. In these applications, the preamble duration must exceed the settling time of the AGC amplifier. Therefore, an AGC amplifier has a constant settling time is required. Manuscript received September 11, This paper was recommended by Associate Editor G. Palumbo. The authors are with Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. ( lsi@cc.ee.ntu.edu.tw). Digital Object Identifier /TCSII Fig. 2. Small-signal model of the proposed AGC amplifier. Analyzed by the author in [6], the VGA with linear-in-decibels voltage gain characteristics leads the AGC amplifier to have a constant settling time. It requires the VGA with the exponential gain characteristic as where, and are constants, and is the gain controlling signal. Since there is no intrinsic exponential characteristic for the MOS transistors in the strong inversion, one possibility is using parasitic bipolar devices [7]. However, the parasitic bipolar devices have a limited frequency response. Alternatively, the pseudo-exponential technique is usually implemented in CMOS technology [8] [11]. The pseudo- exponential implementation is approximated as (1) where (2) According to (2), it can approximate the exponential characteristic efficiently when the gain tuning range is smaller than 30 db. Fig. 2 shows the architecture of the proposed AGC amplifier where and denotes the gain of the power detector and the transconductance of the operational transconductance amplifier (OTA), respectively. The proposed AGC amplifier consists of two cascaded VGAs, a power detector, an OTA, an /$ IEEE

2 WANG AND LIU: m CMOS 1.25-GBPS AGC AMPLIFIER 137 Both the proposed VGA1 and VGA2 utilize the source-coupled pair with source degeneration. To adjust the gate voltages and of the triode pmos devices and, respectively, their gains can be changeable. The voltage gain of VGA1 can be expressed as (6) Fig. 3. The whole VGA. where and are the transconductance and output resistance of the transistor, respectively, and off-chip capacitor and a single-to-differential converter. Two cascaded VGAs realize the pseudo-exponential characteristic to make this AGC amplifier to have a constant settling time. The power detector converts the amplitude of the output signal into a signal to compare with the reference voltage. The OTA and the off-chip capacitor act as an integrator to integrate the error between the output of the power detector and the reference voltage. The outputs of the single-to-differential converter adjust the gain of two cascaded VGAs. To have a the pseudo-exponential characteristic, the voltage gain characteristics of two cascaded VGAs, VGA1 and VGA2, can be expressed as and (3a) (3b) The whole voltage gain characteristic of the cascaded VGAs becomes (4) According to (2) and (4), the cascaded VGAs realize the voltage gain with the pseudo-exponential characteristic as and where is the threshold voltage of the pmos devices, and in Fig. 3. Similarly, the voltage gain of VGA2 can be expressed as where and are the transconductance and output resistance of the transistor, respectively, and (7) (8) (9) (10) Suppose that one makes larger than. Usually, and are larger than 1, and also that is larger than and, then the whole voltage gain of two cascaded VGAs can be expressed as (11) (5) Substituting (7) and (10) into (11), then the gain of cascaded VGA is III. CIRCUIT DESCRIPTION A. Two-Cascaded VGAs In this work, two cascaded VGAs are shown in Fig. 3. The first VGA (VGA1) and the second one (VGA2) realize the function of (3a) and (3b), respectively. The pmos devices are chosen as the input of VGA1 for lower noise considerations. For VGA2, the nmos devices are realized for a smaller input capacitance. Their common-mode voltages are balanced and decoupled by connecting the sources of M2 and M4 to the MOS capacitor, M0. The inputs of the VGA1 are terminated with the resistors of 50,, for impedance matching. The input dc level is 0.6 V. (12) where and. Similarly, based on (4) and (5), (12) can be rewritten as (13) It reveals that this proposed VGA realizes the pseudo-exponential gain characteristic. The VGA s gain tuning range is proportional to (12), when the transistors are in triode region. Once the transistors are out of the triode region, their resistance between

3 138 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 Fig. 4. Power detector, OTA and the single-to-differential converter. the drain and source become larger, so that VGA gain fixed and it is independent of VGA dynamic range and common voltage. Assume that the proposed VGA is a one-pole system. Thus, the VGA bandwidth is dominated by this pole at output node. If the loading capacitance is at output node, this pole is given as (14) When is increased, the gain is increased and is reduced. It results in the reduced bandwidth. Therefore, when the amplitude of input signal is small, it requires a higher voltage gain and leads to a narrower bandwidth. B. Remaining Circuits In our AGC amplifier, the remaining circuits including a power detector, an OTA, and a single-to-differential converter are shown in Fig. 4. The power detector is realized by an analog multiplier, which consists of. This multiplier will generate the output, which is proportional to the square of the input signal amplitude. The capacitor will filter out the high frequency terms. Therefore, the output of the power detector subtracts with the reference voltage by the OTA, which consists of. For the sake of the linearity, the OTA is realized by a source-coupled pair, and, with source degeneration. Another source-coupled pair, and, provides the negative transconductance to improve the linearity further. The integrator is implemented by an off-chip capacitor of 10 uf to have the unity gain frequency of 100 khz. It will result in this proposed AGC amplifier to have a natural frequency about 100 khz for wide bandwidth operation. The output of the OTA is converted by the single-to- differential converter to realize two controlling voltages to adjust the gains of VGA1 and VGA2, respectively. The controlling voltages are and, respectively. The range of is 0.2 V and it insures the MOS devices, and, in the triode region in Fig. 3. is equal to 0.6 V by using a resistor,,of 8k and a dc current source of 150 ua. This converter does not require a high gain, but high linearity. In Fig. 4, the source-coupled pair, and, and the common source amplifier,, with source degeneration are adopted. To have a unity gain for this single-to-differential converter, is equal to. Fig. 5. Die photo. According to [6], the proposed AGC amplifier in Fig. 2 has a high-pass response from the input to the output with a time constant. This time constant is (15) where is the gain of the two cascaded VGAs, and is the transconductance of the OTA. Substituting (13) into (15), the time constant is calculated as (16) Assumed that is designed about 2 A/V, this time constant is calculated as 1.6 s for this proposed AGC amplifier. Finally, to drive the instrument with 50, the output buffer is realized by a nmos with the open drain. IV. EXPERIMENTAL RESULTS The proposed AGC amplifier has been fabricated in m CMOS process and packaged in an 18-pin ceramic package. Fig. 5 shows the die photo. The total chip area occupies 0.82 mm 0.56 mm included the I/O pads with electrostatic discharge (ESD) protection and the core area is mm mm without I/O pads and ESD.

4 WANG AND LIU: m CMOS 1.25-GBPS AGC AMPLIFIER 139 Fig. 6. Measured VGA s characteristic. Fig. 9. Measured transient response of this AGC amplifier. Fig. 7. Measured VGA s group delay response. Fig. 10. Measured eye diagram for a PRBS of 1.25 Gbps. Fig. 8. Group delay versus control voltage. The measured power consumption of this AGC amplifier is 43.2 mw with single power supply of 1.8 V. The measured gain control characteristic of two cascaded VGAs is shown in Fig. 6. The gain control voltage at the node Y in Fig. 4 is swept from 0.4 to 1.2 V. When the control voltage sweeps from 0.4 to 1.2 V, the whole VGA has 28.5-dB gain tuning range from 10 to 18.5 db and the gain control characteristic is linear-in-decibels scale. The group delay response is measured by using Agilent E8358A PNA series network analyzer. The measurement sweeps input signal frequency from 300 khz to 5 GHz with different gain control voltages. The measurement result is given in Fig. 7. Fig. 8 shows the group delay versus the control voltage for the VGA. The averaged group delay is from 12.1 ns to ns in the gain tuning range. The transient response of this AGC amplifier is measured by using Tektronix AWG710 arbitrary waveform generator and sampling oscilloscope TDS 680. A 12-MHz 550-mV sine wave is modulated with the square wave of 100 khz as the input Fig. 11. Measured jitter performance. of this AGC amplifier. The output signal (100 mv/div) and the gain control voltage (500 mv/div) of this AGC amplifier are shown in the upper trace and the lower trace of Fig. 9, respectively, where the horizontal axis is 500 ns/div. It shows the settling time is 1.6 s. The single-ended output eye diagram of this AGC amplifier is measured by using Agilent N4901A pattern generator and 86100C sampling oscilloscope on a single-ended output. Fig. 10 shows the measured eye diagram of pseudorandom bit sequence (PRBS) of 1.25 Gbps. The measured peak-to-peak and RMS jitters are 28 and 19.4 ps, respectively. The jitter histogram with and without the gain control loop is shown in Fig. 11 for the pattern of PRBS from to.

5 140 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 TABLE I PERFORMANCE SUMMARIES REFERENCES Fig. 12. Member BER versus the input signal amplitude. Fig. 12 shows the measured BER versus the input signal amplitude. When the output is set at 200 mv, the minimum input sensitivity is 25 mv when BER is smaller than, and the input overload amplitude is 430 mv when BER is smaller than. It reveals that this AGC amplifier achieves an input dynamic range of 24.7 db. The measured performance summaries are given in Table I. V. CONCLUSION In this work, a 1.25-Gbps AGC amplifier with constant settling time for EPON application is presented. A new AGC amplifier topology for constant settling time is proposed. In this AGC amplifier, two cascaded VGAs are proposed to realize the pseudo-exponential gain characteristic. The chip has been fabricated in a single poly six metal m CMOS process. The proposed two cascaded VGAs achieve ns group delay and 28.5-dB linear-in-decibels gain tuning range. The proposed AGC amplifier can operate with data rate exceeds 1.25 Gbps and a 24.7-dB input dynamic range. ACKNOWLEDGMENT The authors thank National Science Council (NSC) and National Chip Implementation Center (CIC) in Taiwan for chip support and implementation of this work, respectively. [1] IEEE Std ah for Information Technology Telecommunications and Information Exchange Between Systems Local and Metropolitan Area Network-Specific Requirements Part 3, IEEE Std ah, Jul [2] Q. Le, S. G. Lee, Y. H. Oh, H. Y. Kang, and T. H. Yoo, A burstmode receiver for 1.25-Gb/s Ethernet PON with AGC and internally created reset signal, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [3] C. K. Wang and P. C. Huang, An automatic gain control architecture for SONET OC-3 VLSI, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 9, pp , Sep [4] P. C. Huang, C. Y. Huang, and C. K. Wang, A 155-MHz BiCMOS automatic gain control amplifier, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 5, pp , May [5] H. Ikeda, T. Ohshima, M. Tsunotani, T. Ichioka, and T. Kimura, An auto-gain control transimpedance amplifier with low noise and wide input dynamic range for 10-Gb/s optical communication systems, IEEE J. Solid-State Circuits, vol. 36, no. 9, pp , Sep [6] J. M. Khoury, On the design of constant settling time automatic gain control circuits, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp , Mar [7] T. W. Pan and A. A. Abidi, A 50-MHz variable gain amplifier for magnetic data storage systems, IEEE J. Solid-State Circuits, vol. 24, no. 4, pp , Jun [8] P. C. Huang, L. Y. Chiou, and C. K. Wang, A 3.3 V CMOS wideband exponential control variable gain amplifier, in Proc. IEEE Int. Symp. Circuits Syst., Jun. 1998, vol. 1, pp [9] A. Motamed, C. Hwang, and M. Ismail, CMOS exponential current-to-voltage converter, Electron. Lett., vol. 33, no. 12, pp , Jun [10] R. Harjani, A low-power CMOS VGA for 50 Mb/s disk drive read channels, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, pp , Jun [11] Q. H. Duong, Q. Le, C. W. Kim, and S. G. Lee, A 95-dB linear low-power variable gain amplifier, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 8, pp , Aug [12] C. C. Lin, M. T. Shieu, and C. K. Wang, A dual-loop automatic gain control for infrared communication system, in Proc. IEEE Asia-Pacific Conf., Aug. 2002, pp [13] O. Jeon, R. M. Fox, and B. A. Myers, Analog AGC circuitry for a CMOS WLAN receiver, IEEE J. Solid-State Circuits, vol. 41, no. 10, pp , Oct