A 1.5 Gbps Transceiver Chipset in 0.13-mm CMOS for Serial Digital Interface

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, 2017 ISSN(Print) ISSN(Online) A 1.5 Gbps Transceiver Chipset in 0.13-mm CMOS for Serial Digital Interface Kyungmin Lee, Seung-Hoon Kim, and Sung Min Park Abstract This paper presents a transceiver chipset realized in a 0.13-mm CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 db in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mw from 1.2/3.3-V supplies and occupies the area of mm 2, whereas the RX dissipate 133 mw from a 1.2-V supply and occupies the area of 1.44 mm 2. Index Terms CMOS, digital interface, equalization, pre-emphasis, receiver, serial links, transmitter Particularly, the latter may result in severe inter-symbolinterference(isi) and degraded bit-error-rate(ber) during the parallel data transmission. Hence, circuit designers should make efforts not only to avoid these issues, but also to extend the distance of data communication. On the contrary, serial digital interface needs much less number of I/O pins and thus provides advantages of the improved BER due to the mitigated skew and crosstalk between channels. However, considerable signal attenuation cannot be avoided because of the rapid increase of data rate through the channel. In order to compensate the severe signal attenuation, either preemphasis or equalization can be applied at transmitter(tx) or at receiver(rx), respectively [2, 3]. Fig. 1 shows a typical serial digital link with front-end analog circuits, where the TX consists of a N:1 MUX, a retimer with a PLL, and a main driver with pre-emphasis. The RX comprises an equalizer, a clock and data recovery(cdr), and a 1:N DEMUX. I. INTRODUCTION Parallel digital interface has been attractive in the applications of multimedia data transmission systems [1]. However, it inevitably requires more I/O pins, which leads to undesirable cost increase. Also, it gives rise to a number of signal distortion issues, such as skew problems when data and clock are transmitted simultaneously, and crosstalk issues between adjacent channels when multi-channel data are transmitted. Manuscript received Apr. 26, 2017; accepted Jul. 11, 2017 Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, Korea kmrhee13@gmail.com, smpark@ewha.ac.kr Fig. 1. Example of a typical serial digital link.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, Fig. 2. Block diagrams of the proposed TX, the proposed RX. This paper presents a transceiver chipset realized in a 0.13-mm CMOS technology which can compensate the significant cable loss of 45 db at the operation speed of 1.5 Gbps via a low-cost 180-meter coaxial cable. Section II describes the block diagrams of the proposed TX and RX chips along with its schematic diagrams in detail. Section III demonstrates the measured results of the transceiver chipset to confirm the proposed circuit design. Then, the conclusion is followed in Section IV. II. CIRCUIT DESCRIPTION The architecture of the proposed TX is shown in Fig. 2, where an 8:1 MUX is utilized as a serializer with a PLL as a clock generator. The PLL is designed to operate at a wide frequency range of 270 MHz ~ 1.5 GHz, where two reference clocks(i.e. 27/75 MHz) are exploited for alleviating the design burden. The main driver utilizes the wide-range PLL clocks to generate pre-emphasis at the output signals. It should be noted that only one coaxial cable is utilized as a transmission medium, and therefore another output node of the TX driver should be 75-Ω terminated for impedance matching. Fig. 2 shows the block diagram of the proposed RX, where two continuous-time linear equalizers(eqs) and a limiting amplifier(la) are employed as a front-end circuit to boost weak signals occurred in a long 180- meter coaxial cable. Then, a 1/8-rate CDR is followed to recover the clocks and retime the data with no need of an additional 1:8 DEMUX for low power operations. 1. Transmitter Circuit Fig. 3. Block diagram of the TX front-end circuit in detail, a timing diagram to explain the pre-emphasis operations. Fig. 3 shows the block diagram of the proposed TX front-end circuit, which consists of an input buffer, a preamplifier, a D-FF, and a driver with a coaxial cable. The pre-emphasis function is realized at the main driver to compensate the significant cable loss by comparing the original incoming bit sequence with the delayed bit at the output of the D-FF. Therefore, it emphasizes the rising and falling edges of each bit, as shown in Fig. 3. An example of the pre-emphasis operations is depicted, where the equations corresponding to the rising edges of each bit are described in (1) ~ (4). Fig. 4 shows the block diagram of the PLL circuit, in which the divided clocks are generated in the fashion suggested in Fig. 4. As an example, when the VCO generates 1.5 GHz clock signal, 750 MHz clock can be

3 554 KYUNGMIN LEE et al : A 1.5 GBPS TRANSCEIVER CHIPSET IN 0.13-mM CMOS FOR SERIAL DIGITAL INTERFACE Fig. 4. Block diagrams of the PLL circuit, the proposed mechanism of the divided clocks. generated by the utilized frequency divider. By the same principle, a 270 MHz clock can be generated from a 540 MHz clock signal. Therefore, the VCO will have to generate 1.5 GHz and 540 MHz clock signals only, which alleviates the design burden of a wide tuningrange VCO. Each of two generated frequencies is selected by V0. In Fig. 4, POUT and MOUT represent the differential outputs of the VCO, while CK and CKB are the divided clocks to control other circuitry including MUX and the front-end circuits. Switches (S00, S11 and S21) in Fig. 4 are controlled by I 2 C circuit inside the TX chip (which was not shown in the figure). These will select the path and hence the desired clock frequencies. Fig. 5 depicts the post-layout simulation results of the proposed TX. Fig. 5 represents the simulated differential eye-diagrams at the output of the main driver when a 180-meter coaxial cable is disconnected and the pre-emphasis function is turned-off. It is clearly seen that the output voltage levels of larger than 1.0 V are obtained even at 1.5 Gb/s. These values validate the usage of this TX even for the applications of HDMI cables. Fig. 5 shows the output eye-diagrams of the main driver with the pre-emphasis turned-on, where the pre-emphasis of the waveforms is clearly visible with 4-levels of amplitudes. Fig. 6 shows the output eye-diagrams after passing a 180-meter coaxial cable. Even at 1.5 Gbps, the voltage levels of the eye-diagrams are about 8 mv pp. Since the RX in this work includes two equalizers and a CDR Fig. 5. Post-layout eye-diagrams of the proposed TX with the pre-emphasis off, with the pre-emphasis on.

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, Fig. 6. Post-layout eye-diagrams after passing a 180-meter coaxial cable. circuit to enable to recover as weak signals as 5 mv pp. Hence, it confirms the validity of this TX for high-speed video data transmission via a low-cost 180-meter coaxial cable. 2. Receiver Circuit The proposed RX consists of two EQs, a LA, and a 1/8-rate clock-data recovery(cdr) circuit (as shown in Fig. 2). Fig. 7 shows the schematic diagram of the continuous time linear equalizer(ctle) where a twostage equalizer is exploited with capacitor arrays to control gain peaking and zero frequency. Two-stage LA, as shown in Fig. 7, employs negative capacitance at each gain-cell to cancel the parasitic capacitance for wide bandwidth. Also, DCoffset voltage cancellation is utilized in the LA to acquire the DC-voltage balance at the outputs. A CML differential pair is used at both the input and output buffers. Fig. 8 shows the schematic diagram of the proposed CDR. It enables to recover clocks, retime the incoming data, and automatically demultiplex the high-frequency data to 1-to-8 digital NRZ signals. The CDR consists of a 1/8-rate linear phase detector, a voltage-to-current(v-i) converter, a 2 nd -order filter, and a four-stage differential ring-oscillator with 5-bit coarse tuning switches. The CDR circuit exploits the 1/8-rate architecture to realize small chip area and low DC power consumption [6]. It is optimized to enable continuous operations from 135 Mbps to 1.5 Gbps, in which any desired bit-rate can be easily selected by the variation of the control voltage levels in the ring VCO. Fig. 7. Schematic diagrams of CTLE, LA. Fig. 9 depicts the post-layout simulation results of eyediagrams at the differential outputs of the front-end circuit(ctle+la). It is clearly seen that the output voltage levels of 560 mv pp are obtained at the output of

5 556 KYUNGMIN LEE et al : A 1.5 GBPS TRANSCEIVER CHIPSET IN 0.13-mM CMOS FOR SERIAL DIGITAL INTERFACE Fig. 10. Post-layout eye-diagrams of the 1:8 demuxed output at the CDR. Fig. 8. CDR architecture, block diagram of the 1/8-rate phase detector. Fig. 11. Chip photos of the proposed TX and RX. Fig. 9. Post-layout differential output eye-diagrams of the RX(EQ+LA). LA, which is enough to drive the following CDR circuit. Fig. 10 shows the 1:8 demultiplexed data outputs of the CDR circuit for 1.5 Gbps PRBS inputs, confirming the validity of the proposed RX. III. MEASURED RESULTS Fig. 12. Photograph of a coaxial cable with BNC connectors, its measured S21 parameter(cable attenuation) of a 180-meter cable. Test chips of the proposed TX and RX circuits were implemented by using a 0.13-mm CMOS process. Fig. 11 shows the chip microphotographs, where the proposed TX and RX occupies the chip area of mm 2 and 1.44 mm 2, respectively. Fig. 12 shows the photograph of a 180-meter coaxial cable with BNC connectors and its measured S- parameter(s21) by using Agilent N5071C network analyzer, where it is clearly seen that the signal loss reaches 45 db at 1.5 GHz.

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, Fig. 13. Measured TX eye-diagrams (single-ended) at 270/540/750/1500 Mb/s with the pre-emphasis turned-off, turned-on. 1. Transmitter Measurements Fig. 13 demonstrates the measured eye-diagrams of the proposed TX with the coaxial cable at one side of the TX output and a 50-Ω termination at the other side. The eye-diagrams are measured when the preemphasis is either turned-off or turned-on, by utilizing Anritsu MP1775A pulse pattern generator and Agilent 86100D digital communication analyzer. It is clearly seen that the pre-emphasis function is operating from 270 Mbps to 1.5 Gbps with four levels at each bit rate. The output voltage levels with no preemphasis are measured to be about 370 mv pp which is mainly due to the single-ended measurement with a 50-Ω termination. Still, there exist a discrepancy from the postlayout simulation results of 1.1 V pp, which may be attributed to the impedance mismatch between the 180- meter cable and the PCB trace.

7 558 KYUNGMIN LEE et al : A 1.5 GBPS TRANSCEIVER CHIPSET IN 0.13-mM CMOS FOR SERIAL DIGITAL INTERFACE Fig. 14. Measured eye-diagrams of the RX output voltages (single-ended with 50-Ω termination) of EQ+LA, CDR data & clocks. DC measurements reveal that the TX chip consumes 104 mw from 1.2/3.3-V supplies. 2. Receiver Measurements Fig. 14 demonstrates the measured eye-diagrams of the CTLE+LA circuitry with the coaxial cable connected, where the output voltage levels are measured to be 138 mv pp at 1.5 Gbps. The output voltage levels were measured at a single-ended with 50-Ω termination, and therefore, the differential voltage outputs would be two times higher, i.e. 550 mv pp which is similar to the postlayout simulation results. Fig. 14 shows the measured eye-diagrams of the whole RX (i.e., CTLE+LA+CDR) at Gbps with the camera data inputs, and the recovered clocks from the CDR. The reduced voltage levels of 98 mv pp at the CDR output may be attributed to the output buffer of the CDR circuit in which the switching currents becomes much smaller than anticipated.

8 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.4, AUGUST, Table 1. Performance summary and comparison of the proposed TX and RX chipset Parameter [2] [8] This work CMOS Technology (nm) Data rate (Gbps) Max. cable loss (db) TX output voltage max. data rate (mv pp) * Supply voltage (V) / 3.3 Power Consumption (mw) ** 237 Chip Area (mm 2 ) * Pre-emphasis off. ** 0.5-V supply 2 Gbps. DC measurements reveal that the total RX chip dissipates 133 mw from a single 1.2-V supply. IV. CONCLUSIONS We have presented a 270/540/750/1500-Mbps TX and RX chipset implemented in a 0.13-mm CMOS technology for the applications of serial digital interface to realize high-speed video data transmission via a lowcost 180-meter coaxial cable. To compensate the significant cable loss of 45 db, a pre-emphasis driver with a D-FF and two-stage continuous-time linear EQs are exploited in the transceiver chipset. Particularly, the CDR takes the configuration of 1/8-rate architecture for small chip size and low power consumption. With the camera input data, the proposed TX and RX chipset recovers data and clocks even at the operation speed of 1.5 Gbps. Table 1 summarizes the performance comparison of the proposed TX and RX chips, which shows a potential for a low-power solution in the applications of long-distance video data transmission with low-cost coaxial cables. ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(msip) (No. NRF-2014R1A2A2A ). REFERENCES [1] K. D. Hwang and L. S. Kim, A 5 Gbps 1.6 mw/g bps/ch Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single- Ended Parallel Interface, IEEE Tran. on Circ. and Sys. I, Vol. 61, No. 10, pp , Oct [2] H. Higashi, et al, Gbps 12 channel Transceiver with Pre-emphasis and Equalizer, Technical Digest of IEEE Symp. on VLSI Circuits, pp , Jun [3] S. W. Choi, H. B. Lee and H. J. Park, A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current Mode Implementation, IEEE J. of Solid-State Circuits, Vol. 41, No. 3, pp , Mar., [4] S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation, IEEE J. of Solid-State Circuits, Vol. 48, No. 5, pp , May [5] D. Park and S. Cho, A 14.2 mw 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 mm CMOS, IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp , Dec [6] S. Soliman, F. Yuan, K. Raahemifar, An overview of design techniques for CMOS phase detectors, IEEE Int. Symp. on Circ. and Sys., Vol. 5 pp , May [7] J. S. Choi, A 0.18um CMOS 3.5-Gb/s Continuoustime Adaptive Cable Equalizer Using Enhanced Low- Frequency Gain Method, IEEE J. of Solid-State Circuits, Vol. 39, pp , Mar [8] W.-S. Choi et al., A 0.45-to-0.7V 1-to-6Gb/s to-0.58pj/b Source-Synchronous Transceiver Using Automatic Phase Calibration in 65nm CMOS, Technical Digest of IEEE ISSCC, pp , Kyungmin Lee received the B.S. and M.S. degree in electronics engineering from the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea, in 2014 and 2016, respectively. She is currently pursuing the Ph.D. degree in the Department of Electronic and Electrical Engineering at Ewha Womans University. Her research interests include high-speed analog integrated circuit designs.

9 560 KYUNGMIN LEE et al : A 1.5 GBPS TRANSCEIVER CHIPSET IN 0.13-mM CMOS FOR SERIAL DIGITAL INTERFACE Seung Hoon Kim received the B.S., M.S., and Ph.D. degree in the Department of Electronic and Electrical Engineering from Ulsan University, Korea, in 2006, 2008 and 2015, respectively. He is currently a Postdoctoral Researcher at the Department of Electronics Eng. at Ewha Womans University. His research interests include high-speed analog CMOS circuit designs for the applications of digital optical interfaces, Silicon photonics, backplanes, etc. Sung Min Park received the B.S. degree in electrical and electronic engineering from KAIST, Korea, in He received the M.S. degree in electrical engineering from University College London, U.K., in 1994, and the Ph.D. degree in electrical and electronic engineering from Imperial College London, U.K., in May In 2004, he joined the faculty of the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea, where he is currently a full Professor. His research interests include high-speed analog/digital integrated circuit designs in submicron CMOS and SiGe HBT technologies for the applications of optical interconnects, silicon photonics, and RF communications. Prof. Park has served on the technical program committees of a number of international conferences including ISSCC ( ) and A-SSCC ( ).