Technical Data IFD IFD-53110

Transcription

1 Silicon Bipolar MMIC 3.5 and 5.5 GHz Divide-by- Static Prescalers Technical Data IFD-53 IFD-53 Features Wide Operating Frequency Range: IFD-53:.5 to 5.5 GHz IFD-53:.5 to 3.5 GHz Low Phase Noise: -3 khz Offset Output Power: -5 dbm Typ. Single Supply Voltage V cc = 5 V or V ee = -5 V On-Chip Terminations Provide Good Input and Output VSWRs Hermetic Gold-Ceramic Surface Mount Package mil Stripline Package Description Hewlett-Packard's IFD-53 and IFD-53 are low phase noise silicon bipolar static digital frequency dividers using two scaled Emitter-Coupled-Logic (ECL) master-slave D flip-flops and buffer amplifiers. They are housed in hermetic high reliability surface mount packages suitable for commercial, industrial, and Pin Configuration military applications. Typical 3 V EE applications include stabilized or digitally controlled local oscillators for GPS, SATCOM or military receivers, and frequency synthesizers and counters in instrumentation systems. The IFD-53 is a lower cost selected version of the IFD-53, and is distinguished by a reduced V operating frequency range. Functional Block Diagram V C Q C Q C Q C Q 3 V EE The IFD series of frequency dividers is fabricated using Hewlett-Packard's 8 GHz, f t, ISOSAT - silicon bipolar process which uses nitride selfalignment, submicrometer lithography, trench isolation, ionimplantation, gold metallization and polyimide intermetal dielectric and scratch protection to achieve excellent device uniformity, performance, and reliability E

2 Absolute Maximum Ratings Symbol Parameter Units Absolute Maximum [] V cc - V ee Device Voltage V 8 P diss Power Dissipation [,3] mw 65 P in RF Input Power dbm +5 T j Junction Temperature C T STG Storage Temperature C -65 to + Thermal Resistance [] : θ jc = 7 C/W Notes:, Operation of this device above any one of these parameters may cause permanent damage.. T case = 5 C. 3. Derate at 9.3 mw/ C for T C 3 C. Guaranteed Electrical Specifications, IFD-53 and IFD-53 T A = 5 C, Z O = 5 Ω, V cc - V ee = 5. V Symbol Parameters and Test Conditions Units Min. Typ. Max. IFD-53: F MAX Maximum Clock Frequency P in = - dbm ( mvpp) GHz IFD-53: F MAX Maximum Clock Frequency P in = - dbm ( mvpp) GHz I IFD-53 and IFD-53: Supply Current ma Typical Design Information, T A = 5 C, Z = 5 Ω, V cc - V ee = 5. V, P in = - dbm. All values apply to both IFD-53 and IFD-53. f test is 5 GHz for IFD-53 and 3 GHz for IFD-53 (unless otherwise noted). Symbol Parameters and Test Conditions Units Value F MIN Minimum Clock Frequency [] MHz 5 P in Input Sensitivity f = f test dbm - mvpp 5 P out Output Power f =.5 to f test dbm -5 mvpp 355 VSWR Input VSWR f =.5 to f test.: Output VSWR f =.5 to f test.5: PN SSB Phase Noise f = 3 GHz, khz offset dbc/hz -3 f = 5 GHz, khz offset (IFD-53 only) -38 T r Output Rise Time, % - 8% f = f test psec 5 T f Output Fall Time, % - 8% f = f test psec 85 Note:. Minimum clock frequency when driven from a sinusoidal input. Operation to lower frequencies is possible when using input signals with faster rise times, such as occurs in the case of a cascade of two or more IFDs. 7-5

3 Typical Performance, T A = 5 C, Z O = 5 Ω, V cc - V ee = 5. V Graphs apply to both IFD-53 and IFD-53 (unless otherwise noted) IFD-53 & IFD-53 IFD IFD-53 & IFD-53 IFD C C 5 C Figure. Input Sensitivity vs. Input Frequency and Recommended Operating Ranges for Nominal Operating Conditions (T = 5 C, V cc - V ee = 5 V) Figure. Input Sensitivity vs. Input Frequency and Recommended Operating Ranges for Worst Case Operating Conditions (-55 C < T < 5 C and.5 V < V cc - V ee < 5.5 V Figure 3. Input Sensitivity vs. Input Frequency and Temperature (V cc - V ee = 5 V). 7 I (ma) C + 5 C - 55 C VSWR 3: : OUTPUT INPUT OUTPUT LEVEL (dbm) V 5. V.5 V : -8 V -V EE (V) FREQUENCY (MHz) FREQUENCY (MHz) Figure. Device Current vs. Voltage and Temperature. Figure 5. Input and Output VSWR vs. Frequency. Figure 6. Output Power Level vs. Input Frequency and V cc - V ee V in SSB PHASE NOISE (dbc/hz) GHz (IFD-53) TO GHz (IFD-53 & IFD-53) -6 khz MHz OFFSET FREQUENCY V in (mv) - Vout TIME (psec) - V out (mv) Figure 7. SSB Phase Noise vs. Offset Frequency, and Input Frequency. Figure 8. IFD-53 Typical Output Response with 5 GHz Input. 7-53

4 BLOCKING CAPACITORS ARE pf TYP. BYPASS CAPACITORS ARE 7 nf min. BLOCKING CAPACITORS MAY BE OMITTED IF GENERATOR AND LOAD ARE AT V LEVEL. TRANSMISSION LINES ARE 5. V EE = -5. V 3 C BY (7 nf min.) F (5 ) V F/ (5 ) SWINGS BETWEEN V AND V -36 mv PIN: V = V Figure 9. Typical ECL Biasing Configuration, IFD-53 and IFD-53. BLOCKING CAPACITORS ARE pf TYP. BYPASS CAPACITOR SHOULD BE 7 nf min. TO ENSURE GOOD SENSITIVITY PERFORMANCE. TRANSMISSION LINES ARE 5. V EE = V PIN: 3 F (5 ) F/ (5 ) V = 5. V C BY (7 nf min.) Figure. Typical RF Biasing Configuration, IFD-53 and IFD-53. LO OUTPUT DIV. BY PROGRAMMABLE DIVIDER VCO PHASE DETECTOR AFC LPF STABLE REFERENCE Figure. Typical Stabilized LO Configuration, IFD-53 and IFD

5 O 5 TEST SYSTEM Z O = 5 PIN: 3 V = -5. V EE db db SPECTRUM ANALYZER GENERATOR OUTPUT: FREQUENCY = f LEVEL = P in + db (INTO 5 LOAD) P OUT f/ Z in = 5 V = V Figure. Sensitivity Test Configuration, IFD-53 and IFD-53. Package Dimensions mil Stripline Package. (.).5 (.) 3. ±.5 (. ±.).5 (.) NOTES: (unless otherwise specified). DIMENSIONS ARE IN mm (INCHES). TOLERANCES: in.xxx = ±.5 mm.xx = ±.3.76 (.3).57 ±.76 (.95 ±.3) 7-55