cfl Copyright 2000 by Hamid R. Rategh All Rights Reserved ii

Transcription

1 LOW POWER CMOS FREQUENCY DIVISION AND SYNTHESIS AT MULTI GHZ FREQUENCIES A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Hamid R. Rategh May 2001

2 cfl Copyright 2000 by Hamid R. Rategh All Rights Reserved ii

3 I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. T.H. Lee (Principal Adviser) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. B.A. Wooley I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. D.C. Cox Approved for the University Committee on Graduate Studies: iii

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5 Abstract I N the past 10 years extensive effort has been dedicated to commercial wireless local area network (WLAN) systems. Despite all these efforts, however, none of the existing systems has been successful, mainly due to their low data rates. The increasing demand for WLAN systems that can support data rates in excess of 20 Mb/s enticed the FCC to create an unlicensed national information infrastructure (U NII) band at 5 GHz. This frequency band provides 300 MHz of spectrum in two segments: a 200 MHz ( GHz) and a 100 MHz ( GHz) frequency band. This newly released spectrum, and the fast trend of CMOS scaling, provide an opportunity to design WLAN systems with high data rate and low cost. One of the existing standards at 5 GHz is the European high performance radio LAN (HIPERLAN) standard which supports data rates as high as 20 Mb/s. One of the main building blocks of each wireless system is the frequency synthesizer. Phase locked loops (PLLs) are universally used to design radio frequency synthesizers. Reducing the power consumption of the frequency dividers of a PLL has always been a challenge. In this dissertation, we introduce an alternative solution for conventional flipflop based frequency dividers. An injection locked frequency divider (ILFD) takes advantage of the narrowband nature of the wireless systems and employs resonators to trade off bandwidth for power. We have designed a fully integrated CMOS PLL based frequency synthesizer for a 5 GHz WLAN receiver which is compatible with the HIPERLAN standard. In this design we have used an ILFD as the first divider in the feedback path of the PLL to reduce the overall power consumption. The on chip spiral inductors of the voltage controlled oscillator (VCO) are optimized to reduce the power consumption and to v

6 improve the phase noise performance at the same time. The on chip inductors of the ILFD are also optimized for wide locking range and low power consumption. The synthesizer consumes 21.6 mw, of which less than 1 mw is consumed by the ILFD. The phase noise of the synthesizer is less than -134 dbc/hz at 22 MHz offset frequency, and all spurious tones are at least 70 db below the carrier. vi

7 Acknowledgments WOULD like toacknowledge the contribution of many people and organizations Iwho helped me throughout my education at Stanford. I would like to express my deepest gratitude to my advisor, Professor Thomas H. Lee, who has been a constant source of encouragement and support. He gave me the time, space and all the resources required to explore different ideas and I am really thankful for that. I also like to thank my co advisor, Professor Bruce A. Wooley, who has supported me in many ways since my first day at Stanford. My sincere thanks to Professor Donald C. Cox with whom I had the privilege to work as a teaching assistant during my first quarter at Stanford. I have benefited ever since from his intellectual and friendly advice. Also my acknowledgments to Professor Umran Inan who chaired my Ph.D. orals committee. By being part of the Stanford Microwave IntegRated Circuit (SMIrC) lab, I not only enjoyed Professor Lee's supervision but also benefited from the company of many other smart and wonderful friends: Ali, Arjang, Arvin, Dave, Derek, Hirad, Joel, Kare, Kevin, Mar, Mohan, Ömer, Rafael, Ramin, Sergei, Shwe, Talal, Tamara, and Ulrich. I would like to specifically acknowledge my friend and project mate Hirad Samavati, from whom I learned a great deal during our joint project SU- PERNET. I also learned from my discussions with students from research groups of Professors Horowitz, Wooley, and Wong. Ann Guerra deserves special thanks. Although she always says that she is just doing her job," but she always goes far out of her way to help students. I am grateful to her for having helped me any time I asked. I was fortunate to be among the first group of students who received a Stanford Graduate Fellowship (SGF). I would like to thank the SGF organizers and sponsors vii

8 for their financial support. I would also like to acknowledge National Semiconductor, and specifically Tom Redfern, for providing Stanford with the free fabrication services which allowed me to fabricate my design in a leading edge CMOS technology. I also thank Dr. Chris Hull, Fredrick Stubbe, and Julian Tham who were my mentors while I was an intern at Rockwell Semiconductor. I would also like to acknowledge Tektronix, and specifically Jack Hurt, for supporting us with their excellent simulation tool, ADS. My friends, Ali Khalili, Ali Kiaei, Ali Mazouchi, Ali Shirvani, Ali Tabatabaei, Amir Ghazanfarian, Azam Monifi, Azita Emami, Babak Khalaj, Farid Nemati, Farzan Fallah, Fati Jalayer, Hamid Aghajan, Hamid Fahimi, Kambiz Kaviani, Koohyar Minoo, Mahmood Reza Kasnavi, Maryam Fazel, Mehdi Soltan, Mina Komeilian, Nader Shamma, Rasool Khadem, Samira Habibian, Shahram Abdollahi, and... made my life at Stanford awonderful experience and I thank them all. I find myself in great debt to my parents, as well as my brothers and sisters, for their unconditional love and support. I am also thankful to my in laws who have been supportive and understanding from the first day. Finally I thank my wonderful wife, Leili, whose love encouraged me to work harder and whose patience gave me the power to overcome all difficulties. I dedicate this work to my parents and my wife. viii

9 Contents Abstract Acknowledgments List Of Tables List Of Figures v vii xi xiii 1 Introduction Organization Wireless Local Area Networks Wireless LAN standards Wireless LAN transceivers Summary Frequency Synthesizers Phase locked loops Linearized PLL models First order PLL Second order PLL Third order PLL Fourth order PLL Noise in phase locked loops Conclusion Frequency Dividers Digital frequency dividers Analog frequency dividers Injection locked frequency dividers Model for injection locked frequency dividers ix

10 Divide by two ILFDs with third and fourth order nonlinear functions Tracking injection locked frequency dividers Noise in injection locked frequency dividers Summary Experimental injection locked frequency dividers Circuit topologies Measurement Results Single ended ILFD Differential ILFD Noise transfer function Summary An experimental 5GHz frequency synthesizer Proposed synthesizer architecture Synthesizer building blocks Voltage controlled oscillator Injection locked frequency divider Programmable frequency divider (ΞM) Phase/frequency detector Charge pump and Loop filter Measurement Results Conclusion Conclusion Future work Appendix A 2D Fourier series expansion of an ILFD nonlinear function Appendix B Input output phase difference in an ILFD Appendix C Polynomial approximation of an oscillator nonlinearity Appendix D On chip spiral inductors Bibliography 115 x

11 List Of Tables 2.1 First generation WLAN standards Summary of HIPERLAN/1 standard State transitions for the divide by 2/3 when Mc = DILFD performance summary Power consumption of fully integrated wireless receivers PLL parameters Measured synthesizer performance Performance comparison C.1 Polynomial coefficients of a BJT Collpits oscillator nonlinearity D.1 Definition of parameters xi

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13 List Of Figures 2.1 Network topologies. (a) Access point. (b) Ad hoc. (c) Multihop ad hoc U NII and HIPERLAN frequency bands Simplified picture of a wireless transceiver Block diagram of a typical heterodyne receiver Block diagram of a typical phase locked loop Signal to interference degradation due to LO spurious sidebands Signal to interference degradation due to LO phase noise Linearized PLL model Circuit realizations of the loop filter in a second order PLL Circuit realization of the loop filter in third order PLL Maximum phase margin as a function of C 1 =C 2 ratio in a third order PLL Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a third order PLL Normalized settling time to 10 ppm accuracy as a function of loop bandwidth in a third order PLL The magnitude of the input output phase transfer function at the reference frequency as a function of the loop bandwidth when the phase margin is 50 ffi Circuit implementation of the loop filter in a fourth order PLL Loop transmission Bode plot ofatypical fourth order PLL Maximum phase margin as a function of C 1 =(C 2 + C 3 ) Normalized settling time to 10 ppm accuracy as a function of loop bandwidth in a fourth order PLL Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a fourth order PLL xiii

14 3.17 Normalized magnitude of the input output phase transfer function of a fourth order PLL at the reference frequency as a function of the loop bandwidth (PM=50 ffi The linearized PLL model with noise added at the input and output Block diagram of a divide by two frequency divider (a) Block diagram of a divide by 2/3 frequency divider. (b) Block diagram of a master slave D flipflop State transitions in the divide by 2/3 when Mc = Schematic of the SCL D latch Input (Clk) and steady state output voltage (v o (t)) of the SCL D latch inavery high frequency divide by two frequency divider Normalized maximum operational frequency of the SCL latch in a divide by two frequency divider as a function of g m R (a) Regenerative frequency divider. (b) Parametric frequency divider Model for a free running oscillator Model for an injection locked frequency divider Tracking ILFD ILO model used for noise analysis Phasor representation of signals in Fig Noise transfer function of an ILO Schematic of the single ended ILFD Schematic of the differential ILFD a) Top view of a square planar spiral inductor. b) A ß circuit model for spiral inductors Die micrograph of the SILFD in a 0.5 μm CMOS technology (0:7mm 1mm, including pads) Input referred locking range of the SILFD as a function of incident amplitude Maximum input referred locking range of the SILFD as a function of bias current SILFD phase noise measurements Chip micrograph of the DILFD in a 0.24 μm CMOS technology (345 μm 540 μm) Tuning range of the free running voltage controlled DILFD Operational frequency range of the DILFD for different incident amplitudes and two different control voltages DILFD locking range and power consumption as a function of incident amplitude xiv

15 5.12 DILFD phase noise measurement setup DILFD phase noise measurements Sideband generation due to noise injection at an offset from the incident frequency Noise transfer function in the SILFD (P i = 40 dbm) Noise transfer function in the SILFD (P n = 70 dbm) Simplified block diagram of the front end of the U NII band WLAN receiver Block diagram of the proposed frequency synthesizer (a) Schematic of the quadrature VCO. (b) Representation of the quadrature VCO as a ring oscillator Schematic of the differential tracking ILFD, with dummy transistor M4 to provide a symmetric load for the differential VCO Block diagram of the pulse swallow frequency divider Block diagram of the program and pulse swallow counters Block diagram of the prescaler Timing diagram of the prescaler over one output cycle when it divides by Circuit implementation of the NOR/flipflop of the dual modulus divider in the prescaler The block diagram of the phase/frequency detector The phase/frequency detector with reduced skew between the complementary outputs Schematic of the charge pump and loop filter Schematic of the rail to rail unity gain buffer used in the charge pump Percentage of the systematic error between up and down currents as a function of the output voltage Simulated VCO phase noise due to the thermal noise of the loop filter resistors Die micrograph of the 5 GHz frequency synthesizer in a 0.24 μm CMOS technology (1 mm 1:45 mm) VCO tuning range Phase noise of the synthesizer output signal Spectrum of the synthesized signal Synthesizer settling time B.1 ILFD model used for noise analysis B.2 Phasor representation of signals in Fig. B D.1 Cross section of a 2 turn spiral inductor xv

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17 Chapter 1 Introduction N the past decade the wireless industry has attracted the attention of many re- industrialists, and even investors. The current exponential growth of Isearchers, the wireless market requires wireless transceivers with ever increasing bandwidth, better quality, lower cost, and longer battery life. Cellular phones by far constitute the biggest market for wireless systems, but wireless local area network systems are also growing at avery fast pace. Until very recently two limitations of wireless local area network (WLAN) systems have been low data rate and high cost. The former is being overcome by allocating new frequency bands for WLAN service. Among these are the ISM band at 2.4 GHz and the U NII band at 5 GHz. New standards have been developed, with still others under development, to take advantage of these frequency bands. High integration in low cost technologies is the main step toward reducing the cost of WLAN systems. The fast trend of CMOS scaling makes it an attractive technology for low cost systems. However, to get the required RF performance out of standard digital CMOS technologies, new system architectures and circuit topologies need to be developed. Careful studies of wireless architectures identify fundamental limitations and allow modifications to improve performance while maintaining or even increasing battery lifetime. The increasing demand for wideband WLAN systems is the motivation for studying here the design of a fully integrated CMOS receiver at 5 GHz. In this dissertation 1

18 2 Chapter 1: Introduction we focus only on the frequency synthesizer and describe how new architectures and circuit topologies enable us to reduce the cost and power consumption while achieving high performance. 1.1 Organization The main objective of this dissertation is to study high frequency and low power frequency synthesis and division in a low cost CMOS technology. The techniques developed in this study apply to any technology and are not limited to CMOS. To prove the effectiveness of these techniques we demonstrate them in the context of a 5 GHz WLAN receiver. The following chapter introduces WLAN concepts and discusses different WLAN standards. In this chapter we present the existing and future markets for WLAN systems and explain the requirements necessary for a successful WLAN system. Chapter 3 deals with phase locked loop based frequency synthesizers, which are an essential part of any modern wireless system. In this chapter we specifically examine PLL filter design strategies. The effect of loop bandwidth and phase margin on loop settling time, spur levels, and output phase noise are studied and quantified. Finally we introduce a very simple loop filter design recipe for third and fourth order PLLs. Chapters 4 and 5 focus on high frequency and low power frequency division techniques. In chapter 4 we review existing frequency dividers and present the advantages as well as the disadvantages of each technique. Injection locked frequency dividers (ILFDs) that trade off bandwidth for power consumption are introduced and studied in full detail. In this chapter we present a general theory of ILFDs which explains the frequency division mechanism of ILFDs and predicts their operational frequency range (locking range). We also introduce design techniques to reduce the power consumption of an ILFD while increasing its locking range. In chapter 5we demonstrate the design of two experimental ILFDs and compare their performance with that of conventional frequency dividers.

19 1.1: Organization 3 In chapter 6 we put the theoretical and experimental developments of the previous chapters into practice and present the implementation of a fully integrated CMOS frequency synthesizer at 5 GHz. The experimental results show the lowest power consumption reported in any technology while comfortably meeting all specifications for a HIPERLAN receiver. We also demonstrate the operation of analog CMOS circuits with a sub 2V supply. Finally chapter 7 concludes with a summary and a list of suggestions for future work. The four appendices at the end of the thesis provide supplemental information. Appendices A and B present the extended mathematical analysis of the ILFD model and noise dynamics. Appendix C explores a polynomial approximation of oscillator nonlinearities. Finally, appendix D describes the inductor model used in the optimization of the on chip spiral inductors.

20 4 Chapter 1: Introduction

21 Chapter 2 Wireless Local Area Networks HE idea of a modern wireless local area network (WLAN) goes back at least Tto the late 1970s when IBM laboratories in Ruschlikon, Switzerland reported their infrared (IR) technology for indoor wireless networking [1]. Unfortunately the diffuse IR technology never provided a reliable link for desired data rates [2] and suffered from requiring a non obstructed medium. In 1985 WLANs entered a new era when the industrial, scientific, and medical (ISM) band was released by the FCC. The advent of new technologies, new architectures, and the allocation of compatible frequency spectrum stimulated the industry, resulting in the appearance of first generation commercial WLAN products around The demand for WLAN systems has increased steadily since. In health care industries, WLANs not only facilitate wireless connection of laptops, notebooks, and hand held instruments but also provide a wireless connection to health monitoring systems. It also allows fast and mobile connection to pharmaceutical and personal health care databases. In factory floors, WLANs speed up database access, and allow instant network access for delivery trucks. Educational environments also take advantage of WLANs by providing distant learning through wireless classrooms. Students have access to computational databases and online classes with notebook computers no matter where the students are. By far the biggest market for WLANs is in home and other small offices. Multiple computers, printers, and other peripherals are connected without the need for 5

22 6 Chapter 2: Wireless Local Area Networks Table 2.1: First generation WLAN standards IEEE HomeRF Bluetooth Frequency band 2:4 GHz ISM 2:4 GHz ISM 2:4 GHz ISM Modulation DSSS FHSS, 50 hops/s FHSS, 1000 hops/s Data rate 1Mb=s 1Mb=s 1Mb=s Power 20 dbm 20 dbm 0dBm,20 dbm Range 50 m 50 m 50 m Topology access point access point ad hoc cumbersome wiring. Additional nodes can be introduced easily without retrofitting the building to provide wired connections. Mobility isof course another big advantage. In conference rooms information can be transferred between laptops in real time. To maximize utility, WLANs should interoperate. In turn, interoperability requires a universally accepted standard. Because of the consequent importance of standards, we review some existing WLAN standards in the next section. 2.1 Wireless LAN standards First generation standards for spread spectrum WLAN systems in the 2:4 GHz ISM band include IEEE , Bluetooth, and HomeRF. Table 2.1 summarizes key specifications for these three standards. They all support data rates of 1 Mb=s over a distance of 50 m. One main difference among these three standards is that Bluetooth adopts an ad hoc topology (Fig 2.1 b) and creates piconets. Each piconet consists of up to eight nodes, any of which can be a slave or a master. Although HomeRF and IEEE are capable of supporting ad hoc networks, they employ access points (Fig. 2.1 a) to control LAN operation in their primary configurations. Wireless LANs generally need to provide data rates in excess of 10 Mb=s to compete with existing wired LANs. The IEEE b standard provides data rates of up to 11 Mb=s in the 2:4 GHz ISM band. In the US a new spectrum, called the

23 2.1: Wireless LAN standards 7 BSS 2 (a) AP AP Existing wired LAN AP BSS 1 BSS 3 (b) (c) Figure 2.1: Network topologies. (a) Access point. (b) Ad hoc. (c) Multihop ad hoc.

24 8 Chapter 2: Wireless Local Area Networks HIPERLAN U-NII GHz Figure 2.2: U NII and HIPERLAN frequency bands. unlicensed national information infrastructure (U NII) band, has been allocated for high data rate wireless communication. As shown in Fig. 2.2 the 300 MHz U NII band consists of a 200 MHz span from 5:15GHzto5:35 GHz, and a 100 MHz band from 5:725 GHz to 5:825 GHz. This latter span overlaps the ISM band. One of the developing WLAN standards in the U-NII band is IEEE a standard. Wireless LANs compatible with IEEE a use orthogonal frequency division multiplexing (OFDM) to provide data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mb=s [3]. The European WLAN standard for data rates in excess of 20 Mb=s inthe5ghz frequency range is the high performance radio LAN (HIPERLAN). The first draft of the HIPERLAN specification was released in October, 1996, and was finalized by the European Telecommunication Standards Institute (ETSI) with two amendments in June, The HIPERLAN/1 standard employs a multihop ad hoc topology (Fig. 2.1 c), which allows wireless connectivity beyond the radio range of a single node [4]. Each HIPERLAN node is either a forwarder or a nonforwarder. A nonforwarder node simply accepts the packet intended for it. A forwarder node transmits the received packet to other terminals in its neighborhood. The 150 MHz of the HIPERLAN spectrum (Fig. 2.2), which happensto overlap the lower 200 MHz of the U NII spectrum, is divided into 5 channels, each ofwhich is almost 23:5 MHz wide, leaving a guardband of about 25 MHz at each end of the spectrum. As shown in Table 2.2 modulation in a HIPERLAN/1 system is Gaussian

25 2.2: Summary 9 Table 2.2: Summary of HIPERLAN/1 standard Class A Class B Class C Transmitter power +10 dbm +20 dbm +30 dbm Receiver sensitivity 50 dbm 60 dbm 70 dbm Maximum signal level 25 dbm Modulation GMSK (BT = 0:3) Data rate 20 Mb=s Topology multihop ad hoc Carrier switching time» 1ms minimum shift keying (GMSK) with a 3 db bandwidth bit duration product (BT) of 0.3 which allows a data rate of 20 Mb/s ina23.5mhzwide channel [5]. As yet none of the existing standards has received universal acceptance. New standards are still under development to improve the quality of service, reduce system costs, and also to provide higher data rates in the existing frequency spectrum, while operating in a hostile environment inthepresence of strong interferers. 2.2 Wireless LAN transceivers In this section we do not intend to study all existing wireless transceiver architectures; instead we provide an overview of a representative wireless system. Fig. 2.3 shows a simplified picture of a typical wireless transceiver. In the transmitter the input data is modulated on a carrier signal (cos(! c t)) and transmitted over a wireless medium. In a typical heterodyne receiver the incoming signal is first amplified with a low noise amplifier (LNA), then mixed with a local oscillator (cos(! LO t)) to downconvert to a lower intermediate frequency. Finally the demodulator detects the received information to produce output data. As can be seen in Fig. 2.3 both the transmitter and receiver require accurate local oscillators for proper frequency conversion. It is the generation of these local frequencies which is the focus of this dissertation. In the following chapters we will

26 10 Chapter 2: Wireless Local Area Networks Data in Modulator LNA IRF Demodulator Data out cos(! c t) cos(! LO t) Transmitter Receiver Figure 2.3: Simplified picture of a wireless transceiver. first develop the required bases for the synthesis of radio frequency signals and then demonstrate the experimental results of such systems. 2.3 Summary In this chapter we have discussed the history of wireless LANs and some of their applications. A list of existing WLAN standards with a summary of their specifications was also provided for both low and high data rate systems. Existing standards are modified continuously and new standards are being developed. However, the question of which standard will survive and gain worldwide acceptance is not yet answered. It is most probable that a few existing and future standards will coexist and multi standard wireless systems will be built. Important factors in determining the success of these systems are performance reliability, cost, and the ability toop- erate in the presence of interference generated by both compatible and incompatible systems. In the following chapters we focus on the design and implementation of a phase locked loop (PLL ) based frequency synthesizer as a local oscillator (LO) for a low power and low cost U NII band WLAN receiver. Both system and circuit level issues will be discussed in detail.

27 Chapter 3 Frequency Synthesizers REQUENCY synthesizers are an essential part of nearly all multi frequency Fwireless transceivers. Phase locked loop (PLL ) based frequency synthesizers are used as local oscillators (LOs) in wireless receivers (Fig. 3.1) to downconvert the carrier frequency (! RF )toalower intermediate frequency (! IF ). Phase locked loops are also used to perform frequency modulation [6],[7] and demodulation [8]. Clock recovery systems also benefit from phase locked loops [9]. In this chapter we focus only on the frequency synthesis aspect of phase locked loops and study different classes of PLLs. 3.1 Phase locked loops Fig. 3.2 shows the block diagram of a typical PLL. The frequency divider (ΞM) in the feedback path divides the VCO output frequency (f out )andcompares it with a reference frequency (f ref ) with a phase/frequency detector (PFD). The output of the PFD is filtered with a lowpass filter, whose output in turn is the VCO control voltage. In this configuration the output frequency is M times the reference frequency. In an integer N frequency synthesizer M is an integer and thus the frequency separation between adjacent LOs is the same as the reference frequency. In case of a fractional N frequency synthesizer the division ratio is a rational number and thus the LO spacing is a fraction of the reference frequency. 11

28 12 Chapter 3: Frequency Synthesizers LNA Image Reject Channel Select ω ω Filter Filter Cos(ω t) LO ωrf ω 0 ωif ω Figure 3.1: Block diagram of a typical heterodyne receiver. fref f out =Mf ref PFD Loop Filter VCO M Channel Selection Figure 3.2: Block diagram of a typical phase locked loop.

29 3.1: Phase locked loops 13 Adjacent Channel Desired Channel LO Spectrum Downconverted signals Figure 3.3: Signal to interference degradation due to LO spurious sidebands. Wireless systems require very accurate synthesized frequencies (1 10 ppm accuracy). Therefore, temperature compensated crystal oscillators are generally used in generating the reference frequency. Unfortunately fundamental modes of inexpensive quartz crystals are limited to approximately 30 MHz [10] and operation at large order overtone modes is impractical. Therefore, GHz fractional N frequency synthesizers become very expensive for systems with tens of MHz channel channel spacing. Integer N frequency synthesizers are thus more practical and less costly, compared to fractional N frequency synthesizers, for such systems. Low spurious sideband amplitudes are an important requirement for frequency synthesizers. Fig. 3.3 pictures the problem of spurious sidebands. Suppose the synthesized LO is a pure sinusoid plus unwanted spurs at offset frequencies equal to the channel spacing. In the receiver the unwanted spurs act as parasitic LO signals that can downconvert the adjacent channel, into the same intermediate frequency (IF) as the desired channel and thus degrade the signal to interference ratio. In the transmitter the spurious emissions generate interference for the adjacent channels.

30 14 Chapter 3: Frequency Synthesizers Adjacent Channel Desired Channel LO Spectrum Downconverted signals Figure 3.4: Signal to interference degradation due to LO phase noise. Generally the in band blocking requirements define the maximum tolerable spurious tone levels. In most wireless systems spurious sidebands have to be less than 50 dbc. In an integer N frequency synthesizer spurious tones appear at offset frequencies equal to the harmonics of the reference frequency and thus fall in the middle of the adjacent channels. In a fractional N synthesizer, spurs at the harmonics of the reference frequency are not as important. However, spurs at fractions of the reference frequency can fall in the center of the adjacent channel and these are problematic. The source of the fractional spurs is the fractional divider. Generally a fractional divider is designed as a dual or perhaps multi modulus divider that toggles between two or more integer division ratios. The overall division ratio is thus the time average of the integer division ratios which is a fractional number. The periodic toggle between integer division ratios generates strong spurious tones at fractions of the reference frequency. In some synthesizers ± modulators are used to push this quantization noise to higher frequencies and reduce close in fractional spurs [11].

31 3.1: Linearized PLL models 15 Reciprocal mixing of the adjacent channels with LO phase noise also reduces the signal to interference ratio (Fig. 3.4). To understand this mechanism, suppose the RF signal is a pure sinusoid with a strong adjacent tone. When this composite signal is mixed with the noisy LO signal the tail of the downconverted adjacent channel falls in the same IF frequency as that of the desired channel. The signal to interference ratio is approximated by: S I db = 10 log(w s ) L B (3.1) where L is the phase noise in (dbc/hz) at a given offset frequency, B is the relative blocker level in (db) at the same offset frequency, and W s is the signal bandwidth in (Hz). This derivation assumes that the signal is a random process with a uniform power spectral density across the channel bandwidth. It also assumes that the LO phase noise is independent of the signal and is constant over the channel bandwidth. Clearly the phase noise must be reduced to tolerate larger blockers. The close in or in channel LO phase noise also degrades the signal to interference ratio. This time the interferer is the desired signal itself. The close in PLL phase noise is usually dominated by the noise of the reference signal Λ and is typically almost constantover the PLL bandwidth (W c ). The phase noise beyond the PLL bandwidth is mostly due to VCO noise and generally reduces in a 1=f 2 fashion (ignoring the flicker noise). With the assumption that the signal is a random process with a uniform power spectral density across the channel bandwidth and is independent of the LO phase noise, the signal to interference ratio is approximated by: S I db = 10 log(4w c ) L c (3.2) Λ Refer to section 3.3 for a detailed PLL noise analysis.

32 16 Chapter 3: Frequency Synthesizers Φ i + Σ Kp Z(s) K s vco Φ o 1 M Figure 3.5: Linearized PLL model. where L c is the close in phase noise in (dbc/hz). As the loop bandwidth increases it is important to reduce the close in phase noise to prevent signal to interference degradation. 3.2 Linearized PLL models Atypical phase locked loop of the type shown in Fig. 3.2 can be modeled as a linear system, as shown in Fig As long as the loop bandwidth of the PLL is much less than the reference frequency the same linear model can be used for a charge pump PLL as well [12]. The sample and hold nature of the charge pump PLL also demands a small loop bandwidth relative to the reference frequency to guarantee loop stability [8]. In this model the input and output are phases and not voltages. Therefore, the VCO is modeled as an integrator with a gain of K vco, and the phase detector has a gain of K p. In a charge pump PLL K p = I P 2ß [12], where I p is the charge pump current. The loop filter is modeled with Z(s). The number of poles of the loop filter, plus the fundamental pole of the VCO, define the order of the PLL.

33 3.2: Linearized PLL models First order PLL In a first order PLL Z(s) is a simple scalar. The PLL is a type one PLL with one integrator in the loop. In this case the closed loop input output phase transfer function is: ffi o (s) ffi i (s) = K pk vco s + K p K vco (3.3) Although the first order loop can provide a very fast loop response [13], it suffers from a non zero steady state phase error (ffi e ): ffi e (s) ffi i (s) = s s + K p K vco (3.4) If the reference signal is a pure sinusoid, the input phase is a ramp function (ffi i (s) =! i s 2 ) and the steady state phase error is lim sffi e (s) = s!0! i K p K vco =! i! c (3.5) where! c is the loop bandwidth and! i is the reference frequency. A continuous time first order PLL is stable for any loop bandwidth. However, in a practical PLL the loop bandwidth is always much smaller than the reference frequency to suppress spurious tones at the harmonics of the reference frequency. Therefore, the steady state phase error can be very large. First order PLLs using finite range phase detectors can thus go unstable unless an extended range phase detector like the one in [13] is used Second order PLL The steady state phase error is forced to zero in a second order PLL by introducing an additional integrator in the loop (type two PLL). Fig. 3.6 shows two ways

34 18 Chapter 3: Frequency Synthesizers R1 C1 U N D - Vc U N D R1 C1 Vc Figure 3.6: Circuit realizations of the loop filter in a second order PLL. of implementing this additional integrator in a charge pump PLL. Capacitor C 1 provides the additional integrator by integrating the charge pump current. Furthermore, the combination of C 1 and R 1 generates a zero at 1=(R 1 C 1 ). In this case the input output phase transfer function is: ffi o (s) ffi i (s) = MK fis+1 s 2 + fiks+ K (3.6) where K = K pk vco MC 1 (3.7) and fi = R 1 C 1 : (3.8)

35 3.2: Linearized PLL models 19 Compared to a first order PLL, the additional pole of a second order PLL can potentially increase the loop settling time. Settling time is especially an issue for fast frequency hopped systems, where the frequency synthesizer rapidly switches among different frequencies. Typically the PLL frequency is changed by adjusting the frequency multiplication factor M. Suppose at time zero (t = 0) M changes by a small amount m. The output frequency is then equal to: F o (s) = ß K p K vco Z(s) s + KpKvco M+ m Z(s)F i(s) (3.9) K p K vco Z(s) m + s + KpKvco M Z(s)(1 M )F i(s): (3.10) The multiplicative term(1+ m m M ) can be viewed as a step change ( M ) in the reference frequency at t = 0. With this simplification the output frequency is f o (t) = M + m + me fik 2 r t f i sin 2 4 p K 1 fi p K vu u t 1 ψfi p K 2! 2 t cos 1 ( fip K ) (3.11) The initial output frequency is Mf i and the final value is (M + m)f i. The transient time for the output frequency to reach within ff of its final value equals where t s2 ff(m + m) = m e fik 2 t s2 r 1 fi p K 2 t s2 ß 2 fik ln m r Mff 1 2 (3.12) : (3.13) fi p 2 K 2 is the settling time of a second order PLL. One would expect that a larger! c would result in a faster loop and thus a shorter settling time. To place this relationship on a quantitative basis, first note that the crossover frequency of a second order PLL is:

36 20 Chapter 3: Frequency Synthesizers! c2 = ψ K 2 fi 2 + p! 1 K 4 fi 4 +4K 2 2 = akfi (3.14) 2 where a = vu u q t K 2 fi 4 2 > 1: (3.15) Therefore we can rewrite (3.13) as: t s2 ß 2a! c2 ln Mff r m 1 > 2 ln m fi p 2! K c2 Mff 2 (3.16) which demonstrates the inverse dependency of the settling time on crossover frequency. If we repeat the preceding analysis for a first order PLL we get: f o (t) f i = M + m + me! c1t (3.17) and t s1 ß 1! c1 ln m Mff (3.18) where t s1 and! c1 = K p K vco =M are the settling time and crossover frequency of a first order PLL, respectively. Equations (3.16) and (3.18) show that, for a given crossover frequency, the settling time of a second order PLL is more than twice as much as that of a first order PLL. With our linearized model a second order PLL is always stable. However, if a charge pump is used then our linear model is valid only as long as the crossover frequency is much less than the reference frequency. In practice the sample and hold nature of a charge pump PLL requires the crossover frequency to be less than about

37 3.2: Linearized PLL models 21 C2 R1 C1 U N D - Vc U N D R1 C1 Vc C2 Figure 3.7: Circuit realization of the loop filter in third order PLL. 1/10 of the reference frequency to guarantee stability. Furthermore, any mismatch in the charge pump of a second order PLL causes sudden jumps on the VCO control voltage at every phase measurement cycle. Large spurious tones can thus appear at the output. Therefore, an additional capacitor is usually added to the loop filter (Fig. 3.7) to prevent sudden jumps on the VCO control voltage and thus reduce the spurious sideband levels. Unfortunately, this added capacitance increases the PLL order to three Third order PLL The additional pole of a third order PLL provides more spurious suppression. However, the extra phase lag associated with this pole introduces a stability issue. Thus the loop filter must be designed carefully to provide the required filtering while maintaining the loop stability. The impedance of the loop filter shown in Fig. 3.7 is:

38 22 Chapter 3: Frequency Synthesizers b Z(s) =( b +1 ) fis+1 sc 1 ( fis +1) (3.19) b+1 where fi = R 1 C 1 and b = C 1 =C 2. The loop transmission (LT ) of the third order PLL is The phase margin of the loop is LT = K vcoi p 2ß ( b b +1 ) fis+1 s 2 C 1 ( fis (3.20) +1): b+1 PM = tan 1 (fi! c3 ) tan 1 ( fi! c3 b +1 ) (3.21) where! c3 is the crossover frequency. By differentiating (3.21) with respect to! c3 it can be shown that the maximum phase margin is achieved when! c3 = p b +1=fi (3.22) with a corresponding maximum phase margin PM max = tan 1 ( p 1 b +1) tan 1 ( p ): (3.23) b +1 The maximum phase margin is thus only a function of b (the ratio of C 1 to C 2 ). For b less than 1 the phase margin is less than 20 ffi (Fig. 3.8), which makes the loop stability unsatisfactory. To complete our loop analysis we force! c3 = p b +1=fi and get: I p K vco 2ß M ( b b +1 )=C p 1 b +1: (3.24) fi 2

39 Phase margin (degrees) 3.2: Linearized PLL models C 1 =C 2 Figure 3.8: Maximum phase margin as a function of C 1 =C 2 ratio in a third order PLL. For a third order loop it is analytically complicated to find the settling time. In general the settling time is a function of the percentage change in the feedback division ratio ( m=m) and is larger for a larger m. Simulation is used to estimate the settling time of a third order PLL when Eq. (3.24) is satisfied. For most wireless systems m M < 0:04. Fig. 3.9 shows the simulated settling time to 10 ppm accuracy as a function of phase margin when m =0:04. The simulation is repeated for several M loop bandwidths (! c3 ). The settling time in Fig. 3.9 is normalized to the period of the reference frequency, T i =2ß=! i. For all loop bandwidths there is a minimum for the settling time when PM ß 50 ffi (b ß 6:5), and the settling time increases by only 30% when the phase margin is between 46 ffi and 52 ffi (5 < b < 8). For each phase margin the settling time is inversely proportional to the loop bandwidth (Fig. 3.10), as expected. The following empirical formula can be used to estimate the settling time to 10 ppm accuracy when m M < 0:04 and 20ffi < PM < 70 ffi : t s3 ß 2ß! c3 [0:0067PM 2 0:6303PM + 16:78] (3.25)

40 24 Chapter 3: Frequency Synthesizers ! c3 =! i = 0:01! c3 =! i = 0:025! c3 =! i = 0:05! c3 =! i = 0:1 t s3 =T i Phase margin (degrees) Figure 3.9: Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a third order PLL. 400 t s3 =T i PM=30 PM=42 PM=51 PM=58 PM= ! i =! c3 Figure 3.10: Normalized settling time to 10 ppm accuracy as a function of loop bandwidth in a third order PLL.

41 3.2: Linearized PLL models 25 where PM is in degrees and is calculated from (3.23). Notice that according to Eq. 3.25, the settling time changes by more than a factor of three for phase margin variations from 30 ffi to 70 ffi : 1:55 2ß! c3» t s3» 5 2ß! c3 : (3.26) To minimize the loop settling time of a fast frequency hopped PLL, it is therefore important to design the loop filter with a 50 ffi phase margin. As mentioned before, the main reason for adding the third pole to the loop is to reduce spurious tones. Fig shows the magnitude of the input output phase transfer function at the reference frequency as a function of the loop bandwidth when the phase margin is 50 ffi. The vertical axis is normalized to the PLL frequency multiplication factor (M). For a loop bandwidth of 1/10 of the reference frequency the normalized attenuation at the reference frequency is almost 30 db. The attenuation is larger for smaller loop bandwidths and is proportional to 1=! 2 c3 (-40 db/dec). The attenuation of the nth harmonic of the reference frequency (n! i )is40log(n) db more than that of the reference frequency. From the forgoing developments, we can finally define a loop filter design recipe as follows: 1. Find K vco for the VCO. 2. Choose a desired phase margin and find b from (3.23). [If PM=50 ffi, b =6:5] 3. Choose the loop bandwidth (! c3 )andfindfi from (3.22). [fi = p 7:5! c3 ß 2:7! c3 ß e! c3 for b =6:5] 4. Select C 1 and I p such that they satisfy (3.24). 5. Calculate the noise contribution of R 1 y. If the calculated noise is negligible the design is complete; otherwise go back to step 4 and increase C 1. In a third order PLL the combination of the phase margin and loop bandwidth defines the characteristics of the loop. To further reduce the spurs without decreasing y Refer to section 3.3 for noise calculation.

42 jh(j! c3 )j=m 26 Chapter 3: Frequency Synthesizers ! i =! c Figure 3.11: The magnitude of the input output phase transfer function at the reference frequency as a function of the loop bandwidth when the phase margin is 50 ffi. the loop bandwidth and hence increasing the settling time, an additional pole needs to be added to the loop. This additional pole increases the PLL order to four Fourth order PLL Fig shows the circuit implementation of the loop filter in a fourth order PLL. In this case the impedance of the loop filter is: Z(s) = fis+1 sc 1 (1 + C 2 C 1 + C 3 C1 )[B(fis)2 + A(fis)+1] (3.27)

43 3.2: Linearized PLL models 27 U N D R1 C1 C2 R3 Vc C3 Figure 3.12: Circuit implementation of the loop filter in a fourth order PLL. where A = 1+b fi 2 fi (1 + C 2 C 1 ) 1+b B = b 1+b :fi 2 fi :C 2 C 1 fi = R 1 C 1 fi 2 = R 3 C 3 b = C 1 C 2 + C 3 The phase margin is A(fi! PM = tan 1 (fi! c4 ) tan 1 c4 ) ( 1 B(fi! c4 ) ) (3.28) 2 where! c4 is the crossover frequency of the loop transmission. As for a third order loop the maximum phase margin is achieved when the derivative of (3.28) with respect to! c4 is zero. The crossover frequency for the maximum phase margin in a fourth order PLL is vu u! c4 = 1 t 1 fi AB + A A2 + B(B A) s 2B + AB + A A 2 B(B A) 2 1 4(1 A) A : B(B A) (3.29)

44 28 Chapter 3: Frequency Synthesizers 100 Loop transmission Magnitude (db) Phase (degree) Frequency (Hz) Figure 3.13: Loop transmission Bode plot of a typical fourth order PLL Finally for! c4 to be the crossover frequency it should satisfy the following equation. I p K vco 2ß M s 1+(fi! c4 ) 2 (Afi! c4 ) 2 +(1 B(fi! c4 ) 2 ) = C 1( 1+b )! 2 2 c4 (3.30) b As in a third order loop the maximum phase margin is not a function of the absolute values of the R's and C's; it is only a function of their ratios. Equations (3.28) and (3.29), although accurate, are too complex and must be simplified in practical cases. Fig shows the loop transmission Bode plot of a typical fourth order PLL. Because of the two integrators in the loop the phase starts at 180 ffi. The zero then adds positive phase and increases the phase margin. Finally the third and fourth poles come into play and the phase at high frequencies is 270 ffi. A positive phase margin is the result of the zero at a lower frequency than the two high frequency poles and therefore C 2 C 1 < 1. Also for the fourth pole not to decrease the phase margin

45 3.2: Linearized PLL models 29 drastically it has to be more than a decade away from the zero and thus b fi 2 fi fi 1. With these conditions B fi A and we can approximate A,! c4, and (3.30) as: A ß 1 1+b (3.31)! c4 ß 1 fi 1 p A ß p 1+b fi (3.32) I p K vco 2ß M ( b b +1 ) ß C p 1 b +1: (3.33) fi 2 The maximum phase margin also simplifies to A p A PM max ß tan 1 ( p 1 ) tan 1 ( A 1 B A ß tan 1 ( p 1 1+b) tan 1 ( p ): 1+b ) ß tan 1 ( 1 p A ) tan 1 ( p A) (3.34) With these approximations the maximum phase margin is only a function of b = C 1 C 2 +C 3. Fig shows the exact maximum phase margin as a function of b for different fi 2 fi ratios. The phase margin for the case of fi 2 fi =0is shown as well. When fi 2 fi = 0 the loop order reduces to three and Eq. (3.34) is exact. For fi 2 fi < 0:01 and b < 10 the phase margin estimated by Eq. (3.34) is less than 2 ffi higher than the exact value. The error is bigger for larger values of b and fi 2 fi. Simulation is used to estimate the settling time to 10 ppm accuracy when m M < 0:04. As for any loop the settling time is inversely proportional to the loop bandwidth (Fig. 3.15). Also, as shown in Fig the settling time at a given phase margin is independent of fi 2 fi and is the same as that of a third order loop with the same phase margin. Therefore, equation (3.25) can be used for a fourth order loop as well to estimate the settling time. As in a third order loop the loop filter should be designed for a 50 ffi phase margin to minimize the PLL settling time.

46 Phase margin (degrees) 30 Chapter 3: Frequency Synthesizers fi 2 =fi = 0:10 fi 2 =fi = 0:05 fi 2 =fi = 0:01 fi 2 =fi = 0: C 1 =(C 2 + C 3 ) Figure 3.14: Maximum phase margin as a function of C 1 =(C 2 + C 3 ) PM=30 PM=42 PM=51 PM=58 PM=65 t s4 =T i ! i =! c4 Figure 3.15: Normalized settling time to 10 ppm accuracy as a function of loop bandwidth in a fourth order PLL.

47 3.2: Linearized PLL models fi 2 =fi = 5e 2 fi 2 =fi = 5e 3 fi 2 =fi = 5e 4 60 t s4 =T i Phase margin (degrees) Figure 3.16: Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a fourth order PLL. So far we have shown that for b fi 2 fi fi 1, third and fourth order loops with the same b and loop bandwidth have nearly identical phase margins and settling times. The additional pole of a fourth order PLL provides higher spurious filtering without reducing the loop bandwidth. The spurs appear at the harmonics of the reference frequency and are usually largest at the first harmonic. Fig shows the magnitude of the input output phase transfer function at the reference frequency. The solid line is for a third order loop. The non solid lines are for a fourth order loop with different fi 2 fi ratios. As the loop bandwidth decreases, the additional filtering of the fourth pole becomes more prominent. For example when the loop bandwidth is 1/100 of the reference frequency the attenuation at the reference frequency is 14 db larger in a fourth order loop with fi 2 fi = 0:05, and increases by fi 2 fi. To improve the spurious filtering of a third order loop by the same amount, we would have to reduce the loop bandwidth by more than 2.2 times, which would increase the settling time by the same factor. The filtering of the higher harmonics is improved by an even larger factor in a fourth order loop. The attenuation of the nth harmonic of the

48 jh(j! c4 )j=m 32 Chapter 3: Frequency Synthesizers 0 50 fi 2 =fi = 0:10 fi 2 =fi = 0:05 fi 2 =fi = 0:01 fi 2 =fi = 0: ! i =! c Figure 3.17: Normalized magnitude of the input output phase transfer function of a fourth order PLL at the reference frequency as a function of the loop bandwidth (PM=50 ffi. reference frequency is 60 log(n) db more than that of the reference frequency. This is 20 log(n) db more than what is achieved in a third order PLL. Now we can define the loop filter design recipe of a fourth order loop: 1. Find K vco for the VCO. 2. Choose a desired phase margin and find b from (3.34). [If PM=50 ffi, b =6:5] 3. Choose the loop bandwidth (! c4 )andfindfi from (3.32). [fi = p 7:5! c4 ß 2:7! c4 ß e! c4 for b =6:5] 4. Choose the desired spur attenuation and find fi 2 fi from Fig Select C 1 and I p such that they satisfy (3.33). 6. Calculate the noise contribution of R 1 and R 3 z. If their noise contribution is negligible the design is complete, otherwise go back to step 5andincrease C 1 z Refer to section 3.3 for noise calculation.

49 3.3: Noise in phase locked loops 33 Φ ni Φ nv Φ i + Σ + Kp Z(s) K s vco + Σ + Φ o 1 M Figure 3.18: The linearized PLL model with noise added at the input and output. to reduce the noise of both R 1 and R 3, or just increase C 3 (for a fixed b) and repeat step 6toreduce only the noise of R Noise in phase locked loops There are several noise sources in a PLL. The two main noise sources are that of the VCO, modeled by ' nv, and the noise from the reference signal, ' ni. Fig shows the linearized PLL model with the VCO and reference noise added. The noise of the frequency dividers, phase detector, charge pump, and loop filter can all be represented by ' ni. The noise transfer function from ' ni to ' o is the same as the input output phase transfer function and is a low passfunction: ' o (s) ' ni (s) = K p K vco N(s) sd(s)+ KpKvco M N(s) (3.35) where N(s) and D(s) are the numerator and denominator of the loop filter transfer function respectively. At low frequencies sd(s) fi KpKvco 'o(s) N(s) and M ' ni ß M. (s) This noise amplification within the loop bandwidth is expected from the frequency multiplication of the PLL. However, at high frequencies ' ni is attenuated and the attenuation increases by 20 log(n m) db/dec of the frequency, where n is the order

50 34 Chapter 3: Frequency Synthesizers of the loop and m is the order of N(s). The VCO noise, unlike ' ni, is high pass filtered: ' o (s) ' nv (s) = sd(s) sd(s)+ KpKvco M N(s) (3.36) At low frequencies sd(s) fi KpKvco N(s) and the VCO noise attenuation is proportional to s i, where i is the number of integrators in the loop. Except for the M first order loop all other loops discussed in the previous sections have two integrators. At frequencies beyond the loop bandwidth sd(s) fl KpKvco 'o(s) N(s) and M ' nv(s) ß 1. Typically at low frequencies the PLL noise is dominated by reference noise and at higher frequencies by VCO noise. The noise of the frequency dividers, phase detector, and charge pump are simply added to the reference noise and are usually negligible in a careful design. However, loop filter noise can be considerable especially when the VCO gain constant, K vco,islarge. The only source of noise in a loop filter of a second and a third order PLL is resistor R 1. The transfer function from V n1, the equivalent voltage noise of R 1 (V 2 n1 =4KTR 1 f), to the output is calculated as: ' o V n1 = sc 1 ' o (s) R 1 C 1 s +1' ni (s) (3.37) The fourth order loop has an additional source of noise, R 3. The noise transfer function from V n3, the equivalent voltage noise of R 3 (V 2 n3 = 4KTR 3 f), to the output is calculated as: ' o =(1+ C 3 sc 1 ' o (s) + R 3 C 3 s) V n3 C 1 R 1 C 1 s +1' ni (s) (3.38) Because of the additional zeros in (3.37) and (3.38) compared to (3.35) the output noise due to the thermal noise of R 1 and R 3, initially increases with frequency and then decreases. Therefore, it is important to make sure that the thermal noise

51 3.4: Conclusion 35 of these resistors does not cause too much noise peaking at low frequencies while maintaining low noise at high frequencies. 3.4 Conclusion In this chapter we discussed phase locked loops at a system level. Loop stability, phase noise (both in channel and out of channel), spurious tones, and loop settling time are the main issues to consider in a PLL design. Assuming that all of these issues are equally important, the fourth order PLL provides a good compromise, although a third order loop may suffice for many applications. In this chapter we focused on the design of single loop frequency synthesizers and introduced very simple design recipes for third and fourth order PLLs. In some applications we may need to use multiple loops to improve the overall performance, mainly the settling time and noise. Despite the increased complexityofsuch systems the design of each loop uses the same principles discussed in this chapter.

52 36 Chapter 3: Frequency Synthesizers

53 Chapter 4 Frequency Dividers I N the previous chapter we saw one of the main applications of frequency dividers. Frequency dividers are placed in the feedback path of a phase locked loops (PLLs) to synthesize a high frequency local oscillator (LO) from a precise low frequency crystal oscillator. Another important application for frequency dividers is to generate quadrature signals from a higher frequency signal [14]. Conventionally digital techniques are used for both purposes. However, as the frequency of operation approaches the limits of the technology, digital techniques become less attractive as they consume extensive power or even fail to operate. Therefore, at high frequencies purely analog techniques become more appropriate. In this chapter we survey some of the most popular digital and analog frequency division techniques and study injection locked frequency division as a solution for very high frequency and low power applications. 4.1 Digital frequency dividers A digital frequency divider is in principle a counter. The main advantage of digital dividers over their analog counterparts is that they can be readily designed for variable division ratios and are easily cascaded to generate very large division ratios. General characteristics of these dividers are that they are wideband and their power consumption increases with the frequency of operation. 37

54 38 Chapter 4: Frequency Dividers D Q Latch Clk Q D Latch Q Q Clk Clk Figure 4.1: Block diagram of a divide by two frequency divider. Figure 4.1 shows a specific example of a divide by two frequency divider. It comprises two ring connected connected D latches. Details of latch design differ, depending upon the frequency of operation. At low frequencies CMOS logic is desirable. However, at high frequencies source coupled logic (SCL) is preferred for two reasons. First, operation at higher frequencies is feasible with SCL latches. Secondly, power consumption in both CMOS and SCL latches, when designed properly, is proportional to CV 2 f, where V is voltage swing, f is frequency, and C is total capacitance. Therefor, due to the smaller voltage swing of SCL latches the power consumption can be reduced considerably at high frequencies. As mentioned earlier an important characteristic of digital dividers is the feasibility of implementing a variable division ratio. Fig. 4.2 a shows the block diagram of a divide by 2/3 made of two D flipflops, an AND gate, and an OR gate. The implementation of each flipflop is shown in Fig. 4.2 b. When Mc = 1 the first flipflop (FF1) is isolated from the output. Therefore, the divider has only one state variable (Q2) and divides by two. However, when Mc = 0 there are two state variables Q1 and Q2. In steady state Q1 n+1 = Q2 n (4.1) Q2 n+1 = Q2 n :Q1 n (4.2)

55 4.1: Digital frequency dividers 39 D Q FF1 Clk Q Q1 Mc D Q FF2 Clk Q Q2 (a) D Q Latch Clk Q D Q Latch Clk Q Clk (b) Figure 4.2: (a) Block diagram of a divide by 2/3 frequency divider. diagram of a master slave D flipflop. (b) Block Table 4.1: State transitions for the divide by 2/3 when Mc = 0 Q1 n Q2 n Q1 n+1 Q2 n Figure 4.3: State transitions in the divide by 2/3 when Mc = 0.

56 40 Chapter 4: Frequency Dividers where the indices represent the cycle numbers. All the possible states and transitions are tabulated in Table 4.1 and shown in Fig Each circle in Fig. 4.3 represents one state, marked with the state variables (Q1 Q2). In steady state there are only three feasible states and thus the divider divides by three. Flipflop FF2 in the divide by 2/3 frequency divider has a fanout of three (Fig. 4.2), while the fanout of the divide by two divider (Fig 4.1) is two. Therefore, the maximum operation frequency of the divide by 2/3, made of the same latches as in the divide by two frequency divider, is lower by almost a factor of 1.5. On the other hand, since the divide by 2/3 divider has twice as many latches plus two additional gates, its power consumption is more than twice the power of the divide by two divider. The maximum operational frequency of these dividers is determined by the speed of the latches. As mentioned earlier SCL latches can potentially operate at higher frequencies than their CMOS counterparts, with lower power consumption. An example of an SCL latch is shown in Fig. 4.4, whose operation is as follows. When input, Clk, is high the signal on the D port is passed to the output over a bandwidth set by the output RC time constant, where R is the output resistance and C is the total output capacitance. As Clk transitions from high to low the cross connected transistors M5 and M6 generate a negative conductance which provides regenerative feedback and latches the output. To find the maximum theoretical operation frequency of this latch assume that Clk is a square wave signal. Fig. 4.5 shows the SCL latch input (Clk) and output voltage (v o (t) =v(q) v(q)) in a divide by 2 configuration at a very high operation frequency. Without loss of generality we assume that at t = 0Clk transitions from low to high and v o (0) = v a, where v a is the output amplitude. For 0» t» T=2, where T is the period of Clk, the output increases exponentially v o (t) = v ( v + v a )e t fi 1 ; 0» t» T=2 (4.3)

57 4.1: Digital frequency dividers 41 Vdd R R C Q Q C D D M3 M4 M5 M6 Clk Clk M1 M2 I Figure 4.4: Schematic of the SCL D latch. Clk +v a +v m v o (t) v m v a 0 Figure 4.5: Input (Clk) and steady state output voltage (v o (t)) of the SCL D latch in a very high frequency divide by two frequency divider. t

58 42 Chapter 4: Frequency Dividers where v = IR and fi 1 = RC. At t = T=2 Clk transitions from high to low andthe output is v o ( T 2 )=v m = v ( v + v a )e T 2fi 1 : (4.4) In the next half cycle (T=2» t» T ) M5 and M6 provide a differential negative conductance G at the output. For simplicity we ignore short channel effects and assume transistors are square law devices (i = k(v gs V TH ) 2 ). negative conductance as a function of the output voltage is G = 8 < : 2k 2 v p o 2kI 2 2kI k 2 vo 2 if jv o j» 0 otherwise q I k In this case the (4.5) q I When jv o j k either M5 or M6 is turned off and G = 0. When v o = 0 the output conductance is at its most negative value G = g m where g m is the small signal transconductance of M5 and M6 biased with a drain current of I=2. simplicity we assume G is constant over the whole half cycle (G = g m ). With this assumption the output voltage increase exponentially with time For v o (t) =v m e t T=2 fi 2 ; T=2» t» T (4.6) where fi 2 = RC (g mr 1). At the end of the cycle (t = T ) the output voltage is v o (T )=v a = v m e T 2fi 2 : (4.7) Eq. (4.4) and (4.7) result in 1 x v a = v (4.8) x + x (gmr 1) where x = e T 2fi 1. Now if we replace v by IR and recall that g m = is the overdrive voltage (V od = V gs fi fifiid = I 2 I 2V od, where V od V TH), we can rewrite Eq. (4.8) as:

59 4.1: Digital frequency dividers 43 1 x v a =2g m RV od : (4.9) x + x (gmr 1) To steer the current substantially from one branch of a differential structure to the other branch, the output amplitude should be greater than or equal to about p 2V od. Therefore, p 1 x 2gm R 1 (4.10) x + x (gmr 1) For every g m R,(4.10)defines a minimum value for x or a maximum value for fi 1 T at which the divider still functions. Assume that at a given g m R (e.g., g m R = a) the maximum value for fi 1 T is b (i.e., fi 1 T» b). Now replace fi 1 by RC to get f = 1 T» b a g m C : (4.11) If we assume that the divider in Fig. 4.1 drives an identical divider, then C 3C gs, where C gs is the gate source capacitance of M5 or M6 (Fig. 4.4). Thus or f» b g m (4.12) 3a C gs f» b 3a f T : (4.13) The normalized maximum operation frequency of this divider is plotted in Fig. 4.6 as a function of g m R, and is seen always to be less than 0:18 f T. In practice the maximum frequency of operation will be even less than predicted by (4.13), because practical circuits do not satisfy the assumption of a perfect square law device and also perfect square wave Clk. At higher frequencies analog techniques are the only

60 44 Chapter 4: Frequency Dividers f=ft g m R Figure 4.6: Normalized maximum operational frequency of the SCL latch in a divide by two frequency divider as a function of g m R. solution. For this reason several relevant analog frequency division techniques are discussed in the following sections. 4.2 Analog frequency dividers An important characteristic that distinguishes analog frequency dividers from digital dividers is their narrower frequency range of operation. Digital dividers can be viewed as inherently lowpass systems while analog dividers can be bandpass in nature, and potentially operate at higher frequencies. With the right architecture and careful design, analog dividers can trade off bandwidth with power and maximum operational frequency. This trade off is the key to design very high frequency and low power frequency dividers. Regenerative dividers, Fig. 4.7 a, are the most widely used analog frequency dividers [15],[16],[17], and operate by combining frequency multiplication in the feedback path with mixing at the input. Regenerative dividers can operate at frequencies

61 4.2: Analog frequency dividers 45! i! o =! i N A LPF (N 1) (a)! i! r =! i! r =! o! o =! i BPF BPF 2 (b) Figure 4.7: (a) Regenerative frequency divider. (b) Parametric frequency divider. close to f T =2[14].As mentioned earlier, analog dividers may be bandpass systems. In the special case of a divide by two regenerative frequency divider, the theoretical maximum ratio of the highest frequency of operation to the lowest frequency of operation is less than three. In practice regenerative dividers require many functional blocks to guarantee proper operation [17]. Therefore, regenerative frequency dividers, although capable of operation at very high frequencies, are not the best solution for low power systems. Parametric frequency dividers, Fig. 4.7(b), are a group of analog frequency dividers often used in microwave systems [15], [18], [19]. The frequency division principle of a parametric frequency divider relies on exciting a varactor at frequency f and realizing a negative resistance that sustains a loop gain of unity at f. High 2 Q varactors and inductors are key elements in parametric frequency dividers [19]. Therefore, a successful and fully integrated implementation of this kind of divider in contemporary silicon technologies is hard, if not impossible.

62 46 Chapter 4: Frequency Dividers A third group of analog frequency dividers uses injection locking. Conventionally injection locking is used to lock an oscillator to the fundamental or a higher harmonic of an incident signal[20],[21],[22],[23]. However, injection locked oscillators can also serve as frequency dividers [24]. In the following sections we look at the history of injection locked oscillators (ILOs) and develop a general theory for the operation and noise of injection locked frequency dividers. 4.3 Injection locked frequency dividers An injection locked frequency divider is an oscillator in which a harmonic of the oscillation frequency is locked to the fundamental frequency of the incident signal. The theory of injection locking or forced oscillation in nonlinear circuits was first studied by van der Pol in the early 1920s [25]. Adler [26] used a phasor diagram technique to model the behavior of an ILO locked to the fundamental frequency of an incident signal and defined a locking range figure of merit. The study of ILOs was later extended to an ILO with a subharmonic of the oscillation frequency locked to the incident frequency [20],[21],[22],[23]. Uzunoglu et al. [27] prefer the term synchronous oscillator (SO) for an injection locked oscillator. They report frequency division with SOs without providing a physical model to explain the frequency division mechanism. Historically ILOs are named based on the ratio of the incident frequency (f i ) to the oscillation frequency (f o ). When the oscillation frequency is the same as the incident frequency (f i = f o ) the ILO is called a first harmonic ILO. When the incident frequency is a fraction of the oscillation frequency (f i = fo ) the ILO is N a subharmonic ILO. Finally, when ILOs behave as frequency dividers, where the incident frequency is a harmonic of the oscillation frequency (f i = Nf o ), they are called superharmonic ILOs. We will refer to this latter group as injection locked frequency dividers. Regardless of the names and terms used for different classes of ILOs, all of the previously published work focuses on small signal analysis and application of ILOs. In the following sections we eliminate restrictions on signal amplitude and develop

63 4.3: Injection locked frequency dividers 47 f(v o ) u H(!) v o Figure 4.8: Model for a free running oscillator. v i u H(!) f(v i ;v o ) v o Figure 4.9: Model for an injection locked frequency divider. a general theory for injection locked frequency dividers (ILFDs). We also introduce an ILFD whose center frequency tracks the incident frequency, to extend the locking range. A noise analysis of the ILFD completes this chapter Model for injection locked frequency dividers An ILFD is an oscillator with a forced oscillation. An oscillator can be modeled as a nonlinear block, f, followed by a frequency selective block (e.g., an RLC tank), H(!), in a positive feedback loop as shown in Fig The nonlinear block models all the nonlinearities in the oscillator, including any amplitude limiting mechanism. In order to have a steady state oscillation, a loop gain of unity should be maintained. As with conventional unforced oscillators, we may express the oscillation condition in terms of amplitude and phase criteria. The amplitude condition is satisfied if the

64 48 Chapter 4: Frequency Dividers output amplitude is the same as the input amplitude in an open loop excitation of the system at the oscillation frequency! o. The phase condition requires that the excess phase introduced in the loop at! =! o be zero. With an additional external signal (i.e., the incident signal) this same model can be applied to an ILFD (Fig. 4.9). The nonlinear block is now a function of two variables (v i and v o ). To investigate the injection locking phenomenon in an ILFD, we define: v i (t) = V i cos(! i t + ') (4.14) v o (t) = V o cos(! o t) (4.15) u(t) = f(v o (t);v i (t)) (4.16) H(!) = H 0 1+j2Q!!r! r (4.17) where v i (t) is the incident signal,v o (t) is the output signal, ' is the phase difference between those two signals, and! r and Q are the resonant frequency and loaded quality factor of the RLC tank, respectively. The output of the nonlinear block, u(t), generally contains various harmonic and intermodulation terms of v i (t) and v o (t). As shown in appendix A, we can write u(t) as: u(t) =f(v i ;v o )= 1X 1X m=0 n=0 K m;n cos(m! i t + m')cos(n! o t) (4.18) where each K m;n is an intermodulation coefficient of f(v i ;v o ). We assume that all frequency components of u(t) far from the resonant frequency of the tank are filtered out, so the frequency of the output signal can be written as! o =! r +!. Thus, we need only consider intermodulation terms with frequency! o, that is, jm! i n! o j =! o. For an N-th order ILFD (i.e.,! o = 1 N! i), the intermodulation terms with n = Nm ± 1 possess a frequency equal to 1 N of the

65 4.3: Injection locked frequency dividers 49 incident frequency. The signal u!o (t), which is the component ofu(t) with frequency! o, can be written as: u!o (t) =K 0;1 cos(! o t) X m=1 K m;nm±1 cos(! o t m'): (4.19) Using a complex exponential to replace sines and cosines, and applying the oscillation condition, the output signal can be written as: v o = V o e j!ot = H 0e j!ot 1+j2Q!! r [K 0; X m=1 K m;nm±1 e jm' ]; (4.20) or V o (1 + j2q!! r )=H 0 [K 0; X m=1 K m;nm±1 e jm' ]: (4.21) The imaginary and real parts of (4.21) can be equated separately to yield: 2V o Q!! r = H 0 2 1X m=1 K m;nm±1 sin(m'); (4.22) V o = H o [K 0; X m=1 K m;nm±1 cos(m')]: (4.23) Equations (4.22) and (4.23) are the fundamental equations for an N-th order ILFD. The simultaneous solution of these two equations specifies V o and ' for any incident amplitude V i and any incident frequency! i or, equivalently, for any offset frequency! =! i N! r. Equation (4.22) can be rearranged as:

66 50 Chapter 4: Frequency Dividers where! A =!r V i 2Q V o! =! A [ H 0 2V i 1X m=1 K m;nm±1 sin(m')] (4.24) is Adler's locking range figure of merit [26]. The fundamental equations, (4.22) and (4.23), are very general, but provide limited intuition. However, as shown in the next section, (4.22) and (4.23) can be solved analytically for special cases which allow the development of design insight Divide by two ILFDs with third and fourth order nonlinear functions In many cases the ILFD nonlinearity can be approximated with a polynomial function of the sum of the two variables (f(v i ;v o ) = f(v i + v o )). In this case if we limit the order of the nonlinearity to three (i.e., f(x) = a 0 + a 1 x + a 2 x 2 + a 3 x 3 ), the only unknown in (4.22) for a divide by two ILFD (N = 2) is the input-output phase difference, '. The phase condition thus can be satisfied independently of the amplitude condition: and sin(') = 2Q! H o a 2 V i! r jsin(')j < 1 )j! j < j H 0a 2 V i j: (4.25)! r 2Q On the other hand, solving (4.23) results in an expression for the oscillation amplitude: r 4 1 V o = [1 H 0 (a 1 + a 2 V i cos(')+ 3 3 a 3 H 0 2 a 3Vi 2 )]: (4.26)

67 4.3: Injection locked frequency dividers 51 As (4.25) suggests, a larger incident amplitude as well as a larger H 0 Q larger achievable locking range,!. In an LC oscillator H 0 Q result in a =!L, so the largest practical inductance should be used if maximizing the locking range is the objective. Increasing the incident amplitude increases the locking range as long as there exists a solution for (4.26), 1 a 3 [1 H 0 (a 1 + a 2 V i cos(')+ 3 2 a 3V 2 i )] 0: (4.27) The term H 0 a 1 represents the oscillator small signal loop gain and has to be larger than unity for an oscillator to start oscillating. The coefficient of the third order nonlinearity, a 3, has to be less than zero to reduce the loop gain as the oscillation amplitude grows and thus limit the oscillation amplitude (Appendix C). Therefore, (4.27) simplifies to: H 0 (a 1 + a 2 V i cos(')+ 3 2 a 3V 2 i ) 1: (4.28) In practice the locking range can be phase limited (limited by the failure of (4.25)), or amplitude limited (limited by (4.28) failure). An amplitude limited locking range is only observed at large incident amplitudes, with an oscillation amplitude at the edge of the locking range even smaller than the free running oscillation amplitude. Therefore, a phase limited locking range can be distinguished from an amplitude limited locking range by its relatively large output amplitude at the edge of the locking range. A strong quadratic nonlinearity (large ja 2 j) also increases the locking range of a divide by two ILFD. Therefore, circuit topologies with a dominant second order nonlinearity (e.g., the differential ILFD in section 5.1) are favorable for wide locking range divide by two ILFDs. A counterintuitive result of (4.25) is that the locking range does not depend on the tank quality factor, Q. One would expect that a lower Q results in a larger locking range as the total 180 ffi phase variation of the tank circuit spans a larger

68 52 Chapter 4: Frequency Dividers frequency range. That is, we would think that a circuit with a lower Q, being less frequency selective, should provide a larger locking range. The Q independence of locking range is indeed unusual, and holds only for a third order nonlinear system. If we repeat the preceding analysis with a fourth order nonlinear function (f(x) = a 0 + a 1 x + a 2 x 2 + a 3 x 3 + a 4 x 4 )we observe the expected Q dependence of the locking range. In this case Eq. (4.22) and (4.23) simplify to: j!! r j»j H 0a 2 V i 2Q jj1+(3 2 V 2 i + V 2 o ) a 4 a 2 j (4.29) and s 1 H 0 [a 1 + a 2 V i cos(')+ 3 2 V o = a 3Vi a 2 4Vi 3cos(')] H 0 [ 3 a : (4.30) a 4 V i cos(')] The right hand side of (4.29) is the same as that of (4.25) with an additional term ([ 3 V 2 2 i + Vo 2 ] a 4 a 2 ) from the fourth order nonlinearity. In this case the locking range not only depends on H 0 Q and the incident amplitude, but also on the oscillation amplitude, V o. A larger tank Q results in a larger oscillation amplitude and thus reduces the locking range if a 4 a 2 < 0. In Appendix C the nonlinearity of a single ended bipolar oscillator is approximated with a fourth order polynomial function. The identified nonlinear coefficients satisfy the above assumption. Another important observation is that, unlike an ILFD with a third order nonlinearity, the locking range is not a linear function of the incident amplitude. Because of the ( a 4 a 2 )V 2 i term in (4.29), the locking range is sub linear and is less than what is predicted by (4.25). The difference, of course, is more obvious at large incident amplitudes. Finally the locking range in an ILFD is a function of the incident amplitude. So, by injecting the incident signal into a high impedance node, the required incident power can be reduced significantly. Due to the high impedance of the gate of MOS transistors, MOS transistors are a good candidate for injection locked oscillators.

69 4.3: Injection locked frequency dividers 53 VCO Tracking ILFD V i 1 2 Vo V c Figure 4.10: Tracking ILFD Tracking injection locked frequency dividers The previous section discusses different design techniques to increase the locking range of an ILFD. All those methods follow from the fundamental equations (4.22) and (4.23). The underlying assumption in the derivation of (4.22) and (4.23) is that the resonant frequency of the LC tank is constant. In a tracking ILFD we intentionally violate this assumption to achieve a wider locking range [28]. Fig illustrates the idea of a tracking ILFD. The free running oscillation frequency of the tracking ILFD is tuned with a varactor and its control voltage is tied to that of the voltage controlled oscillator (VCO) that supplies the incident signal. Thus the center frequency of the ILFD tracks the incident frequency (VCO frequency). This additional frequency tuning capability of the tracking ILFD increases its locking range beyond what is achieved with a fixed tank frequency Noise in injection locked frequency dividers In order to investigate the phase noise performance of an ILFD, we first consider the response of a first harmonic ILO to a deterministic sinusoidal noise input. For simplicity we assume f(v i ;v o ) can be approximated by f(v i + v o ). Fig shows the simplified model with the noise, v n, added to the summing junction. The noise can either come from the incident signal, or from the ILO itself. The incident signal, output signal, and sinusoidal noise are represented by their equivalent phasors in Fig. 4.12, and mathematically defined as:

70 54 Chapter 4: Frequency Dividers v n v i e u f (e) H(!) v o Figure 4.11: ILO model used for noise analysis. V o E o E fl r U!o ff ' V n fi V i Figure 4.12: Phasor representation of signals in Fig.4.11

71 4.3: Injection locked frequency dividers 55 v i (t) = V i cos(! o t) (4.31) v o (t) = V o cos(! o t + ') (4.32) v n (t) = V n cos((! o +! n )t + ' n ): (4.33) In the absence of noise, the input output phase difference is constant (' = ' o ) when the output signal is injection locked to the incident signal. However, when sinusoidal noise at an offset frequency! n is added to the system, ' is no longer constant and the instantaneous output frequency,!, is defined as:! =! o + d' dt : (4.34) It is the variation of ' which generates phase noise in the output signal. As shown in Appendix B, d' dt can be approximated as: where! 0 d' dt '! o 1 A [ V i V o sin(') V n V o cos(')sin(fi)] (4.35) is the difference between the incident frequency and the free running frequency, A = 2Q! r, and fi =! n t + ' n. The input output phase difference can be written as: ' = ' o + ' ffl (4.36) where ' o is the input output phase difference in the absence of noise and is a constant (! o = V i AV o sin(' o ) from (B.10)), and ' ffl is the time variant portionof '. When V n fi V i and V n fi V o the fluctuations of the input output phase difference are very small (' ffl fi 1) and (4.35) can be simplified to:

72 56 Chapter 4: Frequency Dividers where K = d' ffl dt + K' ffl = V n AV o cos(' o )sin(fi) (4.37) V i AV o cos(' o ) V n AV o sin(' o )sin(fi): (4.38) If tan(' o ) fi V i V n, implying that the incident frequency is not at the edge of a phase limited locking range, K can be approximated as: K ' V i AV o cos(' o ) (4.39) which allows simplification of (4.37) to a first order differential equation: d' ffl dt +[ V i AV o cos(' o )]' ffl ' [ V n AV o cos(' o )]sin(! n t + ' n ): (4.40) The noise transfer function from v n to the output phase is shown in Fig From Eq. (4.40) and Fig it is clear that an ILO has the same noise transfer function as a first order PLL. The noise from the incident signal is shaped by the lowpass characteristic of the noise transfer function and the output signal tracks the phase variations of the incident signal within the loop bandwidth ( V i AV o cos(' o )). However, unlike a first order PLL, the loop bandwidth of an ILO is a function of the incident amplitude and is larger for a larger incident amplitude. The interpretation of the noise transfer function is a little different if the noise comes from the ILO itself. Within the loop bandwidth the noise from the ILO is suppressed by the ratio of the noise power to the incident power. Outside the loop bandwidth the noise suppression increases by 20 db per decade of offset frequency and a 1 f 2 phase noise region is observed. The noise behavior in an N-th order ILFD is the same as that of a first harmonic ILO, except that the frequency division operation causes d'ffl to be 1 of that in a dt N first harmonic ILO. So (4.40) for an N th order ILFD can be modified as:

73 4.4: Summary 57 logj ' ffl V n j 20 db=dec V i! n Figure 4.13: Noise transfer function of an ILO. d' ffl dt +[ V i AV o cos(' o )]' ffl = 1 N [ V n AV o cos(' o )]sin(! n t + ' n ) (4.41) where ' o is no longer a simple function of! 0 but is determined by solving the fundamental ILFD equations (4.22) and (4.23). As the division ratio N increases the noise rejection increases proportionally. So in a divide by two ILFD the output close in phase noise is 20log(2) = 6 db lower than that of the incident signal. The fact that the ILFD close in phase noise is determined by the phase noise of the incident signal has important implications for very low power frequency dividers, just as it does for any other frequency divider. 4.4 Summary In this chapter we have discussed different frequency division techniques and explained the tradeoffs and application of each method. We explained that at high frequencies (e.g., higher than f T =5) analog techniques become more attractive than digital methods. Among all analog frequency dividers, injection locked frequency

74 58 Chapter 4: Frequency Dividers dividers can potentially operate at a higher frequency and with a lower power consumption. The reason is hidden in the nature of the injection locked frequency dividers: An ILFD is an oscillator capable of operation at frequencies approaching f max of the technology. We also developed a general theory for injection locked frequency dividers which elucidates the frequency division mechanism of an ILFD based on intermodulation of the input and output signals. This model predicts for the first time the possibility of injection locking failure at large incident amplitudes. It also provides direct design insight onhow to maximize the locking range of an ILFD. Finally we derived a first order differential equation which describes the noise performance of an ILFD.

75 Chapter 5 Experimental injection locked frequency dividers N this chapter we introduce two circuit topologies (single ended and differential) Ifor divide by two injection locked frequency dividers. Both topologies are fully integrated in standard CMOS processes. The single ended topology was initially designed and fabricated as a proof of concept and was not targeted for any specific application nor optimized for power consumption. However, the differential architecture was designed to be used as a tracking ILFD in a 5 GHz frequency synthesizer as will be discussed in chapter 6. The organization of this chapter is as follows. We first describe the two circuit topologies and explain their operation. Since on chip inductors are a critical part of the design we discuss their optimization next. Finally, measurement results followed by a summary conclude this chapter. 5.1 Circuit topologies Fig. 5.1 shows the schematic of a single ended injection locked frequency divider (SILFD). For simplicity the biasing circuitry is not shown in this figure. A Colpitts oscillator forms the core of the SILFD. The incident signal is injected into the gate of M1. Transistors M1 and M2 are used in cascode, mainly to provide more isolation 59

76 60 Chapter 5: Experimental injection locked frequency dividers Vdd Vdd L R i C M2 M1 C2 C load Vi L i C i I bias C1 Figure 5.1: Schematic of the single ended ILFD. between the input and output (drain of M2). Transistor M2 is sized to be smaller than M1 by almost a factor of three to reduce the parasitic capacitance at the output node. As a result a larger inductor can be used to resonate this reduced capacitance. As discussed in section , using a larger inductor increases the locking range. The power consumption is also reduced due to the increased effective parallel impedance of the LC tank, assuming that tank losses are mainly from the inductor. Lastly, L i and C i in the gate of M1 are used to model the LC tank of the preceding LC oscillator. The isomorphism of this circuit with the model in Fig. 4.9 can be understood by observing that transistor M1 functions as the nonlinear block. The incident and output signals are summed across the gate and source of M1 before they excite the oscillator nonlinearity. Therefore, in this circuit f(v i ;v o )=f(v i +v o ). The schematic of a differential ILFD (DILFD) is shown in Fig The incident signal is injected into the gate of M3 and delivered with a sub unity voltage gain to node Vx, the common source connection of M1 and M2. The output signal is fed back to the gates of M1 and M2 and summed with the incident signal across the gates and sources of M1 and M2. In this circuit, node Vx moves at twice the frequency of

77 5.1: Circuit topologies 61 Vdd + Vout Vc M2 Vx M1 I bias Vin M3 R1 Figure 5.2: Schematic of the differential ILFD. the output signal even in the absence of the incident signal. Therefore, this circuit has a dominant second order nonlinearity. As mentioned in section a large quadratic nonlinearity increases the locking range of a divide by two ILFD. Thus the DILFD is a good candidate for a divide by two ILFD when the incident signal is effectively injected into node Vx. To further improve the locking range of the DILFD accumulation mode MOS varactors [29], [30] are used to realize a tracking ILFD (section 4.3.2). Inductors in both circuits are on chip planar spiral inductors with patterned ground shields [31]. The inductors are designed to maximize the locking range of the ILFD and also reduce the power consumption. As mentioned in section the largest practical inductance L maximizes the locking range. However, reduction of power consumption demands maximization of the effective parallel impedance of the RLC tank. Assuming inductors are the main source of loss, the effective

78 62 Chapter 5: Experimental injection locked frequency dividers Cs Cp1 L Rs Cp2 OD Rsi Csi Csi Rsi w Sub (b) s (a) Figure 5.3: a) Top view of a square planar spiral inductor. b) A ß circuit model for spiral inductors. parallel impedance of the tank equals!lq and is thus the largest when the LQ product is maximized. On the other hand the inductor has its largest value when the total capacitance that resonates with it is minimized. Assuming the external capacitances are already minimized, the only remaining parameter is the inductor parasitic bottom plate capacitance. To reduce this latter capacitance, the inductor should be laid out with narrow topmost metal lines. However, the large series resistance of narrow metal strips degrades the inductor quality factor and reduces the LQ product significantly. Therefore, both L and the LQ product may not be maximized simultaneously for an on chip spiral inductor resonating with a fixed capacitance. To design the spiral inductors, we use a ß model for an inductor as reported in [32]. Fig. 5.3 shows the top view of a square planar spiral inductor as well as the ß model used in our design. Design parameters are the inductor metal width (W), metal spacing (s), number of turns (n), and outer dimension (OD). Resistor Rs represents the resistive loss in the inductor metal strips (including skin effect) as well as the substrate magnetic loss (Appendix D, Eq. D.9). Capacitors Cp1 and

79 5.2: Measurement Results 63 Figure 5.4: Die micrograph of the SILFD in a 0.5 μm CMOS technology (0:7 mm 1 mm, including pads). Cp2 model the parasitic capacitance between the inductor layer and the effective substrate (here, the ground shield). The parallel combination of Rsi and Csi model the substrate. If a ground shield is used Rsi and Csi need not be modeled and Cp1 and Cp2 are grounded. Capacitance Cs models both the inter winding capacitance and the capacitance between the inductor top metal layer and the under pass metal used to gain access to the inner terminal of the inductor (Appendix D, Eq. D.3). The inductance L is first approximated with a monomial expression (Appendix D, Eq. D.6) [33], then optimization used to find the maximum inductance such that the LQ product is large enough to satisfy the specified power budget. Notice that maximizing L with a fixed LQ product also minimizes Q. This minimized Q further increases the locking range as discussed in section

80 64 Chapter 5: Experimental injection locked frequency dividers 5.2 Measurement Results Single ended ILFD The SILFD shown in Fig. 5.1 is designed in a 0:5 μm CMOS technology and operates on 2:5 V at a bias current of 1:2 ma. The free running frequency of oscillation is 920 MHz and the incident frequency is around 1840 MHz. The die micrograph of the SILFD is shown in Fig The total die area, including pads, is 0:7 mm 2 (0:7 mm 1 mm). The locking range as a function of incident amplitude is shown in Fig A maximum locking range of more than 190 MHz (11% of the center frequency) is achieved when consuming 3 mw of power. Notice that increasing the incident amplitude initially increases the locking range, as predicted by (4.25). However, as the incident signal goes beyond 250 mv, amplitude condition (4.28) fails prior to the phase condition and the locking range decreases. The maximum achievable locking range at different bias currents is shown in Fig Although this circuit was mainly designed to prove the concept of injection locked frequency division and was not optimized for the minimum power consumption, still a locking range of more than 135 MHz is achieved with less than 600 μa bias current. The phase noise of the SILFD is measured both in free running and injection locked modes (Fig. 5.7). The thin solid line in this figure shows the phase noise of the free running SILFD. The thick solid line is the phase noise of the HP8664A signal generator used as the incident signal. The non solid lines are the phase noise measurement of the SILFD when locked to three different incident frequencies, referred to as middle frequency, phase limited, and amplitude limited curves. The middle frequency curve is the output phase noise measured at an incident frequency in the middle of the locking range. The phase limited and amplitude limited curves are measured when the incident frequency is at the edge of a phase limited and amplitude limited locking range, respectively.

81 5.2: Measurement Results 65 Input referred locking range (MHz) Incident amplitude (V) Figure 5.5: Input referred locking range of the SILFD as a function of incident amplitude. Maximum input referred locking range (MHz) Bias current (ma) Figure 5.6: Maximum input referred locking range of the SILFD as a function of bias current.

82 66 Chapter 5: Experimental injection locked frequency dividers Phase noise (dbc/hz) HP8664A Middle frequency Phase limited Amplitude limited Free running Offset frequency (khz) Figure 5.7: SILFD phase noise measurements. At low offset frequencies the divider output phase noise is almost 6 db lower than the incident phase noise, as is expected from the divide by two operation and predictions of (4.41). However, at higher offset frequencies the excess noise from the divider itself and the following buffers increases the output phase noise. The far out phase noise at the edge of the amplitude limited locking range is even worse than the phase noise of the free running oscillator because of the small oscillation amplitude at this edge. Despite the large phase noise of the free running ILFD, the divider close in phase noise tracks the phase noise of the incident signal. As a result an ILFD can be designed for very low power operation, without sacrificing the noise performance of the system. Also very low Q on chip spiral inductors, with small physical dimensions, can be used in an ILFD.

83 5.2: Measurement Results 67 Figure 5.8: Chip micrograph of the DILFD in a 0.24 μm CMOS technology (345 μm 540 μm) Differential ILFD A differential ILFD of the type shown in Fig. 5.2 is designed in a 0:24 μm CMOS technology. The chip shown in Fig. 5.8 has an area of 0:186 mm 2 (345 μm 540 μm), excluding the pads. In the free running mode, the oscillator is biased with Vdd= 2:0 V and I bias = 600 μa. The free running oscillation frequency as a function of the control voltage (V c ) is shown in Fig The tuning range is about 110 MHz (ß 5% of the center frequency) for a 1:5 Vcontrol voltage variation. For divide by two operation the supply voltage is set to 1:5 V and the tail current is reduced to 300 μa. However, because of the partial rectification of the incident signal the average tail current increases beyond 300 μa. Fig shows the operation frequencies of the divider as a function of the incident amplitude for two different control voltages. For a given incident amplitude the operation region lies between the two ends of each curve in Fig By increasing the control voltage

84 68 Chapter 5: Experimental injection locked frequency dividers 2500 Output frequency (MHz) Control voltage (V) Figure 5.9: Tuning range of the free running voltage controlled DILFD. the resonant frequency of the LC tank increases and moves the operation region up in frequency. Fig shows the locking range as a function of the incident amplitude for two different control voltages. The locking range increases with the incident amplitude but it is not a linear function of the incident amplitude, just as predicted by (4.29). For a given control voltage, a greater than 1150 MHz (ß 24% of the center frequency) input referred locking range is achieved when V i =1:5 V. Addition of tank tuning increases the total achievable locking range to greater than 1260 MHz (ß 26% of the center frequency) at this incident amplitude. Higher incident amplitudes are not tested due to instrument limitations. As expected, changing the control voltage changes only the operation frequencies and not the locking range. Unlike the single ended ILFD reported in the previous section, the locking range in a DILFD is phase limited and monotonically increases with incident amplitudes even as large as 1:5 V. This difference can be attributed to the fact that the voltage gain of M3 in Fig. 5.2 is less than unity and the amplitude of the incident signal at the summing node (the common source connection of M1 and M2) is less than that on the gate of M3. The amplitude limited region of the locking range, which is observed only at

85 5.2: Measurement Results 69 Incident amplitude (V) Vdd=1.5 V Vc=2.0V Vc=1.5V Incident frequency (GHz) Figure 5.10: Operational frequency range of the DILFD for different incident amplitudes and two different control voltages. Input referred locking range (MHz) Vc=1.5V Vc=2.0V Power (mw) Incident amplitude (V) Figure 5.11: DILFD locking range and power consumption as a function of incident amplitude.

86 70 Chapter 5: Experimental injection locked frequency dividers Vdd HP8563E 50 V i DILFD Ext. Amp. On chip Figure 5.12: DILFD phase noise measurement setup. large incident amplitudes, therefore appears at larger input levels. Compounding this effect is that the increased average tail current (in a DILFD) in the presence of a large incident signal changes the DILFD nonlinearity and effectively moves the amplitude limited region of the locking range to larger incident amplitudes. The average power in the DILFD as a function of the incident amplitude is shown in Fig The average power at 400 mv incident amplitude is less than 0:55 mw while the input referred locking range exceeds 600 MHz (> 12%). Fig shows the test setup for the DILFD phase noise measurement. The phase noise measurement results are shown in Fig The solid line shows the phase noise of the HP83732B signal generator used as the incident signal. The dashed line is the phase noise of the free running DILFD. The other two curves are the phase noise of the DILFD when locked to two different incident frequencies. The curve marked as middle frequency is measured when the incident frequency is in the middle of the locking range and the edge frequency curve is measured at the lower edge of the locking range. Like the SILFD, at low offset frequencies the output of the frequency divider follows the phase noise of the incident signal and is 6 db lower due to the divide by two operation. At larger offset frequencies the added noise from the output buffer, the external amplifier (Fig. 5.12), and from the divider itself reduces the 6 db difference between the incident and output phase noise. Phase noise measurements for offset frequencies higher than 300 khz are not accurate due

87 5.2: Measurement Results 71 Phase noise (dbc/hz) HP83732B Free running Middle freqeuncy Edge frequency Offset frequency (khz) Figure 5.13: DILFD phase noise measurements. to the dominance of noise from the output buffer and the external amplifier. As discussed earlier the locking range of the DILFD is always limited by the failure of the phase condition. Therefore, the phase noise degradation observed attheedgeof the amplitude limited locking range of the SILFDisnotan issue for the DILFD. Table 5.1 summarizes the performance of the DILFD. The power consumption of two flipflop based frequency dividers at 5 GHz is also listed for comparison purposes. In a 0:24 μm CMOS technology a simulated SCL flipflop based frequency divider loaded with the same capacitance as in the DILFD, consumes almost an order of magnitude more power than the DILFD with a 600 MHz locking range. The measurement results of a fast flipflop based divider in an advanced 0:1 μm CMOS technology show a power consumption of 2:6 mw at 5 GHz [34] which is still more than four times the power of the 0.24 μm DILFD with a 600 MHz locking range.

88 72 Chapter 5: Experimental injection locked frequency dividers Table 5.1: DILFD performance summary Output frequency tuning 110 MHz ß 5% Input locking range 600 MHz ß 0.55 mw 1000 MHz ß 0.8 mw Technology 0.24 μm CMOS Die area mm 2 Flipflop based divider (for comparison) 0.24 μm CMOS Λ 5 5GHz 0.1 μm CMOS [34] GHz Λ Simulation with SCL flipflops loaded with the same capacitance as in the DILFD Noise transfer function In order to verify the noise dynamics derived in section 4.3.3, the SILFD is injection locked to an incident frequency while a second signal is injected at an offset frequency from the incident frequency. As demonstrated in Fig. 5.14, two sidebands are generated in the output signal spectrum. The sideband power relative to the carrier is measured at different offset frequencies and is shown in Fig and In Fig the incidentpower, P i, is constant and the noise transfer function is measured for three noise power levels, P n. As predicted by (4.41), reducing the noise power by 3dBshifts the noise transfer function curve down by the same amount. The measurements are repeated for different incident powers, while keeping the noise power constant. The results are shown in Fig When the incident power increases by 3 db both the loop bandwidth and the close in noise rejection increase by 3 db, while the far out noise does not change. The noise transfer function measurement results of Fig and 5.16 areinvery good agreement with(4.41). 5.3 Summary In this chapter we presented two circuit topologies for divide by-two injection locked frequency dividers. The single ended ILFD clearly demonstrates the two failure

89 5.3: Summary Power (dbm) Frequency (MHz) Figure 5.14: Sideband generation due to noise injection at an offset from the incident frequency. Noise power below carrier (dbc/hz) P n = 70 dbm P n = 73 dbm P n = 76 dbm Offset frequency (MHz) Figure 5.15: Noise transfer function in the SILFD (P i = 40 dbm).

90 74 Chapter 5: Experimental injection locked frequency dividers Noise power below carrier (dbc/hz) P i = 70 dbm P i = 73 dbm P i = 76 dbm Offset frequency (MHz) Figure 5.16: Noise transfer function in the SILFD (P n = 70 dbm). mechanisms of injection locking. At small incident amplitudes the locking range is limited by the failure of the phase condition, while failure of the amplitude condition is the reason for the loss of injection locking at large incident amplitudes. On the other hand, the locking range of the differential ILFD is always phase limited even for incident amplitude as large as 1:5 V. Therefore, the DILFD has superior phase noise performance over the SILFD at the edge of the locking range for all incident amplitudes. Furthermore, the strong second order nonlinearity of the DILFD extends its locking range in a divide by two operation. The design of the on chip inductors was optimized to increase the locking range while reducing the power consumption. Under this objective, inductors were designed with a maximum inductance, L, and minimum quality factor, Q, foragiven LQ product at the frequency of operation. To extend the locking range of the DILFD even further, the resonant frequency of the output circuit was tuned in a tracking ILFD configuration. The combination of the frequency tuning capability and optimized inductors resulted in a locking range of more than 26% for less than 1 mw of power consumption. The power

91 5.3: Summary 75 consumption of the DILFD is reduced to about 0:5 mw for a 15% locking range (including the frequency tuning of the tracking ILFD).

92 76 Chapter 5: Experimental injection locked frequency dividers

93 Chapter 6 An experimental 5GHz frequency synthesizer I N the previous chapters we discussed system level design issues of a frequency synthesizer. We also studied the design of very low power frequency dividers. In this chapter we use the knowledge of the previous chapters to implement a low power frequency synthesizer forau NIIband WLAN receiver (chapter 2). Frequency synthesizers usually consume a large percentage (20 30%) of the total receiver power (Table 6.1). As mentioned in chapter 3 a typical PLL based frequency synthesizer comprises both high and low frequency blocks. The high frequency blocks, mainly the VCO and first stage of the frequency dividers, are the main power consuming blocks, especially in a CMOS implementation. Therefore, BiCMOS technologies have often been chosen over CMOS, where the VCO and the prescaler are designed with bipolar transistors and the low frequency blocks are CMOS [35]. Off chip VCO's and dividers have also been used as an alternative [7]. However, because of the increased cost neither of these two solutions is suitable for many applications, and a fully integrated CMOS solution is favorable. A dividerless frequency synthesizer [36] which eliminates power hungry frequency dividers is one solution for such low power and fully integrated systems. In this technique an aperture phase detector is used to compare the phase of the reference signal and the VCO output at every rising edge of the reference signal only for a limited time 77

94 78 Chapter 6: An experimental 5GHz frequency synthesizer f rf= GHz + Σ - I LNA LO1=f rf x 16 1 LO2=LO1x Frequency Synthesizer + Σ + Q Figure 6.1: Simplified block diagram of the front end of the U NII band WLAN receiver. window which is a small fraction of the reference period. Thus no frequency divider is required in this PLL. The idea of a dividerless frequency synthesizer, although suitable for systems such as a GPS receiver where only one LO signal is required, is not readily applied to wireless systems which require multiple LO frequencies with a small frequency separation. In chapter 2 we mentioned the increasing demands for WLAN systems that can support data rates in excess of 20 Mb/s with very low cost and low power Table 6.1: Power consumption of fully integrated wireless receivers Reference Receiver power PLL power [37] 115mW 36mW [38],[39] 225mW 51mW

95 6.1: Proposed synthesizer architecture 79 consumption. We also discussed the existing standards for such high data rate systems at 5 GHz. In this chapter we describe the design of an integer N frequency synthesizer as a local oscillator (LO) for a U NII band WLAN receiver. To stay compatible with HIPERLAN, we divide the lower 200 MHz of the U NII spectrum into 8 channels that are 23:5 MHz wide, leaving 12 MHz for guard bands. The minimum signal level in a class C receiver is 70 dbm while the maximum strength of the received signal is 25 dbm (Table 2.2). The large dynamic range and wide channel bandwidth of this system set very stringent requirements for synthesizer phase noise and spurious sideband levels. The synthesizer is fully integrated in a standard CMOS process. The front end of the receiver is described in detail in [40] and its simplified version is shown in Fig This double conversion architecture is known as a Weaver architecture. This architecture rejects the image signal without any external image reject filter. However, it requires fairly accurate quadrature LOs to perform the image rejection. To reject the image by more than 41 db the phase error between the quadrature LOs should be less than 1 ffi [8], assuming zero gain mismatch. 6.1 Proposed synthesizer architecture Our proposed architecture (Fig. 6.2) is an integer N frequency synthesizer with an initial low power divide by two in the PLL feedback path. The prescaler follows the fixed frequency divider and operates at half the output frequency and thus its power consumption is reduced significantly. Furthermore, the first divider is an injection locked frequency divider (chapter 4) which takes advantage of the narrowband nature of the system and trades off bandwidth with power via the use of resonators. To further reduce the power consumption, optimization techniques are used to design the on chip spiral inductors of the VCO and ILFD. Because of the fixed initial divide by two in the loop, the reference frequency in our system is half of the LO spacing and is 11 MHz. Consequently, the loop bandwidth is reduced to maintain the loop stability. This bandwidth reduction helps to filter harmonics of the reference signal (mainly the second harmonic) which

96 80 Chapter 6: An experimental 5GHz frequency synthesizer fref PFD Charge Pump Loop Filter VCO fout M 1 2 Tracking ILFD Program & Pulse Swallow Counters Prescaler N/N+1 Channel Select Modulus Control Figure 6.2: Block diagram of the proposed frequency synthesizer. generate spurs in the middle of the adjacent channels. The drawbacks of a reduced loop bandwidth are an increased settling time and a higher in band VCO phase noise. The higher in band VCO phase noise is not a limiting factor here as the in band noise is dominated by the upconverted noise of the reference signal (section 3.3). The slower settling time is only a problem in very fast frequency hopped systems. The synthesized LO frequency in our system is 16 of the received carrier frequency. This choice of LO frequency not only eases the issue of image rejection 17 in the receiver [40], but also facilitates the generation of the second LO, which is 1 16 of the first LO, with the same synthesizer.

97 6.2: Synthesizer building blocks Synthesizer building blocks Voltage controlled oscillator To generate the accurate quadrature LO signals required for the Weaver architecture we have used the quadrature VCO of Fig. 6.3 a [41]. This VCO consists of two mutually coupled differential VCO's, marked inside the dashed squares. Each VCO is made of two cross-coupled transistors, (M1, M2) and (M3, M4), to generate the negative conductance required to cancel the losses of the RLC tanks. Transistors M5 M8 couple the two VCO's. These two VCO's oscillate at the same frequency but in quadrature phases. The two VCO's, with their coupling transistors, can be pictured as two differential buffers in a ring structure as shown in Fig. 6.3 b. A sustained oscillation of the ring requires a zero phase shift across the ring. The inverting structure of the loop introduces a 180 ffi of phase shift. Therefore, each buffer should introduce an additional 90 ffi phase shift to provide the overall zero phase shift in the ring. The two VCO's thus oscillate in quadrature. As mentioned before the symmetry of the VCO structure defines the quadrature accuracy of VCO outputs and thus the total receiver image rejection. Therefore, it is important to sustain the VCO symmetry in a perfectly symmetric layout. On chip spiral inductors with patterned ground shields [31] are used in this design. The two main requirements for the VCO are low phase noise and low power consumption. If the inductors were the main source of noise, maximizing their quality factor would improve the phase noise significantly. However, in multi GHz VCO's with short channel transistors, inductors are generally not the main source of noise although they are still the main source of loss in the RLC tank. Therefore, a better design strategy is to maximize the effective parallel impedance of the RLC tank at resonance. With a maximized tank impedance the oscillation amplitude is maximized for a given power consumption and thus the phase noise due to the noise of active devices is reduced. Since inductors are the main source of loss in the tank, the LQ product should be maximized to maximize the effective parallel impedance of the tank at resonance, where L is the inductance and Q is the quality factor of

98 82 Chapter 6: An experimental 5GHz frequency synthesizer Vdd I bias Vo Vc + M7 M3 M4 M8 Vdd I bias (b) Vo Vc M5 M1 M2 M6 (a) Figure 6.3: (a) Schematic of the quadrature VCO. (b) Representation of the quadrature VCO as a ring oscillator.

99 6.2: Synthesizer building blocks 83 the spiral inductors. It is important to realize that maximizing Q alone does not necessarily maximize the LQ product, and it is the latter that matters here. To design the spiral inductors, we use the same inductor optimization technique explained in chapter 5 with the objective to find inductors with the maximum LQ product. The inductors in this design are 2:26 nh each with a quality factor of 5:6 at 5 GHz. It is worth mentioning that at 5 GHz, the magnetic loss in the highly doped substrate of the epi process reduces the inductor quality factor significantly. Approximate calculations [42] show that substrate inductive loss is proportional to the cube of the inductor's average diameter (Eq. D.9). Therefore, a multi layer stacked inductor which has a smaller area compared to a single layer inductor with the same inductance may achieve a larger quality factor. We should mention that in this design, inductors are laid out using only the top most metal layer. The varactors in Fig. 6.3 are accumulation mode MOS capacitors [29],[30]. The quality factor of these varactors can be substantially degraded by the gate resistance of the structure, if the varactors are not laid out properly. In this design each varactor is laid out with 21 fingers which are3μm wide and 0:5 μm long. The quality factor of this varactor at 5 GHz is estimated to exceed 60. The losses of the RLC tank are thus dominated by the inductors, as expected Injection locked frequency divider The same differential tracking ILFD discussed in chapter 5 is used in this design and is shown in Fig The only modification is the dummy transistor M4 to provide a symmetric load for the differential VCO which drives the ILFD. The inductors of the ILFD are 10:5 nh with a quality factor of 3:6 at2:5 GHz Programmable frequency divider (ΞM) Fig. 6.5 shows the block diagram of the programmable frequency divider known as a pulse swallow frequency divider. The pulse swallow frequency divider (ΞM) consists of a ΞN=N +1 prescaler followed by a program and swallow counter. Only one CMOS logic ripple counter is used for both the program and pulse swallow counters

100 84 Chapter 6: An experimental 5GHz frequency synthesizer Vdd + Vout Vc M2 Vx M1 I bias R2 M4 M3 R1 Vin Figure 6.4: Schematic of the differential tracking ILFD, with dummy transistor M4 to provide a symmetric load for the differential VCO.

101 6.2: Synthesizer building blocks 85 Prescaler Program Counter f in N/N+1 P f out M MC S Reset Swallow Counter Channel Selection Figure 6.5: Block diagram of the pulse swallow frequency divider. (Fig. 6.6). The program counter generates one output pulse for every P input pulses to the counter. The output of the swallow counter (MC) switches the division ratio of the prescaler and is controlled byfive binary coded channel select bits (Ch1 Ch5). At the beginning of the cycle MC = 1 and the prescaler divides by N +1. After S +1 cycles, with S determined by the channel select bits, MC is set to zero and the prescaler divides by N for the rest of the cycle. Therefore, the overall division ratio is M = NP + S +1. Flipflops FF1 and FF2 in Fig. 6.6 are used to set and reset MC at the falling edges of the Clk. Therefore, the set and reset of MC are independent of the delays of the ripple counter and the logic gates. Also, because of FF2 the system can tolerate a total delay of as large as one Clk cycle before its operation fails. The first step in the design of a pulse swallow frequency divider is to select the values of N, P and S. One constraint in this process is S +1» P. The second constraint is set by the required minimum power consumption. Conventionally a prescaler is designed by cascading dual modulus frequency dividers and fixed frequency dividers to get the desired division ratio (Fig. 6.7). Each dual modulus (e.g., a divide by 2/3) generally burns more than twice the power of a divide by 2 (section 4.1). Therefore, to minimize the power consumption of the prescaler, it should

102 86 Chapter 6: An experimental 5GHz frequency synthesizer clk Program Counter (P=26) R Q T-FF Clk Q R Q T-FF Clk Q R Q T-FF Clk Q R Q R Q T-FF T-FF Clk Q Clk Q Ch1 Ch2 Ch3 Ch4 Ch5 Reset D Q FF1 Clk Q Q Q D FF2 Clk clk clk Swallow Counter (S=1,2,...,24) MC Reset Out Figure 6.6: Block diagram of the program and pulse swallow counters.

103 6.2: Synthesizer building blocks 87 MC In MC Clk 2/3 Q O1 Clk 2 Q Clk 2 Q O2 Out MC D Q FF2 Clk Q D Q FF1 Clk Q Q Clk Figure 6.7: Block diagram of the prescaler. consist of no more than one dual modulus divider, which means N is an integer power of two. Finally the last constraint is the overall division ratio. In this design the overall division ratio of the pulse swallow frequency divider is an integer number between 220 and 227. The selected values of N, P, and S based on the preceding discussions are N =8,P =26,and S is an integer between 11 and 18 to select any of the eight channels. The prescaler consists of one dual modulus divide by 2=3 and two divide by 2 frequency dividers made of SCL flipflops and gates (Fig. 6.7). The modulus control (MC) input selects between divide by 8 and divide by 9. To divide by eight, MC is set to zero and the dual modulus divider divides by two. When MC=1 the dual modulus divider divides by three only once per output cycle and therefore the overall

104 88 Chapter 6: An experimental 5GHz frequency synthesizer In O O2 Out Figure 6.8: Timing diagram of the prescaler over one output cycle when it divides by 9. division ratio is nine. Fig. 6.8 shows the prescaler input as well as outputs of each divider over one output cycle when the prescaler divides by nine. The shaded area in this figure marks the time when the dual modulus divider divides by three and swallows one input cycle. The block diagram of the dual modulus divide by 2/3 is shown inside the dashed square in Fig The advantage of this structure over the conventional implementation of the divide by 2/3 shown in Fig. 4.2 is its simpler and more symmetric layout, rather than speed as mentioned in [43]. To reduce the prescaler power consumption, the current ofeach NOR gate is shared with the following flipflop. Fig. 6.9 shows the circuit implementation of the NOR/flipflop of the dual modulus divider. Unlike the implementation of the NOR/flipflop in [43] this implementation is fully differential and symmetric with respect to both NOR inputs. In addition, no extra reference voltage is required for the NOR gate in our implementation. All of the flipflops, including those used in the CMOS counters, are triggered by the falling edges of their input clocks, allowing a delay ofasmuch as half the period of the input of each divider. With this arrangement we guarantee overlap between O 2, Out, and MC (Fig. 6.7) at the right time and prevent aracecondition.

105 6.2: Synthesizer building blocks 89 Vdd Vdd R R R R Q Q A B A B B A Clk Clk I bias Figure 6.9: Circuit implementation of the NOR/flipflop of the dual modulus divider in the prescaler.

106 90 Chapter 6: An experimental 5GHz frequency synthesizer R D Q FF1 Clk Q Reset U V Reset D Q FF2 Clk Q D Figure 6.10: The block diagram of the phase/frequency detector Phase/frequency detector Fig shows the block diagram of the phase/frequency detector. Flipflops FF1 and FF2 are falling edge triggered D flipflops with their D input connected to Vdd. The clock of FF1 is connected to the reference signal, R, and FF2 is clocked with the output of the program counter, V. If the falling edge of R arrives before the falling edge of V, output U is set to speed up the VCO. In a different scenario if the falling edge of V arrives prior to the falling edge of R the VCO is faster than the reference signal and D is set to slow down the VCO. In either condition the falling edge of the late signal resets both U and D. The next cycle starts with the next falling edge of V or R. The two inverters in the reset path generate enough delay to eliminate the dead zone of the charge pump [44]. The implementation of the phase/frequency detector at the gate level is shown in Fig In order to reduce the skew between the complementary output signals, (U, U) and (D, D), complementary pass gates are used to match the delay of a single inverter in the output stage of the phase/frequency detector (Fig. 6.11).

107 6.2: Synthesizer building blocks 91 R Reset U U D V D Phase/frequency detector Output stage Figure 6.11: The phase/frequency detector with reduced skew between the complementary outputs Charge pump and Loop filter Fig shows the circuit diagram of the charge pump and loop filter. In this charge pump the up and down current sources are always on and transistors M1 M4 are used as switches to steer the current from one branch of the charge pump to the other. The charge pump has a differential architecture, but only a single output node, O p, drives the loop filter. To prevent node O n from drifting to the rails when neither of the up and down signals (U and D)isactive, a rail to rail unity gain buffer of the kind shown in Fig is placed between the two output nodes. This buffer keeps the two output nodes at the same potential and thus reduces the systematic charge pump offset. Transistors M5 M8 are used to reduce the charge injection into the VCO control line by the up and down signals. The power of the synthesizer spurious sidebands is thereby reduced. To compensate the finite output impedance of the up and down current sources and match their currents more precisely over all output voltages, the up and down currents are monitored in a replica circuit. A feedback network measures the output voltage, V O p, and compares it with the voltage of the replica circuit, Vr, and thereby

108 92 Chapter 6: An experimental 5GHz frequency synthesizer Wp Wp U Wp M3 M7 I Up M4 M8 U C1 Vdd vco C2 C3 Vr O n 1 O p R1 R3 Vc M5 M6 Loop filter M1 D Wn 2Wn Wn M2 I Down D Replica bias Feedback network Charge pump Figure 6.12: Schematic of the charge pump and loop filter. Vdd In M3 I M4 Out M1 I M2 Figure 6.13: Schematic of the rail to rail unity gain buffer used in the charge pump.

109 (I D I U )=I D Λ 100% 6.3: Measurement Results V O p (V) Figure 6.14: Percentage of the systematic error between up and down currents as a function of the output voltage. equates the up and down currents at every output voltage. Fig shows the simulated systematic percentage mismatch between the up and down currents as a function of the output voltage. The percentage error for 0:25 V» V O p» 1:75 V is less than 0:05% and increases to less than 2% for 0:1 V» V O p» 1:8 V. With the loop filter shown in Fig we have a fourth order PLL. Table 6.2 summarizes the values of the loop parameters. The loop has a phase margin of 49 ffi. As shown in chapter 3 a phase margin of about 50 ffi minimizes the loop settling time for a given loop bandwidth. With this phase margin and a crossover frequency of 60 khz the settling time to a 10 ppm accuracy is less than 35 μs. Fig shows the calculated VCO phase noise due to the thermal noise of resistors R 1 and R 3 using Eq and The calculated contribution to VCO phase noise at 22 MHz offset frequency is 149 dbc=hz, which is negligible compared to the intrinsic noise of the VCO.

110 94 Chapter 6: An experimental 5GHz frequency synthesizer Table 6.2: PLL parameters Parameter K vco I p C 1 C 2 C 3 R 1 R 3 PM Ω c t s Value 360 MHz/V (Average) 500 MHz/V (Maximum) 3 μa 42 pf 3.5 pf 2.2 pf 170 kω 64.5 kω 49 ffi 60 khz < 35μs Phase noise (dbc/hz) noise of R1 noise of R3 total noise Offset frequency (Hz) Figure 6.15: Simulated VCO phase noise due to the thermal noise of the loop filter resistors.

111 6.3: Measurement Results 95 Tracking ILFD Prescaler VCO PFD Counters Loop Filter Charge Pump Bias Figure 6.16: Die micrograph of the 5 GHz frequency synthesizer in a 0.24 μmcmos technology (1 mm 1:45 mm). 6.3 Measurement Results The frequency synthesizer is designed in a 0:24 μm CMOS technology. Fig shows the die micrograph of the synthesizer with an area of 1 mm 1:45 mm, including pads. The VCO layout is symmetrical (Fig. 6.16) to minimize the phase error between the VCO quadrature outputs. The synthesizer can operate with a single 2 V supply. However, to demonstrate the feasibility of sub 2 V analog design in a conventional CMOS process, the analog blocks (VCO, ILFD, and prescaler) are supplied by 1:5 Vwhile the digital portions of the synthesizer are supplied by 2V.