A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization

Transcription

1 A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization 유병민 High-Speed Circuits & Systems Lab. 1/19

2 Content 1. Introduction 2. PLL jitter analysis 3. Design examples 4. Experimental results 5. Conclusion 2/19

3 Introduction - Individual PLL component design to reduce low jitter PLL - Low-noise VCO - Deadzone-free PFD - Zero-offset charge pump circuits - Low-noise frequency divider - Overall noise performance of the PLL not only individual component but also heavily depends on the choice of the loop bandwidth - Time-domain analysis - Natural way of understanding PLL dynamics - Direct estimation of timing jitter - Nonlinear effects 3/19

4 Major jitter - External reference input noise - Thermal noise, crosstalk, shot noise - VCO internal noise - Device-inherent noise (1/f noise, thermal noise), power supply noise - Phase Detection noise - Nonideal characteristics (dead zone, current mismatch effects, charge injection) - VCO control voltage noise - Thermal noise, power supply noise 4/19

5 Trade off Loop bandwidth decrease External input noise Locking time Internal VCO noise Loop bandwidth increase - Optimization of loop bandwidth sufficient noise reduction (internal VCO noise, input noise) 5/19

6 Assumption and analysis flow Assumption for analysis Phase noise relatively small (loop: linear) Loop filter is first order (C 1 >>C 2 ) Reference signal >> zero of loop filter, loop bandwidth of PLL Analysis flow S-domain represent Z-domain transform Discretetime domain RMS value of timing jitter 6/19

7 S-domain S-domain represent Z-domain transform Discretetime domain RMS value of timing jitter Transfer function of output noise (VCO noise) + N: value of output divider (= /): Phase detection noise : VCO gain H(s): transfer function of loop filter I s : charge pump current T (= /): period of VCO s output = 7/19

8 Z-domain S-domain represent Z-domain transform Discretetime domain RMS value of timing jitter output noise caused by all input noise Θ = Z-domain transformation K +ΔI H s +T ΔV N Θ z = N+K K H z Θ z + N K K H (z) M N+K K H (z) Θ z + K K H z N+K K H z ΔI (z) 1 NK + 1 z N+K K H z T () +Θ 8/19

9 Z-domain S-domain represent Z-domain transform Discretetime domain RMS value of timing jitter Impulse-invariant transformation (ideal sampler, zeroth-order-hold, loop filter, VCO transfer(without gain)) H z = 1 z Z L () = ( + )/ a: value of resistor (= 1/ ): zero of loop filter : 1 + Z-transformation H s s 1+ 2 (1 /2) 1 Θ, (z) Θ (z) = 1 z 1 1 ε z Θ, (z) Θ (z) = N εz M 1 1 ε z Θ, (z) ΔI (z) = N εz K 1 1 ε z Θ, (z) ΔV (z) =K 1 T 1 1 ε z 9/19

10 Discrete-time domain & RMS value S-domain represent Z-domain transform Discrete-time domain Θ, = Θ = 2πδ /T (unit step phase jump) RMS value of jitter, Discretetime domain RMS value of timing jitter E[Θ (nt)] = δτ + ΔV + ΔV + τ,τ,δ,δ : RMS value of τ,τ,δ,δ = / << 1 (assumption) 10/19

11 Discrete-time domain & RMS value S-domain represent E[Θ (nt)] = δτ + ΔV + Z-domain transform + ΔV Loop bandwidth: / ω Loop bandwidth for minimization of the PLL jitter equation Discretetime domain RMS value of timing jitter = /19

12 Design example - CMOS MHz clock generator (0.6-μm CMOS tech.) - Individual PLL components: minimized jitter design - Voltage reference, driver circuit: effect of power supply fluctuation reduction - VCO: critical component more carefully designed 12/19

13 Design example VCO without reference voltage VCO with reference voltage Reference voltage - VCO frequency: negative temperature dependency - Reference voltage: positive temperature dependency Reference voltage cancel VCO negative temperature dependency 13/19

14 Experimental result Technology 0.6μm, 3-metal, 2-poly CMOS Area 4mm 2 Frequency range V power supply Output jitter 3.1 ps rms, 22 Supply voltage range 3.0~5.0 V Output duty cycle 50.7% Current consumption 13.5 ma from 3.3 V Summary of performance output waveform of the prototype clock generator 14/19

15 Experimental result - Jitter simulation setup - Each noise source: white gaussian noise model (in C language model) - Loop filter: adjusted for each different loop bandwidth - Simulation procedure - Loop B.W, loop filter value (fixed VCO gain, charge pump current etc.) - RMS output jitter: calculated for each bandwidth 15/19

16 Experimental result - Estimation of the timing jitter based on jitter analysis - Simulation results of timing jitter - Theoretical estimation agree with simulation 16/19

17 Experimental result - Measured jitter as a function of loop bandwidth - Optimization and other point of loop bandwidth 17/19

18 Conclusion - Analysis for optimization loop bandwidth for low noise - Proposed phase model can be used for best noise performance in various application such as CDR and PLL - Computer simulation using a charge-pump PLL model and measurement of 0.6-μm clock generator show good agreement with the theoretical predictions. 18/19

19 Thank you for listening Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea 19/19