CMOS Circuit for Low Photocurrent Measurements

Transcription

1 CMOS Circuit for Low Photocurrent Measurements W. Guggenbühl, T. Loeliger, M. Uster, and F. Grogg Electronics Laboratory Swiss Federal Institute of Technology Zurich, Switzerland A CMOS amplifier / analog-to-digital (A/D) converter for the measurement of ultralow currents like photocurrents down to the subpicoampere range and with a bandwidth of some khz is presented. Double sampling of the integrated current by a window comparator eliminates clockfeedthrough, kt/c-noise as well as nonlinearities of the amplifier, which is operated in a switched-current like mode. The circuit operates with a superimposed signal bias and periodic zero signal (dark current) calibration. The dynamic range can be expanded to five decades if only relative precision of the A/D conversion is important. I. Introduction The classical way of photocurrent measurement bases on a transresistance amplifier used as a current-to-voltage converter [1]. Fig. 1 shows a simplified version of this circuit cascaded by a switched integrator which serves as noise filter as well as sample-and-hold (S/H) circuit for the output A/D conversion. The capacitor C f across the feedback resistor R f of the input stage may serve for antialiasing or the stabilization of the feedback loop. The photodiode is represented by a current source i s and a parallel capacitor C s. The achievable current sensitivity of this circuit is mainly dominated by the noise of the feedback resistor R f. Represented by the noise equivalent signal current i seq at the input terminal when the signal-to-noise ratio is unity (S/N = 1), i seq can be approximated by 4kT iseq R B s = d 1 B s, (1) f where B s is the signal bandwidth, k the Boltzmann constant and T the temperature in degrees Kelvin. B s is determined by the sampling rate f s = B s of the S/H switch S 1. Equation (1) is a worst case approximation which assumes integration of white noise on capacitor C 1 whereas in reality the noise produced by R f is lowpass-filtered by C f. The respective reduction of i seq is not significant however, if practical values of C f are considered. Approximation (1) is valid as long as the noise contribution of the operational amplifier A 1 is at least one decade R f C f S 1 i s C s 1 A 1 R 1 C 1 3 A U 0 Fig. 1. Transresistance amplifier with sample-and-hold circuit.

2 smaller than the noise originating from R f. This condition is fulfilled in realistic circuits if 04. ktrf v neq <, () 1 πrcb f s s + ( ) where v neq is the spectral noise voltage density of the operational amplifier. Whereas () can be fulfilled with today s operational amplifiers in a wide field of applications, CMOS integration of the circuit fig. 1 poses different problems if ultralow currents have to be measured: - Very high values for the feedback resistor R f are required, i.e. R f = 50 MΩ with B s = 500 Hz for i seq = A. - Integration of the second stage with operational amplifier A involves either very high resistor or very high capacitor values. Therefore alternative solutions have to be found for CMOS integrated circuit concepts. II. Current Integration Based Circuit A simplified version of this novel sampled signal circuit is shown in fig.. After reset of the charge on C 1 by S 1, similar to the switched-current technique [,3], the input current i i is integrated on C 1 according to idt it vi = i i, (3) C1 C1 and the output voltage (in the small signal mode) yields itg R vo i m1 L, (4) C1 where g m1 is the transconductance of transistor T 1. This ramp signal is further processed by a window comparator / counter which delivers the time difference between the two level crossings of the comparator t VC1 a ig i m1rl ii = =, (5) which is inversely proportional to the input current i i. In (5) V is the voltage difference between the two comparator levels and a = VC 1 /g m1 R L. i i 1 I 0 S 1 S i L R L t Window Comparator Counter S 0 C 1 T 1 V 0 Processor i s I B U B1 Fig.. Photocurrent measurement circuit consisting of photocurrent source with superimposed signal bias, amplifier, window comparator with counter, and processor.

3 Ultralow current measurement by integration requires a superimposed bias current I B in order to keep a minimum sampling rate independent of the signal current and to enable a zero signal current calibration, which is applied alternatively with the signal measurement. Equation (5) then yields a t = is + IB and the ratio i s /I B can be determined by two time measurements is IB ( ), (6) tc0 t = m. (7) tm t C0 and t m correspond to t measurements with I B alone and i s +I B respectively. The size of I B is a compromise between noise and dynamic range of the system. (See also section III.) If shot noise with spectral density i n = qi B is accompanying I B, it becomes the dominating noise contribution of the circuit in fig., which approximates the noise equivalent signal current according to iseq qibbs = qa Bs = d Bs, (8) if I B» i seq and q is the electron charge. The assumption of shot noise is reasonable for I B generated by photocurrents or current mirrors operated in the subthreshold region. Equation (8) is only valid if the noise contribution of T 1 can be kept reasonably small, i.e. if ktg f B qi m s B» 8 1) 1 ω, (9) T where ω T is the transit frequency of the input node 1 and f is the bandwidth of node in fig.. A comparison of (1) and (8) yields a similar dependence of i seq on the signal bandwidth B s. Practical design values show that realization problems favour the integration method in the case of very low signal currents, since extremely high resistor values are usually required in the transresistance solution. As an example, circuit fig. 1 yields i seq = A with R f = 50 MΩ and B s = 500 Hz, while i seq = A is achieved with I B = 10 pa and B s = 500 Hz using current integration according to fig.. III. Dynamic Range In many applications, i.e. measuring techniques, one is only interested in the relative resolution of the A/D converter, i.e. only in the most significant bits at high signal levels and in the least significant bits at low current levels. The clock frequency requirements of the counter measuring t at the comparator output profits to a great extent from such a reduced resolution requirement at high signal levels. However the 1/i i -law limiting the resolution of the t measurement at high i s is far from the optimum µ-law usually applied for data compression in the telephone network. The resolution P of the i s measurement based on a t=a/(i s +I B )-law with a counter operating at clock frequency f c yields is i P s 1 I = = af B c is IB is I + 1. (10) B In fig. 3 this limitation of the resolution P as well as the signal-to-noise ratio curve S/N is plotted against the increasing signal current i s. As long as i s «I B, noise is dominated by the fluctuations of I B and S/N grows proportional to i s. At high signal currents i s > I B, S/N is limited by the fluctuations accompanying i s, which reduces the slope of the S/N curve. A constant S/N results at i s» I B, if the reduction of the integration time t at high i s is considered as well. The steep decay of the P values and the saturation of the S/N curve at high i s can be circumvented if a multiple readout of the t value (oversampling) is applied during a sample interval at high signal currents. The dashed curves P * and S/N * in fig. 3 reflect this modified procedure. 1) It is furthermore assumed that three transistors (T 1 and two current mirrors) contribute to node.

4 10 5 P S/N S/N* i seq /I B S/N P min P S/N P P* i s /I B Dynamic Range Fig. 3. Linear signal-to-noise ratio S/N and resolution P of a photocurrent measurement circuit with the following values: bias current I B = 1 na, a = 10-1 As, sampling period t = 1 ms, counter clock frequency f c = 16 Mhz, minimum relative resolution at high signal levels P min = S/N * and P * represent the multiple readout method. Assuming a fixed resolution requirement P min at high currents, a dynamic range can be defined according to fig. 3. Using different bias currents or parallel signal processing paths with different amplification factors, the dynamic range of the system can be further improved with respect to the basic circuit described above. IV. Hardware Implementation and Experimental Results The critical parts of the circuit fig. (i.e. the signal current source and the integrating amplifier) were implemented in a 1µ-n-well-CMOS technology with a photodiode as a signal source. A high speed counter instrument with a clock speed well above the application requirements was used in order to verify the various formulae used for the transient noise process in sampled data systems. Several nonidealities of the components had to be considered for the detailed circuit design. Some of these problems are listed below: - Clockfeedthrough of the reset switch as well as kt/c-noise [4] of the input capacitor C 1 produce an offset voltage which is basically canceled by the window comparator. However this offset must not exceed a certain limit in order to keep the supply voltage at 3.3 V. - The nonlinearity of the transistor amplifier T 1 is canceled by the periodic comparison with a zero signal or reference signal measurement, because the time measurement by the window comparator corresponds to a fixed charge difference Q on C 1. However this is true only as long as V and the transfer function across T 1 do not change between the two measurements and therefore guarantee the same a = t i i i independent of nonlinearities. A high offset difference within a measurement pair may violate this condition if the output conductance g o at node is not low enough. For this reason transistor T 1 and the current source I 0 have been built with regulated cascode circuits [5,6], and some special means like dummy switch accompanying S 1 and an offset compensation stage [7] were used in the prototype circuit.

5 U B U B U B 3 1 T 1 R L U B C 1 U B1 Amplifier Stage Offset Compensation Stage Photocurrent Source Fig. 4. Photocurrent measurement amplifier with specially designed photocurrent source and offset compensation stage. Regulated cascode circuits are drawn as single transistors. Noise Equivalent Signal Current i seq [A] B s [khz] Signal Bandwidth Fig. 5. Measured noise equivalent signal currents of prototype circuit compared with theory.

6 - In a first version of the circuit the signal source photodiode was connected across the input terminal 1 and ground. If very low signal currents have to be detected, the thermal reverse current of the diode masks the photocurrent. A specially designed circuit, which keeps the voltage across the photodiode at zero volts and converts its current into a current source without additional noise, had to be used. Fig. 4 shows a more detailed circuit diagram which contains this modified signal source and the offset compensation stage, but which is still drawn with single transistors instead of regulated cascodes for simplicity. The noise t n accompanying the t measurement was determined, from which the noise equivalent signal current i seq can be calculated according to t iseq = n t a B s. (11) These experimental results are compared in fig. 5 with the theoretical performance predicted by (8), where only the shot noise of the bias current I B is considered and the noise of the amplifier T 1 is neglected. Flicker noise has a minor influence since it is reduced by the double sampling process of the window comparator. Careful shielding is necessary against the magnetically induced currents. References [1] R.G. Meyer and R.A. Blauschild, A wide-band low-noise monolithic transimpedance amplifier, IEEE Journal of Solid-State Circuits, vol. sc-1, pp , August [] S.J. Daubert, D. Vallancourt, and Y.P. Tsividis, Current copier cells, Electronics Letters, vol. 4, pp , December [3] J.B. Hughes, N.C. Bird, and I.C. Macbeth, Switched currents - a new technique for analog sampled-data signal processing, IEEE International Symposium on Circuits and Systems, pp , May [4] W.M. Leach, Fundamentals of low-noise analog circuit design, Proceedings of the IEEE, vol. 8, pp , October [5] E. Säckinger and W. Guggenbühl, A high-swing, high-impedance MOS cascode circuit, IEEE Journal of Solid-State Circuits, vol. 5, pp , February [6] C. Toumazou, J.B. Hughes, and D.M. Pattullo, Regulated cascode switched-current memory cell, Electronic Letters, vol. 6, pp , March [7] W. Guggenbühl, J. Di, and J. Goette, Switched-current memory circuits for high-precision applications, IEEE Journal of Solid-State Circuits, vol. 9, pp , September 1994.