An Fpga Implementation Of N/N+1 Prescaler For A Low Power Single Phase Clock Distribution System

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1 An Fpga Implementation Of N/N+1 Prescaler For A Low Power Single Phase Clock Distribution System V Satya Deepthi 1, SnehaSuprakash 2, USBK MahaLakshmi 3 1 M.Tech student, 2 Assistant Professor, 3 Assistant Professor V.S.Lakshmi Engineering College for Women, Kakinada, India deepthisrivatsavaya@gmail.com Abstract: In the VLSI design clock distribution in an IC is very important as it deals with 70% of the power consumption. This paper deals with the design of prescaler to reduce the power consumption by the clock. A prescaler is used to reduce a high frequency electrical signal to a low frequency by integer division. Demand for low power circuits increased in conjunction with a higher level of integration. A multiband flexible divider is used to reduce the power consumption. The proposed design consists of a wideband multimodulous prescaler which divides the input frequency. Two flip-flops and different logic gates are embedded between the flip-flops to achieve two ratios and also to reduce the switching power and short circuit power in the prescaler. Prescalers are typically used at very high frequency to extend the upper frequency range of frequency counters, phase locked loop (PLL) synthesizers, and other counting circuits. The design doesn t require any extra flip-flop, thus saving a considerable amount of power. Reduction of power consumption and delay is very important for high speed low power applications. The proposed prescaler based approach reduces the area and power significantly. A 32/33 prescaler, 47/48 prescaler along with a multimodulous 32/33/47/48 prescaler which incorporates the proposed 2/3prescaler are designed and implemented. The proposed system can be simulated using Modelsim for logical verification, Xilinx ISE tool for synthesizing and the Verilog language is used. Index Terms Prescaler, Flexible Divider, Multimodulous Prescaler, Flip-Flops I. Introduction A dual-modulus prescaler is one that has the ability to selectively divide the input frequency by one of two (normally consecutive) integers, such as 32 and 33. The frequency synthesizer, usually implemented by a phase-locked loop (PLL), is one of the power-hungry blocks in the RF front-end and the first-stage frequency divider consumes a large portion of power in a frequency synthesizer. The integrated synthesizers for WLAN applications at 5 GHz consume up to 25mW in CMOS realizations, where the firststage divider is implemented using an injection-locked divider which consumes large chip area and has a narrow locking range which allows higher operating frequencies but uses more power. Dynamic latches are faster and consume less power compared to static dividers. The TSPC and E-TSPC designs are able to drive the dynamic latch with a single clock phase and avoid the skew problem. The frequency synthesizer uses an E-TSPC prescaler as the first-stage divider, but the divider consumes around 6.25mW. Most IEEE a/b/g frequency synthesizers employ SCL dividers as their first stage, while dynamic latches are not yet adopted for multiband synthesizers. In this paper, a dynamic logic multiband flexible integer-n divider based on pulse-swallow topology is proposed. In general a divide-by-n/n+1 c o u n t er consist of flip flops and some extra logic implemented using logic gates. Various flip-flop based designs have been proposed to improve the operating speed of dual-modulus prescalers. These designs suffer from large load capacitance which limits the maximum operating frequency Page 1360

2 which in turn increases the power consumption. Therefore, dynamic and sequential circuit techniques or clocked logic gates such as, True Single Phase Clocks (TSPC) have to be used to reduce the circuit complexity, power dissipation and increase the operation speed. TSPC logic based designs can be further enhanced by using the Extended True Single Phase Clock (E-TSPC) logic. Frequency dividers (FDs) also called prescalers are used in many communications applications such as frequency synthesizers, timing-recovery circuits and clock generation circuits. Figure 1: PLL Block Diagram The prescaler is employed in the feedback path of the synthesizer, takes a periodic signal and generate a periodic output signal whose frequency is a fraction of the input frequency. The prescaler is one of the most critical blocks in the frequency synthesizer since it operates at the highest frequency and consumes large power. Thus the power reduction in the first stage of the prescaler is important in realizing a low power frequency synthesizer. Dual modulus prescalers are key parts in the frequency synthesizers used in cordless and cellular phones. Figure 1 shows the block diagram of a typical phase-locked loop (PLL) synthesizer. The output signal of the voltage-controlled oscillator (VCO) is applied to the dual modulus prescaler which acts as a divider by P or (P+1), respectively. It was the goal of this work to design a dual-modulus prescaler that operates up to more than 2 GHz to include the frequency bands used for the DECT, PCS and DCS standards. Main demands were operation with a supply ranging from below 2.7 V to at least 5.5 V and extremely low power dissipation. Since it was decided to mount the chip in a tiny SOT363 SMD package, which measures only approximately 1.25 mm by 2 mm, the chip size was also restricted. The SOT363 package has six pins. Two of these are internally connected and used for ground. The remaining pins are needed for Vcc, Input, Output and Modulus Control. This means that a differential input found in many circuits or a selection of different divider ratios (e.g. 64/ 65 and 128/ 129) is not possible due to the limited number of pins. II. Dual Modulous Prescalers The complexity of the N counter in PLL frequency synthesizers has grown over the years. In addition t o a straightforward N counter, it has evolved to include a prescaler. This structure, illustrated earlier in Figure has developed as a solution to the problems inherent in using the basic divide-by-n structure to feed back to the phase detector when very high-frequency outputs are required. For example, suppose a 900 MHz output is required with 10 khz channel spacing. A 10 MHz reference frequency might be used, with the R- divider set at Then, the N-value in the feedback would need to be of the order of This would need a 17-bit counter capable of dealing with an input frequency of 900 MHz.To handle this range, it makes sense to precede the programmable counter with a fixed counter element (the prescaler), to bring the very high input frequency down to a range at which standard CMOS will operate. However, using a standard prescaler introduces other complications. The system resolution, or the effective channel spacing, is now degraded by P, the modulus of the prescaler. This issue can be addressed by using a dual-modulus prescaler. It has the advantages of the standard prescaler but without any loss in system resolution. A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. By using the dual-modulus prescaler with an S and P counter one can still maintain an output resolution specified by the input to the PLL. As long as the S counter ha s not timed out, the prescaler divides down by N +1. So, both the S and P counters will count down by 1 every time the prescaler Page 1361

3 counts (N + 1) VCO cycles. This means the S counter will time out after ((N + 1) S) VCO cycles. At this point the prescaler is switched to divide-by-n mode. The P counter still has (P - S) cycles to go before it times out. So after ((P - S) N) more cycles, the system is now reset to the initial condition. III. Conventional Designs Dual-modulus or multi modulus division gives the flexibility to select channels on the basis of the number of times each of the moduli is selected. A.WIDEBAND E-TSPC 2/3 PRESCALER The dual-modulus prescaler (DMP) divides the VCO frequency by either N, or N+1, depending on the value of modulus control. In this project, N was chosen to be 15 and the circuit was designed to divide by 16 when modulus control is low and by 15 when modulus control is high. The DMP was designed as a finite state machine with 16 possible states. Four flip-flops were required to generate the 16 states, and next-state generation logic was used to cycle through the states on each cycle of the input signal from the VCO. The implementation of the DMP is provided in figure. divided by 16. These results suggest that the dual-modulus prescaler operates as designed and intended. B. Multi Modulus32/33/47/48 Prescaler The proposed wideband multimodulus prescaler which can divide the input frequency by 32, 33, 47, and 48 is shown in Fig. 4. It is similar to the 32/33 prescaler used, but with an additional inverter and a multiplexer. The proposed prescaler performs additional divisions (di -vide-by-47 and divide-by-48) without any extra flip-flop, thus saving a considerable amount of power and also reducing the complexity of multiband divider which will be discussed in Section V. The multimodulus prescaler consists of the wideband 2/3(N1/N1+1) prescaler [10], four asynchronous TSPC divide-by-2 circuits ((AD) =16) and combinational logic circuits to achieve multiple division ratios. Besides the usual Signal for controlling (N1/N1+1) divisions, the additional control signal Sel is used to switch the prescaler between 32/33 and 47/48 modes. Figure 2: Wideband Prescaler When the modulus control signal is low, all 16 states are possible; however, setting modulus control high causes the circuit to skip the zero state. Since only 15 states are used, the DMP divides by15 when the modulus control signal is high. The use of the differential MCML logic gates is evident. In addition, the three-input OR gate indicated in Figure 2 was implemented using 2 two-input OR gates. Figure provides the simulation results for the DMP with modulus control set to logic 0. As expected, the frequency of Slow CLK is equal to the input frequency Figure 3: Multimodulous Prescaler A. Case 1: Sel= 0' When Sel= 0', the output from the NAND2 gate is directly transferred to the input of 2/3 prescaler and the multimodulus prescaler operates as the normal 32/33 prescaler, where the division ratio is controlled by the logic signal. If MC=1, the 2/3 prescaler operates in the divide-by-2 mode and when MC=0, the 2/3 prescaler operates in the divide-by-3 mode. If MOD=1, the NAND2 gate output switches to logic 1 (MC=1) and the wideband prescaler operates in the di-vide-by-2 mode for entire operation. The division ratio N performed by the multimodulus prescaler is Where N1=2 and AD=16 is fixed for the entire design. If, for 30 input clock cycles MC remains at logic 1, where wideband prescaler operates in divide-by-2 mode and, Page 1362

4 for three input clock cycles, MC remains at logic 0 where the wideband prescaler operates in the divide-by-3 mode. The division ratio N+1 performed by the multimodulus prescaler is B. Case 2: Sel=1 When Sel=1, the inverted output of the NAND2 gate is directly transferred to the input of 2/3 prescaler and the multimodulus prescaler operates as a 47/48 prescaler, where the division ratio is controlled by the logic signal MOD. If MC=1, the 2/3 prescaler operates in divide-by-3 mode and when MC=0, the 2/3 prescaler operates in divide-by- 2 mode which is quite opposite to the operation performed when Sel= 0'. If MOD=1, the division ratio N+1 performed by the multimodulus prescaler is same as (4) except that the wide -band prescaler operates in the divide-by-3 mode for the entire operation given by If MOD=1, the division ratio N performed by the multimodulus prescaler is Iv. Multiband Flexible Divider The single-phase clock multiband flexible divider which is shown in Fig. 1 consists of the multimodulus 32/33/47/48 prescaler, a 7-bit programmable S-counter and a 6-bit swallow P-counter. The multi modulus 32/33/47/48 prescaler is briefly discussed in Section IV. The control signal Sel decides whether the divider is operating in lower frequency band (2.4 GHz) or higher band ( GHz). A. Program Counter The program counter is responsible for counting P pulses of SlowCLK before outputting a pulse to the phase/frequency detector and reset- ting itself and the swallow counter. The implementation used in this project, using a 7-bit ripple counter, a 7-bit comparator, and a zero-detector is shown in Figure. Figure 5: Program Counter The ripple counter is clocked by SlowCLK, and increments its count by one each clock cycle. At each stage, the 7-bit comparator compares each count bit to the corresponding bit in the control signal, and outputs a 0 for each equal bit. When the zero-detector detects equivalence in all of the 7 bits, indicating that the desired count has been reached, Fout is driven high. On the next clock cycle, the program counter is reset to zero and the count is re- started.the ripple counter is implemented using 7 cascaded D- type flip-flops, each arranged in a toggle configuration. The output of each flip-flop is used to clock the next flip-flop. Since the output of each flip-flop inverts on every clock cycle, each flip-flop essentially divides its clock by two, causing the next stage of the ripple counter to be clocked at half the rate of the previous flip flop. Each flip-flop was designed to respond to the falling edge of its clock, when the output of the previous stage changes from a 1 to a 0. In this way, an incrementing binary count is achieved with the outputs of each flip- flop forming the bits of the count. B. SWALLOW COUNTER The swallow counter, as indicated in the figure is used to count S pulses of SlowCLK before asserting the modulus control signal and changing the modulus of the DMP to N. Figure 4: Multiband Flexible Divider Page 1363

5 operating frequency of 6.5 GHz [10] and the multimodulus 32/33/47/48 prescaler designed using wideband 2/3 prescaler has a maximum operating frequency of 6.2 GHz. Figure 6: Swallow Counter By looking at Figure, the similarities between the swallow counter and the program counter are apparent. Once again, the count (6-bits in this case) is maintained using a ripple counter comprised of cascaded flip-flops clocked with SlowCLK. In addition, a comparator compares each count bit with its corresponding bit in the control signal, and a zero-detector asserts modulus control when all bits are equal. However, the swallow counter does not reset when the count is reached, but masks the input clock us- ing an AND gate connected to the inverse of modulus control. As a result, the ripple counter stops counting when the count is reached, and the state of the circuit is maintained until a reset signal (SwallowRST) is received from the program counter. Since the swallow counter contains 6 bits, it is capable of any count from 0 to 64. Once again, the control signal must be set to S-1, since the zero-state is included in the count. V. Simulation Results The simulations of the designs are performed using MODELSIM. The simulation results show that the wide band 2/3 prescaler has the maximum operating frequency of 8 GHz with a power consumption of 0.92 and 1.73mW during the divide-by-2 and divide-by-3 modes, respectively. The pro-posed wide band multimodulus prescaler has the maximum operating frequency of 7.2 GHz (simulation) with power consumption of 1.52, 1.60, 2.10, and 2.13mW during the divide-by-32, divideby-33, divide-by-47 and divide-by-48, respectively. For silicon verification, the multiband divider is fabricated using the Global Foundries 1P6M 0.18-µm CMOS process.the measurement results shows that the wideband 2/3 prescaler has a maximum Figure 7: 2/3 Prescaler Figure 8: 4/5 Prescaler Figure 9: Program Counter Figure 10: Swallow Counter Figure 11: 4/5 Frequency Divider Page 1364

6 Table 2: Comparison of area for different Device families Figure 12: Flexible Divider Figure 15: Power Analysis Figure 13: Place and Route(Package) Figure 14: FPGA Device VI.Results Table 1: Comparison of power for different Logic Families Figure 16: Area Analysis VII. Conclusion In the proposed design a 2/3 prescaler was implemented using E-TSPC logic. The proposed design is much more area efficient compared to the existing implementations due to the reduced number of transistors required for its implementation. Simulation results show that, compared with the conventional TSPC and E-TSPC based 2/3 prescaler designs as much as 46% in Power Delay Product (PDP), 24% in operation speed and 44% in area can be achieved by the proposed design. Also a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler which incorporates the proposed 2/3 prescaler were designed and implemented. Simulation results show that the power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler design. The schematic entry was done using Mentor Graphics Design Architect and simulation was done using Mentor Graphics References: [1] Anish M George,Prof. Riboy Cheriyan Design and Analysis of Power and Area Efficient 2/3 Prescaler Using E-TSPC Logic International Page 1365

7 Journal of Scientific & Engineering Research, Volume 4, Issue 8, August 2013 ISSN [2] Ramesh.K, E.Velmurugan, G.Sadiq Basha. Design Of Low Power Cmos High Performance True Single Phase Clock Dual Modulus Prescaler. Int. Journal of Engineering Research and Applications ISSN: , Vol. 3, Issue 5, Sep-Oct [3] Yin-Tsung Hwang and Jin-Fa Lin Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 9, September [4] Yeo, Kiat Seng Boon, Chirn Chye Lim, Wei Meng, Do,Manh Anh, Krishna, Manthena Vamshi. Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY [5] Fernando P. H. de Miranda, Joho Navarro SJr., Wilhelmus A.M. Van Noije A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in 0.35pm CMOS Technology July 10, 2010 from IEEE Xplore. [6] P. Y. Deng et al., A 5 GHz frequency synthesizer with an injectionlocked frequency divider and differential switched capacitors, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp , Feb [7] B.-Y. Lin, K.-H. Tsai and S.-I. Liu, A to ghz Injection Locked Frequency Divider in 65nm CMOS, ISSCC Dig. Tech. Papers, pp , Feb., Page 1366