Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc.

Size: px

Start display at page:

Download "Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc."

Randall Crawford
5 years ago
Views:

Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic Frequency Generators Integrating Time Michael S. McCorquodale, Ph.D.

1 Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic Frequency Generators Integrating Time Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc IEEE International Frequency Control Symposium Honolulu, HI Session B3L-A: Novel Oscillators and Modeling Tuesday, May 20, 2008

2 Outline A brief history of frequency synthesis Emerging integration technologies Self-referenced, trimmed and compensated RF CMOS harmonic (LC) oscillators (CHOs) Motivation and concepts Simplified architecture Published implementations Performance benchmarking Total frequency error Single sideband phase noise power spectral density Period and cycle-to-cycle timing jitter Conclusions Slide 2 of 41

3 A brief history of frequency synthesis Slide 3 of 41

4 A brief history of frequency synthesis Crystal oscillators (past present) 1880: piezoelectricity discovered by the Curies 1917: XTAL resonance explored by Langevin for SONAR 1919: frequency control using XTALs by Nicholson and Cady 1919 present: XOs proliferate Phase-locked frequency synthesizers (present) 1980s present: PLLs developed to allow for multiple and rational frequencies to be synthesized from one XTAL reference Degraded phase noise and jitter relative to fundamental mode XOs, but silicon integration becomes paramount Integrated frequency references (future?) Significant work toward realizing integrated frequency references begins a race to replace quartz 1990 s present: MEMS microresonators 2000 s present: CMOS harmonic oscillators (this work) Slide 4 of 41

5 Emerging integration technologies Slide 5 of 41

Emerging integration technologies Surface

Integration may enable advanced timing or

6 Emerging integration technologies Surface and bulk MEMS microresonators have emerged as possible replacement for quartz technology as a frequency reference Objective is integration: smaller form-factor, lower cost, etc. Integration may enable advanced timing or carrier synthesis architectures as references become free [Discera] [SiTime] Slide 6 of 41

7 Emerging integration technologies Fundamental challenges New process technology Hermetic packaging Relatively high freq. temperature coefficient (f TC ) Scaling resonator frequency Power handling High motional resistance complicates circuit design Nonlinear transduction incurs noise penalty Current MEMS-referenced implementations Low frequency MEMS resonator with fractional-n PLL where divider is dithered based on input of a temperature sensor for compensation of f TC Synthesizes frequencies in the 10 s of MHz band Slide 7 of 41

8 Self-referenced, trimmed and compensated RF CMOS harmonic (LC) oscillators (CHOs) Slide 8 of 41

9 CHOs: Motivation and concepts Achieve integration with a solid-state technology to realize monolithic timing references Leverage advances in RF CMOS Explore performance limits of CMOS oscillators Conceive an architecture to achieve: Low frequency error, low phase noise and low timing jitter Develop with an eye toward consumer timing Clock references for serial wire interfaces such as USB (±500ppm), S-ATA (±350ppm) and PCI (±300ppm) Here bit error rate (BER) is paramount and dominated by eye closure due to total frequency error and timing jitter Slide 9 of 41

10 CHOs: Motivation and concepts Measured eye-opening Specification template Period jitter determines the eye-opening and eye-opening determines the BER Commercial serial-wire interfaces have eye-opening specifications (USB test shown here) Slide 10 of 41

11 CHOs: Motivation and concepts Key concepts Far-from-carrier phase noise is the most significant contributor to timing jitter Linear frequency multiplication/division increases/decreases phase noise power quadratically Total timing error is dominated by jitter, not frequency error With these concepts is it possible to develop a monolithic low-q RF LC oscillator and achieve low timing jitter as well as low frequency error? Slide 11 of 41

12 CHOs: Motivation and concepts SSB phase noise PSD (dbc/hz) σ p = 8 N o sin 2 ω 0 o Po f m 2 πf m T o df m How does phase noise manifest into period jitter? σ p = RMS period jitter ω o = fundamental radian frequency T o = fundamental period f m = offset frequency from fundamental (N o /P o ) fm = phase noise at offset f m from fundamental sine square Offset from fundamental (Hz) Slide 12 of 41

13 CHOs: Motivation and concepts Consider 10MHz reference Peak at f m = ½ f o -50dB at 10kHz Period Jitter sin 2 (πf T o ) Integration Mask Offset Frequency (Hz) Linear to log x 10 6 Period Jitter sin 2 (πf T o ) Integration Mask Offset Frequency (Hz) Null at f o (f m = 0) Null at 2f o (f m = f o ) Close-to-carrier phase noise (<10kHz) is significantly attenuated when converting to period jitter Slide 13 of 41

14 CHOs: Motivation and concepts Visualizing frequency multiplication and division effects and the typical net performance degradation in a phase-locked loop relative to the reference Phase noise PSD (dbc/hz) Reference N N Close-to-carrier phase noise is attenuated and far-from carrier phase noise is amplified +20log 10 (N) -20log 10 (N) Phase noise PSD (dbc/hz) f m (Hz) XO/MEMS reference +10log 10 (N 2 ) PLL loop BW PLL VCO (unlocked) PLL output path Period jitter integration mask sin 2 (πf m T o ) f m (Hz) Slide 14 of 41

15 CHOs: Simplified architecture Free-run a CMOS RF LC oscillator near 1GHz Frequency divide by a large ratio Implement high-resolution process trimming Implement open-loop temperature compensation Implement closed-loop long-term drift stabilization Actively regulate the power supply Slide 15 of 41

16 2.5 High-swing pmos cascode bias CHOs: Simplified architecture v ac + _ C v (v ctrl (T)) compensates LCO over T C f [12:0] v bias Fixed thin film caps trim nominal frequency C f [12:0] Control loops mitigate drift Amplitude detector TR[12:0] MR[12:0] MR[12:0] TR[12:0] C v [5:0] C v [5:0] Common mode detector TC[5:0] TC[5:0] TC[5:0] TC[5:0] + _ v ctrl (T) v ctrl (T) v cmc Slide 16 of 41

17 CHOs: Simplified architecture 3.3 v BG v BG _ 3.3 Regulated supply via bandgap-referenced LDO Differential to single-ended converter, programmable divider and configurable output CHO D2S CLK I CTAT I PTAT + _ v ctrl (T) To trimming switches and programmable logic 96-bit MTP NVM I 2 C FLL SSCG NVM Control SDL SDA Programmable T-dependent compensating analog voltage Logic for I 2 C interface, trimming, spread-spectrum clock generation and NVM Slide 17 of 41

18 Recently published implementations 1500µm 400µm Config. Dividers Test Structures vctrl(t) Generator I2C, FLL, SSCG, NVM Control LDO I/O + ESD 2.5-to-3.3V Level Shift Bias 96-bit MTP NVM Michael S. McCorquodale, et al., A MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread Spectrum Capability, IEEE Int. Solid State Circuits Conf. Dig. of Tech. Papers, San Francisco, CA History Emerging CHOs gm amplifier ftc cal. bus Bias POR ½ fo discrete calibration array CB<7:0> ftc open-loop temp. comp. A-MOS varactors D2S ½ fo discrete calibration array Cf [12:0] and M[12:0] 2 x Cv [5:0] and TC[5:0] Bias Generation & Distribution ftc open-loop temp. comp. A-MOS varactors I/O + ESD gm Amplifier, Amplitude and Common Mode Control Loops Band-Gap Reference 550µm 1500µm Cf [12:0] and M[12:0] Process Control Structures Frequency dividers Michael S. McCorquodale, et al., A Monolithic and Self-Referenced RF LC Clock Generator Compliant with USB 2.0, IEEE J. of Solid State Circuits, vol. 42, no. 2, Feb. 2007, pp Benchmarking Conclusions Slide 18 of 41

19 Performance benchmarking Slide 19 of 41

20 Performance benchmarking Existing (XO/XO-PLL) 24MHz 4-pin can crystal oscillator (XO) 24MHz 2-pin passive crystal-referenced phase-locked loop (XO-PLL) 12MHz 2-pin passive ceramic resonator + sustaining circuit Emerging (MEMS-PLL) 20MHz MEMS-referenced PLL (vendor #1) 12MHz MEMS-referenced PLL (vendor #2) This work (CHO) 12MHz, 1.536GHz LC-referenced CHO 12MHz, 960MHz LC-referenced CHO Benchmarks Total frequency inaccuracy (due to trimming, power supply and temp.) SSB phase noise PSD Period and cycle-to-cycle jitter Total timing error Slide 20 of 41

21 Total frequency inaccuracy δf /f o (ppm) Normalized frequency innacuracy, Best CHO performance in Si to date shown Typical production yield is ±150ppm CHO trim occurs at 35 C 24MHz XO 20MHz MEMS-PLL 12MHz MEMS-PLL 12MHz CHO VDD + 10% 12MHz CHO nominal VDD 12MHz CHO VDD -10% 12MHz Ceramic δf /f o (ppm) Normalized frequency innacuracy, Temperature ( C) Slide 21 of 41

22 Single sideband phase noise PSD 0 24MHz XO -20 SSB phase noise PSD, (N o /P o ) fm (dbc/hz) Offset frequency (Hz), f m (Hz) Slide 22 of 41

23 Single sideband phase noise PSD SSB phase noise PSD, (N o /P o ) fm (dbc/hz) MHz XO 12MHz Ceramic Oscillator Ceramic resonator is lower Q than XO so close-to-carrier phase noise is higher Offset frequency (Hz), f m (Hz) Slide 23 of 41

24 Single sideband phase noise PSD MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL SSB phase noise PSD, (N o /P o ) fm (dbc/hz) Outside PLL loop BW, phase noise tracks VCO (note PLL loop mult. is 1) Offset frequency (Hz), f m (Hz) Slide 24 of 41

25 Single sideband phase noise PSD MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL SSB phase noise PSD, (N o /P o ) fm (dbc/hz) Offset frequency (Hz), f m (Hz) Slide 25 of 41

26 Single sideband phase noise PSD MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL SSB phase noise PSD, (N o /P o ) fm (dbc/hz) MEMS-PLL frequency multiplication increases phase noise inside PLL loop BW Outside PLL loop BW, phase noise tracks VCO Offset frequency (Hz), f m (Hz) Slide 26 of 41

27 Single sideband phase noise PSD SSB phase noise PSD, (N o /P o ) fm (dbc/hz) MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO Offset frequency (Hz), f m (Hz) Slide 27 of 41

28 Single sideband phase noise PSD SSB phase noise PSD, (N o /P o ) fm (dbc/hz) MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO 12MHz CHO Close-to-carrier phase noise is higher in CHO but comparable to MEMS-PLL CHOs have much lower far-from-carrier phase noise than PLLs Offset frequency (Hz), f m (Hz) Slide 28 of 41

29 Single sideband phase noise PSD SSB phase noise PSD, (N o /P o ) fm (dbc/hz) MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO 12MHz CHO Project onto sin 2 (πf m T o ) SSB phase noise PSD sin 2 (πf m T o ) (dbc/hz) From ~30kHz all PLL implementations are noisier than CHOs 24MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO 12MHz CHO Offset frequency (Hz), f m (Hz) Offset frequency (Hz), f m (Hz) Slide 29 of 41

30 Single sideband phase noise PSD SSB phase noise PSD sin 2 (πf m T o ) (dbc/hz) Visualize on linear scale 24MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL 12MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO 12MHz CHO Offset frequency (Hz), f m (Hz) SSB phase noise PSD sin 2 (πf m T o ) (dbc/hz) CHO, XO and Ceramic Oscillator all exhibit similar far-from-carrier noise >15dB Projected CHO noise approaches XO noise but XO is at twice the frequency 24MHz XO 12MHz Ceramic Oscillator 24MHz XO-PLL MHz MEMS-PLL 20MHz MEMS-PLL 12MHz CHO 12MHz CHO Offset frequency (MHz), f m (Hz) Slide 30 of 41

31 Period and cycle-to-cycle jitter Phase noise measurements show that far-from-carrier phase noise is very similar for XO, ceramic oscillator and CHO Far-from-carrier phase noise for CHO appears lower than all implementations, except XO, due to higher power in LCO (but XO at double freq.) Theory predicts that these three implementations should exhibit similar period jitter and CHO should exhibit the lowest jitter Theory also predicts that the PLL implementations should exhibit comparatively higher period jitter Slide 31 of 41

32 Period and cycle-to-cycle jitter 24MHz XO σ p = 6.52ps rms σ cc = 11.48ps rms 24MHz XO-PLL σ p = 10.38ps rms σ cc = 18.89ps rms Ceramic oscillator and XO have similar jitter; 1x multiplier in PLL degraded jitter in XO-PLL 12MHz Ceramic σ p = 6.52ps rms σ cc = 11.01ps rms Slide 32 of 41

33 Period and cycle-to-cycle jitter Jitter for both implementations is much higher than XO and XO-PLL as expected 20MHz MEMS-PLL σ p = 12.16ps rms σ cc = 17.60ps rms 12MHz MEMS-PLL σ p = 36.40ps rms σ cc = 46.99ps rms Slide 33 of 41

34 Period and cycle-to-cycle jitter CHO has lowest jitter and is directly comparable to high-q XO because CHO has low far-from-carrier phase noise 12MHz CHO σ p = 6.41ps rms σ cc = 11.25ps rms 12MHz CHO σ p = 5.73ps rms σ cc = 9.32ps rms Slide 34 of 41

35 Period and cycle-to-cycle jitter MEMS-PLL is >6x higher CHO has the lowest jitter Slide 35 of 41

36 v Fractional total timing error Introduce the concept of the fractional total timing error, or the maximum error in any period due to frequency inaccuracy and jitter δt max To Maximum period error = T o δt max T o ( T ( ) ) o max δf fo + ασ p To Maximum jitter for a bounding cycle count Basically, consider the sum of the total frequency error AND the maximum period jitter as a metric which is relevant to eye closure t Ideal period Slide 36 of 41

37 This is the worst-case fractional period error and determines eye opening and BER Total timing error f o (MHz) max(δf/f o ) (ppm) max( f -1 ) (ps) σ p (ps) ασ p α = 14.1 (ps) max(δt/t o ) (ppm) ασ p /max(δt/t o ) (%) XO XO + PLL MEMS + PLL α = 14.1 is for cycles (a common specification) MEMS + PLL CHO CHO Slide 37 of 41

38 Period jitter summary A low-q LCO can achieve period jitter much lower than high-q implementations (including XOs and MEMS) by: Exploiting frequency division Exhibiting low far-from-carrier phase noise High-Q MEMS oscillators do not achieve low jitter and phase noise due to loop multiplication and PLL VCO A low-q LCO can be implemented in a standard solid state process technology and achieve period jitter performance directly comparable high-q oscillators Power dissipation in the CHO is comparable to the XO-PLL and MEMS-PLL implementations Slide 38 of 41

39 Conclusions Slide 39 of 41

40 Conclusions Self-referenced, trimmed and compensated RF CMOS harmonic oscillators (CHOs) were introduced as monolithic frequency generators realized entirely in a solid-state process technology CHO implementations were benchmarked against incumbent XOs/XO-PLLs and emerging MEMS-PLLs where it was shown that frequency error was comparable and period jitter was superior for the CHO CHOs are now entering the production phase Slide 40 of 41

41 Questions are welcome Slide 41 of 41

Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic Frequency Generators

Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic Frequency Generators Michael S. McCorquodale Mobius Microsystems, Inc. Sunnyvale, CA USA 9486 mccorquodale@mobiusmicro.com