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1 Design Methodology or Power-Constrained Low Noise RF Circuits Jung-Suk Goo, Hee-Tae Ahn, Donald J Ladwig, Zhiping Yu, Thomas H Lee, and Robert W Dutton, Stanord University, Stanord CA National Semiconductor, Santa Clara CA Texas Instruments, Dallas TX 1

2 NF Four Noise Parameters Minimum Noise Factor (F min ) Optimum Source Admittance (Y opt ) Equivalent Noise Resistance (R n ) : Best achievable noise perormance : Source admittance yielding NF min : Sensitivity o NF when Y s diers rom Y opt = F min + (Y s Y opt ) 2 R n F s G 2 Desired to be Low F min Small R n 15 1 Rn Y s Y opt 5 1 NFmin 5 =[ s] opt <[ s] 1 2

3 L g L s Integrated LNA Design (Tuned LNA Architecture) Basic Architecture Conjugate Power Match O-Chip Matching ZC ZB ZA Rs Lg Tm Vs Cp Cm Ls Controls noise perormance Why? 3

4 Z conj;best NF min;lna Integrated LNA Design (Continue) (Power Matched Design) 1 = 1/24 M 2 = 5/24 M DS1 =25V V GS1 =8V V = 4GHz Z opt;best Noise Figure [db] = 1/24 M 2 = 5/24 M DS1 =25V V GS1 =8V V = 4GHz NF LNA Source Inductance [nh] = F min + (Y s Y opt ) 2 R n F s G M 2 contribution is excluded 4

5 NFLNA NFmin Integrated LNA Design (Continue) (Power Matched Design) Optimum Source Inductance [nh] I DS =2mA 5mA 1mA 2mA Gate Bias o M1 [V] 2 = W 1 /2 W DS1 =25V V = 4GHz Noise Figure [db] M 2 contribution is excluded NFmin;LNA W 2 = W 1 /2 VDS1=25V = 4GHz Gate Bias o M1 [V] Optimum L s is bias dependent and linearly scaled by the current speciication The achievable noise igure is independent o the current speciication and quite close to the intrinsic NF min 5

6 Z opt Z opt Integrated LNA Design (Continue) (Power Constrained Perormance, Z s =Z in =5Ω) Optimum Impedance (Z opt ) 2 = W 1 =2 W DD =2V V = 8MHz Z conj =5Ω 2mA I DD =2mA 5mA 1mA 5mA 1mA Z conj =5Ω I DD =2mA 2 = W 1 W DD =25V V = 4GHz Matched Cascode Mismatched Cascode = F min + (Y s Y opt ) 2 R n F s G 6

7 Integrated LNA Design (Continue) (Power Constrained Perormance, Z s =Z in =5Ω) Noise Resistance (R n ) Noise Figure (NF) Noise Resistance [Ω] = W 1 =2 W =2V VDD = 8MHz IDD=2mA 5 1mA Gate Bias o M1 [V] 5mA Noise Figure [db] = W 1 =2 W =2V VDD = 8MHz NF min Gate Bias o M1 [V] IDD=2mA 5mA 1mA = F min + (Y s Y opt ) 2 R n F s G 7

8 Integrated LNA Design (Continue) (Impact o Pad Capacitance, Z s =Z in =5Ω) Optimum Impedance (Z opt ) Noise Resistance (R n ) W 2 = W 1 =2 =2V VDD = 8MHz = 375mA IDD Z conj =5Ω 15 Z opt Noise Resistance [Ω] 1 5 W 2 = W 1 =2 =2V VDD = 8MHz = 375mA IDD C p =F 2F 5F Gate Bias o M1 [V] = F min + (Y s Y opt ) 2 R n F s G 8

9 Integrated LNA Design (Continue) (Impact o Pad Capacitance, Z s =Z in =5Ω) 6 Noise Figure [db] js21 j [db] Noise Figure (NF) Gain (s 21 ) W 2 = W 1 =2 =2V VDD = 8MHz = 375mA IDD C p =F 2F 5F W 2 = W 1 =2 =2V VDD = 8MHz = 375mA IDD p =F C 2F 5F NF min Gate Bias o M1 [V] Gate Bias o M1 [V] 9

10 LNA Implemenation (Continue) (Implementation, Z s =Z in =5Ω) 8MHz single-ended 24µm, silicided-poly, 5-metals W 1 =9, W 2 =45 (not optimized) 5µm-long gate ingers M5 spiral inductors w/ patterned ground shield M5/M1 pad capacitors 24-pin LLP package An o-chip inductor or L g 1

11 Die Area 19 mm 2 LNA Implemenation (Continue) (Perormance) Parameters Frequency Supply Voltage Power Consumption Noise Figure Available Gain IIP3 s 11 Measured Value 8 MHz 2 V 75 mw 9±2 db 88 db -381 db 71 dbm Just adds 3dB to NF min 11

12 Conclusions Overall NF is controlled by L s : Optimal L s achieves NF close to intrinsic NF min with a perect power match For a ixed Z s, simultaneous choice o V gs and width o input stage is most critical in design Mismatched cascode stage determines the lower limit o noise igure Pad capacitance provides another design lexibility CMOS LNA can be competitive with GaAs and Bipolar in low GHz range 12