Design Considerations for Highly Integrated 3D SiP for Mobile Applications

Transcription

1 Design Considerations for Highly Integrated 3D SiP for Mobile Applications FDIP, CA October 26, 2008 Joungho Kim at KAIST

2 Contents I. Market and future direction of 3D system in package II. Signal integrity issues in 3D SiP Design III. Power integrity issues in 3D SiP Design IV. Summary 2 2

3 Ubiquitous Mobile Life Physical World Mobile Platform Player Brain Product Robot Wired Wireless Internet Computing Communication Sensing/Cognition/Iden tification Entertainment Medical/Welfare service Telephony network Auto-mobile 3

4 3D System In Package 3D Memory Stack Multi-core Processor SRAM DRAM Flash RF Transmitter/ Receiver Filter Antenna Embedded de-cap Termination Resistor EBG Structure 4

5 16GB Samsung NAND Flash, 8Gbx16 Terahertz Interconnection and Package Sharp, Morihiro Laboratory Kada 5

6 3D Hamburger SDRAM Digital Core RF Analog 6 6

7 Advantages of 3D SiP approach Small form factor Fast time to market Inhomogeneous device integration Integration of passive devices, filters, and antenna Suitable for RF mobile communication systems Low cost 7 7

8 Applications for SiP 71 % Concentrate on Multi-Function Light Weight Device Application - Short Product Life Cycle (PLC) 3 % SiP Application 5% 6% 2007 Source: Advanced IC Packaging (2007 Edition) 8

9 Frequency Spectrum of Digital Clock Waveforms f(x) Time 9

10 Waveform and Spectrum of Clock Signal Magnitude (mv) ns10ns 100MHz 200MHz Time (ns) Power [dbm] Fundamental : 100MHz 200MHz Odd harmonics Even harmonics 100MHz 200MHz Frequency [MHz] 10

11 Spectrum of Wireless Mobile Communication Systems WI-FI Bluetooth T-DMB TPMS GPS S-DMB AM FM RF-ID WiBro UWB UWB 174~216MHz MHz MHz 2.3GHz 2.6GHz 3.1~4.8GHz 7.2~10.2GHz 주파수 535~1,705kHz 2.4GHz MHz 88~108MHz 900MHz 11

12 Noise coupling path from digital circuits and RF circuits - Noise coupling Paths: Wire, Traces, slot, and Balls Via transitions Return current path discontinuities Power and ground pane cavities - Results: Timing and voltage margin violation at receiver Degradation of receiver sensitivity and BER 12

13 Signal Integrity Concerns at SiP design Reflections and resonances by impedance mismatches: source end termination, line impedance, and receiver end termination Reflections and resonances by impedance discontinuities: via, pad, wire, connectors, cables. Reflections and resonances by return current path discontinuities Common return current path and non-zero return current path impedance Channel loss by skin effect loss and dielectric loss 13

14 Impedance discontinuities at package wire, pad, via, trace, ball Channel of chip-to-chip link : A package is becoming a major bandwidth restraint. Gnd Pad SDRAM Bump Digital BB & Multimedia Cap Cap RF tuner(flipped) Cap Cap PKG (4 layer) Board Signal 14 14

15 Transmission Lines on SiP Package Type : PBGA No. of Layers : 4 Package Size : 23 x 23mm Ball Array 22x22 Ball Array, 384 Balls Power/Ground Plane Split 5 Ground / 7 Power Die Size 5 x 5mm, 1.6 x 1.8mm Line Width : 60um Ball pitch, size : 1mm,0.6mm Via : 300um, Drill : 150um Finger length : 300um Finger pitch : 140~150um Finger spacing : 25um A1 placement : no routing 15

16 Insertion Loss of 900MHz Single Line 0 S21[dB] MHz frequency (GHz) Case No split / no ref change No split /ref change Split / no ref change S21(dB) No split & no reference change No split & reference change Split & no reference change 16

17 Spectrum Analyzer Measurement of P/G Plane Edge Radiation from TV2 (Center Via) with 500MHz Clock Excitation Edge Radiation (SA-PPG) [dbm] TV2 SA Measurement TV2 P/G Plane Impedance rd 500 MHz CLK TV2 (7cm,7cm) P/G Plane Impedance [Ω] 14cm Short Via Frequency [GHz] 14cm 17

18 Resonances in SiP Substrate Multiple reflections Power/Ground plane cavity Interactions between via inductance, wire inductance, and ESL of decoupling capacitors with off-chip decoupling capacitors, on-chip decoupling capacitors, and power/ground plane capacitance Slots 18

19 Digital noise isolation in SiP Balancing Secure return current Filtering Shielding Separations 19

20 Separation Between Digital Signals and RF Signals A digital clock or digital I/O can be an aggressor signal to an RF signal, while an RF signal can be a victim. Digital clocks or I/Os should be spatially separated from RF signals. All Signals Digital CLK & I/Os Sensitive RF Signals Digital CLK & I/Os All Signals Sensitive RF Signals 20 20

21 Coupling Between Signal Line & Digital Clocks : T-DMB Case 50dB Band 3 Band 3 Band 3 L-Band IN Clock Name Operation Voltage Operation Frequency DACBITCLK 3.3V 2MHz Band III IN DACSYSCLK 3.3V 12MHz SPI0CLK 3.3V 16MHz TCK 3.3V 350kHz AGND TSCLK 3.3V 4MHz TVCLK 3.3V 27MHz VRCLK 3.3V 27MHz 21

22 Coupling in Wires for Stacked SiP 22 22

23 10 chip stacked Package by KAIST μm TSV diameter 150 μm Pitch 23

24 Key Technology : TSV (Through Silicon Via) 3 rd Chip (Thinned Substrate) Short Interconnection Reduced RC Delays Low Impedance for Power Distribution Network Low Power Consumption Heat Dissipation Through Via 2 nd Chip (Thinned Substrate) 1 st Chip Under fill Dielectric Dielectric Under fill Multi-level On-chip Interconnect SiO2 No Space Limitation for Interconnection High Density Chip Wiring No Limitation of I/O Number No Limitation of I/O Pitch Small Area Package Si-Substrate 3D TSV Stacked IC 24

25 Background(1): High-frequency Channel Loss in TSV -Significant high-frequency signal loss occur at Signal Transmission C Through TSV via_ox -The signal loss through TSV is caused by substrate leakage and coupling G sil S21(magnitude) [db] 0.1μm Frequency [GHz] Si SiO 2 Ta Cu Close up of through wafer via Magnitude of S21 25

26 Loss characteristics of single-ended signal TSVs Electrical characteristics of signal TSVs: 1 Capacitance C area, 1/(distance) Capacitance bet. metal & SiO2 Capacitance bet. metal & Silicon sub. S21(magnitude) [db] # of stacks Via diameter Bump diameter SiO2 thickness area distance S21 slope Pitch bet. TSVs distance S21 slope 26 26

27 Coupling Issues in Stacked Dies using TSV Bonding Adhesive P-Substrate Bonding Adhesive 3 rd Chip Inductor TSV TSV TSV TSV N+ P+ P+ N+ N+ P+ N-Well 2 N+ P+ N-Well P-Substrate N+ N+ 3 P+ N+ Metal N-Well to Metal Coupling 2 nd Chip TSV to Active Circuit Coupling Inductor 1 TSV TSV TSV to TSV Coupling N+ P+ P+ N+ N+ P+ N-Well N+ P+ N-Well N+ N+ P+ N+ N-Well P-Substrate 1 st Chip < CROSSSECTIONAL VIEW > 7/32 27

28 Crosstalk Mechanism Between TSV s -20 Port3 C bump Port C si C bump C via_ox + C parasitic,top -50 C ox C parasitic,bump L via -60 R via C si C via_ox + C parasitic,bottom -70 G si M 1G 10G Freq [Hz] Port4 Port2 Very small parasitic capacitances, C bump, C SiO2,top, C SiO2,bottom R via, L via have very little effect on near & far end coupling -28- start to be in effect over GHz range 28

29 SSN coupling paths in SiP - Wires of RX front end near digital power/ground wires - Vias though digital power/ground planes - Traces near digital power/ground traces - Embedded passive components of RX front end : Balun, filter, coupler, and antenna 29 29

30 PDN Noise Isolation Methods Digital PDN Chip Analog/RF PDN A Package PCB B A Chip Level - Split On-chip Metal PDN Bus - Guard Ring (P+/ N+/ Deep-Nwell type) - On-chip Decoupling Capacitor - Internal Voltage Regulator B Package/PCB Level - Split Power/Ground Planes - On-Package/PCB Decoupling Capacitor (Discrete type, Embedded type) - Electromagnetic Band Gap (EBG) Frequency dependency of noise isolation Z21 analysis in the frequency domain 30

31 The isolation methods of each hierarchical PDN Transfer Impedance [Ω] Merged PCB PDN/Merged Package PDN Split PCB PDN/Split Package PDN Split PCB PDN/Split Package PDN+off-chip decap. Split PCB PDN/Split Package PDN+off-chip decap.+on-chip decap. By Split 10-2 off-chip decap. on-chip decap M 10M 100M 1G 3G Frequency [Hz] By split of PCB and package level PDN, the PDN transfer impedance can be suppressed except around 10MHz. By adding on-/off-chip decoupling capacitor, the PDN transfer impedance can be suppressed in both low and high frequency region. 31

32 Measured PDN Impedances between TSV PKG and Bond-Wire PKG P/G network impedance [Ω] Plane Plane C of of package package =70pF =70pF Impedance Improvement With Discrete Decoupling Capacitors De-cap C=4nF De-cap. C=4nF Bonding-wire w/o de-cap. TSV w/o de-cap. TSV w/ 4 x 1nF on-package de-cap. Parallel resonance between ESL of de-cap. and package plane 512MHz ESL=1.66nH Impedance Improvement over GHz Parallel resonance With between TSVs ESL of de-cap. and package plane C 755MHz ESL=0.79nH Frequency [Hz] Discrete on-package de-cap provides low impedance at the low frequency range (Large Capacitance) TSV reduces impedance over GHz range (Small ESL of TSV) 32

33 Characterization [3] : Chip-PKG-TSV port1 L chip L chip L via L PKG L PKG Chip n+ n+ C cap C chip C chip_decap C PKG Package L cap L chip L chip L via L PKG L PKG 40 Z11 of Chip-PKG Hierarchical PDN(dB) L cap +ESL C PKG +C via + C chip_decap +C chip L PKG +ESL C chip_decap +C chip ESR L chip 0 100M 1G 10G Frequency(Hz) 33

34 Cell Partitioning in EBG Structure with Embedded Film Capacitor 0.2mm 100mm Port 1 Port 2 9.8mm Via EBG Cell Array 100mm 10mm Fig.1. (a) The top view of the test vehicle with EBG structure EBG cells are arrayed in 100mm 100mm board. The measurement port 1and 2 locate at the center and the edge of the board, respectively. 34

35 Measured Z21, Transfer Impedance of PDN f 20,02 f 20,02 f 22 f 40,04 f f f 62, ,06 f 42, Z 21 [Ω] band-gap (3.2GHz) band-gap (1GHz) 10-3 TV C (EBG, Thin Film) Frequency [GHz] TV A (Solid, FR4) TV B (EBG, FR4) Fig. 3. (b) The measured transfer impedance curves between port 1 and 2: TV A (dashed line); TV B (dotted line); and TV C (solid line). TV C (thin film EBG) has band-gap from 300MHz to 3.5GHz and TV B (typical EBG) has band-gap from 2.3GHz to 3.3GHz. 35

36 Measured Radiated Emission Spectrum Radiated Emission [dbm] Radiated Emission [dbm] dBm Frequency [GHz] Reference Noise Floor 2.5dBm TV B (EBG, FR4) Frequency [GHz] Radiated Emission [dbm] Radiated Emission [dbm] dBm Frequency [GHz] dBm TV A (Solid, FR4) TV C (EBG, Thin Film) Terahertz Frequency Interconnection [GHz] and Package Laboratory 36

37 Summary - Significant noise coupling occurs from digital PDN to noise sensitive RF and analog circuits on a same SiP. - The clock frequencies and harmonic frequencies should be placed away from the RF carrier frequencies. - Low PDN impedance should be maintained. - PDN resonance frequencies should be placed away not only from the clock frequencies, and their harmonic frequencies, but also from RF carrier frequencies. - Via and wire are a major noise coupling path from digital PDN to noise sensitive circuits. - Noise coupling reduction methods including using PDN design, frequency control, filtering, separation/isolation, decoupling, shielding, and grounding techniques. - Chip-package co-design can provide optimal and cost-effective solutions