Characterization of Alternate Power Distribution Methods for 3D Integration

Transcription

1 Characterization of Alternate Power Distribution Methods for 3D Integration David C. Zhang, Madhavan Swaminathan, David Keezer and Satyanarayana Telikepalli School of Electrical and Computer Engineering, Georgia Institute of Technology Atlanta, GA 30332, USA. Phone: , Fax: Abstract Signal return path discontinuities, parasitic inductance and impedance mismatch within interconnects are major factors that contribute to degraded high-speed signal quality in threedimensional (3D) integrated circuits and systems. In this paper, we apply an alternate power delivery method and a novel I/O signaling scheme to a 3D system to address these issues. Two test vehicles made of stacked PCBs that resemble 3D integrated systems will be presented. One test vehicle is designed based on our proposed approach while the other is based on the conventional power delivery network design. The signal integrity and power supply noise performance will be shown in both simulated environment and actual test measurement. At data rates up to 3Gbps, our proposed design produces higher signal quality than the conventional design with better eye height, lower timing jitter, and lower power supply noise. Index Terms Power delivery network (PDN), power transmission line (PTL), simultaneous switching noise (SSN), power supply noise (PSN), return path discontinuity (RPD). I. INTRODUCTION In the current and future high-speed digital systems, the I/O speed is being pushed to tens or even hundreds of gigabits per second with transition time precision in femtoseconds. Additionally, the supply voltages in an integrated chip (IC) also trends down to sub-volt range to prevent current leakage and gate breakdown due to shrinking transistor size. As a result, noise tolerance in a high-speed digital system decreases as the circuits switch faster. Therefore good signal integrity (SI) and power integrity (PI) are vital for the success of any high-speed systems. A 3D IC system such as the one shown in Fig. 1, it normally consists of a PCB and a stack of heterogeneous IC dies. Maintaining high SI and PI in such a complex structure has its own challenges. The first challenge is return path discontinuities (RPD). The modern printed circuit board (PCB) designs have become more challenging due to increased number of layers, complex power delivery network and high routing density. As a result, maintaining uninterrupted return paths and avoiding impedance mismatch for high-speed signals in the face of current power delivery network design is very difficult. Many times additional ground layers have to be added for the purpose of providing a complete reference for fast switching signals. This approach significantly increases the manufacturing cost. Return path discontinuities occur when transmission lines carrying fast /14/$ IEEE Fig. 1 A conventional 3D model for simulation edged signals make via transitions without proper ground reference or are routed over splits of planes underneath. Return path discontinuities cause increased loop inductance formed by the forward and return signals, excite cavity resonance within the PCB, and facilitate unwanted electromagnetic coupling which can then lead to degraded signal quality and increased simultaneous switching noise [1][2]. Fig. 2 shows an illustration of how RPD can occur in a PCB. The return path for the forward signal is interrupted by the middle plane 1 layer which forces return current to jump between plane 1 and 2. This return path interruption can lead to increased effective loop inductance and undesired signal and PDN coupling. Fig. 2 Illustration of RPD cause-effect in a PCB The second issue is the increasing parasitic inductance as the height of the IC stack grows. As illustrated in [3] and [4], Electronic Components & Technology Conference

2 due to increasing parasitic inductance from interconnects among the stacked dies, the impedance of the PDN of a higher die is more than that of a lower die in the inductive region. Consequently this increasing parasitic inductance contributes to higher simultaneous switching noise (SSN) as one moves up the stack. The third issue is impedance mismatch among the various interconnect for signal, power and ground. As one can see from Fig. 1 that there are various bonding structures such as ball grid array (BGA), soldering micro bump and through silicon via (TSV) along a power or ground rail interconnect that runs from bottom to the top. It would be impractical to expect their impedances would match among themselves. The mismatch among interconnects causes voltage and current reflection as well as unwanted coupling among the interconnects. The aggregate effect of the aforementioned three major problems with 3D ICs systems causes increased system level noise and reduced SI and PI. To reduce the noise, the most common method used is by using on-chip and/or off-chip decoupling capacitors. Therefore, many studies are devoted to the characterization, selection and placement of decoupling capacitors. The works done in [5]-[7] focus on relatively large two dimensional systems such as a computer server in which space may not be a critical constrain. However for many modern smart consumer electronics such smartphones and 3D integrated systems, on-board or on-chip real estate is a precious commodity. There may not be enough space to place the required number of off-chip decoupling capacitors in order to meet the impedance target. In addition, adding decoupling capacitors whether on-chip or off-chip does not always help to meet the impedance target or design requirement in ICs due to current leakage and parasitic inductance. For on-chip decoupling capacitors, the effectiveness of the capacitors also heavily depends on the distance between the capacitors and where noise needs to be controlled. Researchers and designers also propose to put voltage regulators on chip. However, the effectiveness of these regulators also heavily depends on the placement [8]. Power efficiency of the on-chip regulars is another important factor to determine whether it is a worthwhile approach. Fig. 3 Power transmission line based PDN in a PCB The design method we propose in this paper uses few or no decoupling capacitors to suppress noise. Instead, we tackle the problem in a proactive way by redesigning the power delivery network in a 3D system working in tandem with a new signaling scheme. We propose to use power transmission lines (PTL) to replace power planes in conventional PDN designs in PCBs so that the forward signal and its return path will be able to form a complete loop and hence eliminate the RPD effect as shown in Fig. 3 and [1]. We further improve the design by introducing a novel high-speed signal scheme that would add a current compensation mechanism in order to reduce current transient on the power supply rail [1]-[2]. The design approach is named constant current power transmission line or. The proof of concept was demonstrated in [1]. The PTL design concept was then applied to 3D models and produced optimistic results in the previously published work in [4] and [9]. The simulated result showed the SI and PI performances of our proposed method clearly exceed that of the traditional design in a 3D system. However, there was no measurement that had been done in an actual 3D test vehicle with our proposed design until now. This paper will report the design of two 3D test vehicles based on conventional PDN design and the PTL design respectively. The high-speed signal eye-height, peak to peak jitter and power supply noise will be shown and compared between the two designs. We will show that with minimum decoupling capacitors, our proposed PTL-based design can produce better SI and PI than conventional design in a 3D environment even with parasitic inductance of several nanohenries at a data rate of 3Gbps PRBS. This paper is arranged as follows: in section II, a brief summary of design is introduced. The manufacturing details of the 3D test vehicles are reported in section III. Measurement results of two test cases are shown to demonstrate proof of concept in a 3D test vehicle. Finally, we conclude this paper through a summary in section V. II. Proposed PTL-Based design The fundamental difference in PTL based design is the use of transmission lines as the medium to carry power from the supply source to local digital logics instead of the traditional use of power planes [1]. By removing power planes, only ground planes exist in a PCB design. Regardless of the complexity of the PCB, continuous reference for the return path of a forward signals is made easily accessible. Therefore, a complete loop of forward and return path can be formed without inducing any RPDs as shown in Fig. 3. As a result, both SI and PI can be significantly improved [1] and [2]. A PTL based 3D IC system model is shown in Fig. 4. By using PTL as a conduit to channel power from the power supply to local active devices, dynamic data dependent DC drop will occur. In addition, impedance of the PTL needs to be matched with that of the on-resistance of the connected drivers to minimize reflection. This is a difficult task for practical designs. Therefore, a signaling method was proposed in [1] named constant current PTL or which can address both dynamic DC drop and impedance mismatch issues by providing a current compensating mechanism, 2261

3 namely the dummy path, based on the input data as shown in Fig. 5. This mechanism ensures that regardless of the state of the input bit, the current draw from the power supply source through the PTL remains the same. Therefore current fluctuation or di/dt is minimized [1] and [2]. With a minimum di/dt, even we have significant parasitic inductance along the path of PDN in a 3D structure; noise can be kept at a minimum [4]. For each version of the TVs, the designed PCBs are stacked together to create a 3D structure as illustrated in Fig. 8. The bottom PCB is the motherboard. On top of the motherboard are three stacked PCBs that are named daughter cards. Each daughter card has multiple high speed I/O drivers. The PCBs are joined together by board-board connectors. The boardboard connector pins can be treated as interconnects of the 3D model as described in section I. The inductance of each connection within the board-board connector is estimated to be 7.77nH between adjacent PCBs. The parasitic inductance between adjacent stacked dies in our previously presented simulation model [4] was about 66.9pH. Therefore, the inductance between two stacked PCBs in the TVs is approximately 116 times more than the parasitic inductance from the simulation model presented in [4]. We will show through measurement that even with this large parasitic inductance we can still maintain good SI and PI with our proposed PTL based design with minimum number of decoupling capacitors. Fig. 4 A PTL-based 3D model for simulation Fig. 6 3D PCB structure illustration and test setup Fig. 5. (a) schematic. (b) simulated waveform at nodes V_PTL and V_out III. 3D PCB test vehicle information In order to model a 3D IC system that consists of a stack of IC dies and a PCB at the bottom as shown in Fig. 1 and 4, two versions 3D test vehicles made of PCBs were designed and fabricated. The first version was designed based on PTL power delivery network and the second, conventional PDN. Both motherboard and daughter cards are 4-layer FR-4 PCBs whose stack-up is shown as shown in Fig 7. The top and bottom layers are used for routing purpose. The middle two layers are ground layers for PTL based TV as the power plane is replaced by PTLs which are routed on the bottom layer. For conventional design, layer-2 is set as VDD power layer and layer-3 is assigned to ground. The dimension of the motherboard is 18.41cm by 10.16cm. The daughter-card is approximately 12.12cm by 35.56cm. Mated height between adjacent PCB is 11.05mm. In the conventional design TV, the top daughter card has eighteen 0402 and eighteen 0603 decoupling capacitors strategically placed around the board to suppress the power supply noise. On the PTL based TV; however, only two 0402 decoupling capacitors are placed for every active driver. The ratio of the placed decoupling capacitors on the convention design to that on the PTL design at the time of measurement was approximately 9:1. The test setup is illustrated in Fig. 6. The signal generator is an Agilent 81133A 3.35GHz Pulse/Pattern Generator. The oscilloscope is an Agilent DCA-X 86100D with HP 54752A Two-Channel 50GHz Module probe. The IC drivers are OnSemiconductor NBSG16 12Gbps SiGe drivers. Since the signal generator can only generate one pair of differential 2262

4 signals, a 1:16 fan-out board is used to drive more drivers on the TVs. The lab-bench setup is shown in Fig. 8. The intermittent crossover among the impedance curves is due to board to board process variation. Fig. 7 PCB stackup for the 3D test vehicles Fig. 9 Top view of the daughter card with mounted SMA connectors Fig. 10 Measured impedance profile of the test vehicle based on conventionally PDN design Fig 8 Lab-bench setup for 3D test vehicle measurement IV. 3D PCB Test Vehicle Measured Results As with the 3D IC system model which was previously shown in [7], the impedance profile of the conventional 3D test vehicle is measured with a VNA with SMA connectors mounted directly onto the test points as shown in Fig. 9. Due to the larger scale of the TV the impedance is about eight times higher than that in [7] for the simulated 3D IC system model; nonetheless, the general trend of higher impedance for higher stacked PCB can be seen from Fig. 10. Next, we excite a total of six drivers with a 3Gbps pseudorandom bit stream, two drivers on each daughter card, to compare the SI and PI performance. The eye diagrams and performance data plot of the conventional and PTL based designs are shown in Fig. 15. From Fig. 15 and Fig. 10, both simulated and actual lab measurement, the proposed design performance exceed that of the conventional design in term of eye height and especially in p-p jitter and power supply noise. For example, at the 3rd stack the eye height of the design is 104% higher, p-p jitter is 53.3% lower and power supply noise is 72.9% lower than the conventional design. Both the power supply noise and p-p jitter at each daughter card of the PTL-based TV varies very little with a standard deviation of only 5.5 and 4.4 respectively while those in the conventional design varies by as much as almost 26 and 13 respectively. Table 1 presents a summary of measured results and percentage of improvement. 2263

5 Table 1 Performance comparison between PTL based and conventional designs Eye Height (mv) P-P Jitter (PS) PSN (mv) DC DC DC *CNV=Conventional Based Design We have also compared the SI performances of the two TVs at different speeds. Fig. 12 shows the eye diagrams measured at the 3rd stacks of the two TVs at 1Gbps and 3Gbps respectively with one active driver on each TV. The performance of design again exceeds that of the conventional design. The peak to peak jitter improves by over 40%. While the eye heights between the two designs are similar at 1Gbps, the eye of the conventional design is significantly reduced at a higher speed of 3Gbps. Table 2 summarizes the measured data. (a) Fig. 12 Measured Eye Diagrams at the 3rd stacks of the Two TV s with 1Gbps and 3Gbps Data rates Table 2 Performance Comparison between Based and Conventional Designs at 1Gbps and 3Gbps at the 3rd Stack Eye Height (mv) P-P Jitter (PS) 1Gbps Gbps *CNV=Conventional Based Design V. Conclusion (b) Fig. 11 (a) Eye diagrams measured at each level of the TVs (b) Plots of the SI and PI Performance Comparison of the PTL-base and Conventional Design TVs In this paper, we present an alternate power delivery network design by proposing to replace conventional power planes with power transmission lines. The advantage of this approach is to eliminate return path discontinuities in a PCB. We further offered a high speed signaling scheme to work in tandem with the PTL design in order to solve impedance mismatch and parasitic inductance issues along the power and ground rail interconnects in a 3D system. To show proof of concept and advantage of our design approach, two 3D test 2264

6 vehicles made of stacked PCBs were made and subsequently tested and measured. The stack consists of three daughter cards stacked on a mother board with sockets in between them, which mimics a 3D IC stack with approximately 160 times more inductance between the stacks. We successfully demonstrated for the first time the measured SI and PI results on a complex 3D stacked test vehicle that implements our proposed alternate PDN design and signaling method, namely constant current power transmission line. The communication between the stacked boards using this new comprehensive method is made possible due to better and more consistent signal and power integrities as compared to the conventional designs. Eye height, jitter and power supply noise measurements for channels operating at 1Gbps and 3Gbps using the alternate methods were shown and compared with the more traditional methods used today. Even with far more decoupling capacitors placed on top of the conventional test vehicle, the SI and PI performance of the PTL-based test vehicle still outperforms the former by significant margins. As an example, the eye height has improved by 104%; p-p jitter and power supply noise have reduced by 53.3% and 72.9% respectively at the 3rd stacked daughter card in the -based test vehicle as compared to the conventionally designed test vehicle when all daughter cards are active. This PTL design concept was also applied to silicon interposer based 3D IC systems with advantages quantified through simulations [4] and [9]. [8] [9] ACKNOLWEDGEMENT This research was supported by NSF under the reward number ECCS The main author would like to thank Professor Swaminathan for his guidance, confidence and support throughout the development of the test vehicles. He would also like to thank Professor Keezer for his valuable feedback during the design and layout of the test vehicles. Professor Keezer also generously provided the access to the many of his lab equipment. REFERENCE [1] [2] [3] [4] [5] [6] [7] S. Huh, M. Swaminathan and D. Keezer, "Constant current power transmission line based power delivery network for single-ended signaling," IEEE Transactions on Electromagnetic Compatibility, Vol. 53, Issue: 4, pp: , S. Huh, D. Chung and M. Swaminathan, Achieving near zero SSN power delivery networks by eliminating power planes and using constant current power transmission lines, in Proceedings of EPEPS, pp , 2009 K. Kim, W. Lee, J. Kim, T. Song, J. Kim, J. S. Pak, J. Kim, H. Lee, Y. Kwon and K. Park, Analysis of Power Distribution Network in TSVbased 3D-IC, Electrical Performance of Electronic Packaging and Systems (EPEPS), Zhang, D.C. ; Swaminathan, M. ; Huh, S., New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high speed I/Os, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). Novak, I., Miller, J., Frequency-dependent characterization of bulk and ceramic bypass capacitors, Electrical Performance of Electronic Packing (EPEP), pp , Novak, I., Power Distribution Network Design Methodologies, IEC publications, December, Larry D. Smith, Raymond E. Anderson, Douglas W. Forehand, Thomas J. Pelc, and Tanmoy Roy, Power Distribution System Design 2265 Methodology and Capacitor Selection for Modern CMOS Technology, IEEE Trans. on AP, vol. 22, no. 3, pp , Kose, S, Friedman, E.G., Distributed power network co-design with on-chip power supplies and decoupling capacitors, th International Workshop on System Level Interconnect Prediction (SLIP), pp. 1-5, June Telikepalli, S.; Zhang, D.C.; Swaminathan, M.; Keezer, D., "Constant Voltage-Based Power Delivery Scheme for 3-D ICs and Interposers," Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol.pp, no.99, 2013