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2 Technical Paper Understanding Power Integrity By definition, power integrity in integrated circuits (IC) is the practice of ensuring and verifying that all the transistors on a chip have proper voltage and current in order to operate at their intended performance levels. A power delivery network is a complex chain of interconnects, designed to deliver electrons from the voltage regulator, through the PCB power delivery network (PDN), across the package, and lastly through the on-die PDN to the transistors themselves. While each aspect of the system s design can contribute to power delivery noise, the engineer must consider the electronic interaction of chip, package and system (CPS) in order to accurately determine the power integrity of a design. To fully understand the full picture of CPS power integrity, the engineer must look at the individual power noise contributions from chip, package and printed circuit board (PCB). Starting at the receiving end of the PDN, on-die, power is delivered through the IC s power connections (wirebond pads or C4 RDL bumps) through the multi-layer power grid. The power grid inherently has non-ideal impedance that ultimately results in voltage drop at the transistors. In the past, technology node voltage drop analysis was solved using a static IR drop methodology. Figure 1. Static IR drop analysis modeling. A DC voltage source modeling the power supply is connected to a chip model. Transistors are modeled as DC average current sources and the PDN is modeled solely by its resistive properties. In a static approach, R&D teams model transistors as time-domain average DC current sources, while the power grid is extracted as a resistance network. All time-dependent passive components are ignored in a static DC average simulation. The full-chip PDN is stitched together as a mesh of current sources and resistors, and subsequently Ohm s law (V=IR) is solved to determine the voltage level at the transistors. Since the industry has migrated to the deep sub-micron technology nodes, analysis methodologies have shifted from an average IR drop paradigm to a dynamic, time-dependent solution that more accurately represents the chip during its operation. In the time domain, power grid capacitance and inductance are included in the mesh. The transistors themselves are modeled as time-varying current sources that depend on the voltage, load and input slew for each logic gate. Figure 2. Dynamic voltage drop analysis modeling. The power supply is connected to a chip model where the transistors are now modeled as time-domain current profi les which are a function of load, VDD level and input slew. The PDN is completely modeled with the R, L and C components necessary for dynamic simulation. All capacitive coupling components are included. The timing of an IC cell switching is a critical factor to correctly analyze the impact of the PDN. A large number of locally placed transistors firing at the same time have a cumulative effect on the peak current demand in a particular region. Standard cell capacitance comes into play, as charge accumulates on both intentional decap cells as well as non-switching standard cells. The current demanded by the dynamically switching transistors must be supplied either by the charge accumulated on these nearby cells or it must come from the off-chip regulator, resulting in dynamic voltage 1

3 Understanding Power Integrity drop. In addition, the extracted power grid mesh (PDN) must now consider capacitive and inductive coupling since these passive elements become a factor due to their time-dependent behavior. Traditional static IR analyses ignore the time-dependent inductance and capacitance; thereby the PDN s resistance plays the only analytic role during analysis. In summary, a dynamic transient power analysis involves the resistance, capacitance and inductance parasitics of the chip and the switching current demand (di dt) of each cell during its operation. Solving for voltage becomes a function of the following equations: V = I 2R, V=L di, and I=C dv dt dt Once the complete mesh is stitched together, a transient circuit solver is used to determine the time-varying voltage v(t) at each transistor, after which sign-off criteria can be weighed against the results. Figure 3. Example of modern 12-layer package layout. IC complexity and multiple power domains drive designs to take on complex geometries thereby increasing package impedance. As mentioned, a system s power delivery network reaches the chip through the package and PCB network. To ensure that the chip receives an adequate amount of stable voltage, the package and PCB design involve reducing impedance at all frequency ranges. As technology scales, the drive to reduce cost and lower power contribute to package and PCB design complexity. For example, in order to reduce package cost, the numbers of layers allowed for package implementation are kept to a minimum. Low-power design methodology involves the technique of creating multiple power domains such that lower performance blocks on-chip can receive a reduced voltage, saving on power consumption, in comparison to high-performance blocks. Because of this trend, engineers are seeing power domain counts in the hundreds. Lack of routing real estate and increased numbers of power domains force designers to move away from the implementation of large planes dedicated to the power and ground domains. Instead, Swiss-cheese type structures are put into place. This significantly adds to package and PCB design complexity, in which the amount of routing layers grows inversely to the power domain count in modern electronic design. Ultimately, these trends contribute to increased package and PCB impedance. Before the power even reaches the die, the design experiences a voltage drop at the chip package interface. This applies to static IR drop, but more significantly in dynamic voltage drop for which time-dependent passive elements (especially inductance) play a critical factor. Typically, in comparison to the chip, the package design is highly inductive in nature. The largest component of power delivery voltage drop in the package is due to inductive voltage drop across the package governed by V=L di dt 2 The package voltage drop itself can constitute 5 percent to 10 percent of the overall voltage drop seen at the transistors from the nominal supply voltage. As can be determined from the last equation, package voltage drop is indeed a function of the package s extracted inductance, but is also scaled by the current demand (di dt) of the chip. The package voltage drop

4 Understanding Power Integrity contribution is not only dependent on the package itself but the chip and PCB as well. This show s the importance of looking at the complete system in regard to power analysis. As seen in time-domain dynamic voltage drop analysis, a large amount of simultaneously switching instances can cause a cumulative spike in current demand from the chip, which must be supplied from the package, PCB and ultimately the VRM. These spikes in current have been shown to be a major cause of design failure especially in high-current modes such automatic test pattern generation (ATPG) test mode, where simultaneous switching is encouraged to ultimately save time and money on the automated test equipment (ATE) test machine. System-wide power integrity must also be solved in the frequency domain. Because impedance is a complex metric Z(ω)=R+ 1 jωl the impedance of the system varies as a function of frequency. Designers must ensure that the PDN impedance is under the specification limits at the frequencies of operation of the design. Typically, engineers look at the impedance at the chip package interface where the package connects to the redistribution layers (RDL) C4 bumps. Figure 4. Typical impedance vs. frequency waveform for a CPS frequency-domain analysis. Impedance calculations and optimal decoupling capacitor locations are determined using hybrid electromagnetic fi eld solvers with optimization algorithms. In general, chips and PCBs are more capacitive with respect to their package counterparts. Likewise, packages are largely inductive compared to the on-die and PCB power delivery networks inductance. With this assumption, the frequency of the impedance peaks (also known as resonant peaks) of the system are largely determined by the LC resonance between chip package and package PCB as determined by f= 1 (2π LC) Typically there are two main resonant peaks in a chip package PCB system. Because of the large size and capacitance of the PCB, the coupling between the package and PCB determines the lower frequency peak that typically resides in the 10 MHz to 500 MHz range, depending on the size of the PCB and amount of placed capacitance. The package chip coupling determines the higher-frequency peak (1 GHz to 5 GHz), which depends largely on package inductance, the more variable metric in the f= 1 (2π LC) equation, in which L refers to L package and C refers to C die. 3 Avoidance of the resonant peaks is critical for the power integrity of a system. Package and PCB designers use techniques such as adding decoupling capacitance to lower the frequency of the peaks and suppress peak magnitude. In addition, chip designers insert decoupling capacitance cells to lower the frequency of impedance peaks, but designers will also avoid switching

5 Understanding Power Integrity the on-die transistors at the frequencies around the resonant frequency associated with their power domains. Simply determining resonant peaks based on one component of the system (chip, package or PCB) provides an incomplete solution, as each component uniquely determines the frequency and magnitude of the peak it corresponds to. The best solution for PDNs is to solve for a CPS solution that includes an IC chip power model, package model and PCB model simultaneously with electromagnetic field solvers. Impedance peak determination is a must-have step in the power integrity sign-off of IC design, as these peaks coincide with the maximum impedance values of the system. Maximum impedance is scaled by a parameter known as the quality factor, or Q, which can be related proportionately to Q ~ Imag{Z} Real{Z} in which Z is the impedance of the system. In oscillator theory, higher Q indicates a lower rate of energy loss relative to the stored energy of the oscillator; the oscillations die out more slowly. Physically speaking, Q is 2π times the ratio of the total energy stored divided by the energy lost in a single cycle, or equivalently, the ratio of the stored energy to the energy dissipated over one radian of the oscillation [1]. For an ideal series RLC circuit, which can be used to represent a chip package PCB PDN, Q is defined as Figure 5. Example of a time domain simulation of a chip package PCB analysis that operates around resonant frequency. Top waveform: current demand of the switching instances of the chip vs. time. Middle waveform: current flow from battery to the chip vs. time. Bottom waveform: voltage noise is observed at the bumps. An exaggerated noise ringing effect can be seen at the bumps. Q = LC R an equation that refers to the parasitics of each component of the system. In a PDN system, resistance and inductance are largely determined by the architecture of the PDN, which is bound to the main goal of PDN routing getting a power signal from the voltage regulator to the transistors, in multiple power domains, without congestion or shorting. In other words, there is a lack of freedom to adjust PDN routing significantly to reduce L or increase R. As with resonance frequency adjustment, designers will add capacitance on the chip, package or PCB with a sub-linear effect on the peak impedance. Minimization of peak impedance contributions from CPS resonance is critical as it directly influences the power noise seen at the chip package interface. Hybrid electromagnetic field solvers provide the Q of the entire system including decoupling capacitors from the IC to the PCB. When the current flow of a power domain happens to coincide with its resonance frequency, an undesired ringing effect occurs as power domain noise is exaggerated and temporally extended. As can be seen in Figure 5, the voltage potential (bottom waveform) at the C4 bumps of the design takes on a diminishing sinusoidal form, in which the magnitude and time to dampen are determined by the quality factor of the system. 4

6 Understanding Power Integrity Resonant frequency avoidance is critical in ensuring power integrity. A design might be under the voltage noise limits under normal conditions, but operating at resonant frequency will almost always result in failure due to the exaggeration of power noise. In the above example, voltage noise seen at the bumps reaches 94 percent of ideal voltage in a chip-only dynamic voltage drop analysis. However, once the package and PCB models are added to the analysis and resonance is seen, voltage drop exceeds 12 percent of ideal voltage. As can also be observed, voltage and current overshoots occur, which is an effect only of resonant ringing. Summary Numerous factors contribute to the power noise of a system. The chip, package and PCB each contribute to power noise individually, but numerous power integrity issues are affected by the mutual interaction of these various components of the system. This can be observed in time-domain voltage drop analysis, frequency domain impedance minimization and resonance frequency avoidance. In summary, power integrity must be analyzed in the context of the complete system to solve the interactive complexities of the system. Reference [1] Jackson, R. (2004). Novel Sensors and Sensing. Bristol: Institute of Physics Pub. pp. 28. Keywords Power integrity, power delivery network, power optimization, chip package system, CPS ANSYS, Inc. Southpointe 275 Technology Drive Canonsburg, PA U.S.A ansysinfo@ansys.com 2013 ANSYS, Inc. All Rights Reserved. ANSYS, Inc. is one of the world s leading engineering simulation software providers. Its technology has enabled customers to predict with accuracy that their product designs will thrive in the real world. The company offers a common platform of fully integrated multiphysics software tools designed to optimize product development processes for a wide range of industries, including aerospace, automotive, civil engineering, consumer products, chemical process, electronics, environmental, healthcare, marine, power, sports and others. Applied to design concept, final-stage testing, validation and trouble-shooting existing designs, software from ANSYS can significantly speed design and development times, reduce costs, and provide insight and understanding into product and process performance. Visit for more information. Any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. All other brand, product, service and feature names or trademarks are the property of their respective owners.