Lecture 4 ECEN 4517/5517

Transcription

1 Lecture 4 ECEN 4517/5517 Experiment 3 weeks 2 and 3: interleaved flyback and feedback loop Battery 12 VDC HVDC: VDC DC-DC converter Isolated flyback DC-AC inverter H-bridge v ac AC load 120 Vrms 60 Hz d d Feedback controller V ref Digital controller Step-up dc-dc converter with isolation (flyback) Feedback controller to regulate HVDC Parallel two flybacks with phase-shifted gate drive signals 1

2 Due dates and goals Right now: Prelab assignment for Exp. 4 Part 1 (one from every student) Due within five minutes of beginning of lecture This week in lab (Feb. 3-5): Final reports for Exps. 1 and 2 due Begin Exp. 3: construct and debug basic flyback power stage Next week in lab (Feb ): Get parallel flyback power stages working at 85 W Begin simulation of ac transfer functions and feedback loop design 2

3 Goals in upcoming weeks Exp. 3: Flyback step-up dc-dc converter Exp. 3 Part 1: Design and fabrication of flyback transformer Snubber circuit Demonstrate flyback converter power stage operating open loop V batt snubber v HVDC Exp. 3 Part 2: Construct, debug, and demonstrate paralleled flyback converters producing 85 W PWM Compensator Exp. 3 Part 3: Design feedback loop Measure loop gain, compare with simulation and theory Demonstrate closed-loop control of converter output voltage V ref 3

4 Layout of power stage Identify loops having high di/dt (pulsating currents). Since v = L di/di, stray inductance in these loops leads to voltage spikes and ringing on components (usually the MOSFET) that can exceed their peak voltage ratings. Minimize the inductance of the critical loops: keep area of loop small, use twisted pairs, add bypass capacitors. 4

5 Effect of transformer leakage inductance V g i g L l v l L M Transformer model i Q 1 1:n v T D 1 C R v Leakage inductance L l is caused by imperfect coupling of primary and secondary windings Leakage inductance is effectively in series with transistor Q 1 When MOSFET switches off, it interrupts the current in L l L l induces a voltage spike across Q 1 v T ir on Voltage spike caused by leakage inductance { DT s V g v/n t If the peak magnitude of the voltage spike exceeds the voltage rating of the MOSFET, then the MOSFET will fail. 4

6 Protection of Q1 using a voltage-clamp snubber V g i g R s Snubber { v s C s Usually, Cs is large Q 1 Flyback transformer 1:n v T D 1 C R v Snubber provides a place for current in leakage inductance to flow after Q 1 has turned off Peak transistor voltage is clamped to V g v s v s > V/n Energy stored in leakage inductance (plus more) is transferred to capacitor C s, then dissipated in R s Decreasing R s decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating C s and R s 5

7 Overvoltage on output diode Diode turn-off (reverse recovery) transition: i g L l1 v l Transformer model i 1:n L l2 D 1 Transformer leakage inductance causes voltage ringing and overshoot on secondary diode V g L M Q 1 v T C R v Leakage inductance plus diode output capacitance form resonant circuit: secondary induced voltage v i i L L v L Silicon diode i B v B leakage inductance C diode capacitance i L 0 v B 0 Area Q r t t V 2 t 1 t 2 t 3 6

8 Diode snubber Damp the ringing with R-C snubber network L l1 Transformer model L l2 D 1 i g v l1 i 1:n v l2 V g L M Q 1 v T Diode snubber C R v Snubber capacitance similar in value to diode capacitance Snubber resistance similar in value to resonant circuit characteristic impedance More capacitance and/or smaller resistance lower peak voltage, larger snubber loss 7

9 Limits on maximum output power Week 1 circuit Wiring inductance causes ac component of i flyback to flow through capacitor C, while the dc component flows from the battery Capacitor rms current must not exceed the rating of 4.42 A Decreasing converter efficiency caused by snubber and other losses, along with capacitor current rating, limit the maximum output power How much output power can you produce? 8

10 Increasing the output power Week 2 circuit Interleaving of parallel-connected flyback converters: AC components of phase-shifted input current waveforms partially cancel out Less rms capacitor current per unit of output power 9 Produce 85 W output power by end of week 2

11 Exp. 3 Part 3 Regulation of output voltage via feedback v HVDC Model and measure control-to-output transfer function G vd (s) Design and build feedback loop V batt snubber Measure loop gain to verify phase margin and crossover frequency PWM Compensator V ref Demonstrate closed-loop regulation of v HVDC 10

12 Negative feedback: a switching regulator system Power input Switching converter Load i load v g v H(s) Sensor gain Transistor gate driver Pulse-width modulator v c G c (s) Compensator Error signal v e Hv Reference input v ref 11

13 Transfer functions of some basic CCM converters Table 8.2. S alient features of the small-signal CCM transfer functions of some basic dc-dc converters Converter G g0 G d0 0 Q z V 1 buck D D R C LC L 1 V D' boost D' D' D'R C D' 2 R LC L L buck-boost D' D V D' DD' 2 D'R C D' 2 R LC L DL where the transfer functions are written in the standard forms G vd (s)=g d0 1 s z 1 s Q 0 s 0 2 G vg (s)=g g0 1 1 s Q 0 s 0 2 Flyback: push L and C to same side of transformer, then use buck-boost equations. DC gains G g0 and G d0 have additional factors of n (turns ratio). 12

14 Bode plot: control-to-output transfer function buck-boost or flyback converter example G vd 80 dbv G vd G vd 60 dbv 40 dbv 20 dbv G d0 = 187 V 45.5 dbv f Hz Q = 4 12 db 40 db/decade 0 dbv 20 dbv G vd /2Q f Hz f z / Hz f z 2.6 khz RHP 20 db/decade dbv 10 1/2Q f Hz f 10f z 26 khz 10 Hz 100 Hz 1 khz 10 khz 100 khz MHz 13

15 The loop gain T(s) Loop gain T(s) = product of gains around the feedback loop More loop gain T leads to better regulation of output voltage T(s) = G vd (s) H(s) G c (s) / V M Power input v g Transistor gate driver Switching converter Pulse-width modulator G vd (s) = power stage control-to-output transfer function PWM gain = 1/V M. V M = pk-pk amplitude of PWM sawtooth v c G c (s) v i load Error signal v e Compensator Reference input Load v ref Hv H(s) Sensor gain 14

16 Phase Margin A test on T(s), to determine stability of the feedback loop The crossover frequency f c is defined as the frequency where T(j2 f c ) = 1, or 0 db The phase margin m is determined from the phase of T(s) at f c, as follows: m = 180 (T(j2 f c )) If there is exactly one crossover frequency, and if T(s) contains no RHP poles, then the quantities T(s)/(1T(s)) and 1/(1T(s)) contain no RHP poles whenever the phase margin m is positive. 15

17 Example: a loop gain leading to a stable closed-loop system T 60 db 40 db T T 20 db f p1 f z Crossover frequency 0 db T f c 0 20 db db m Hz 10 Hz 100 Hz 1 khz 10 khz 100 khz (T(j2 f c )) = 112 m = = 68 f 16

18 Transient response vs. damping factor v Q = 50 Q = 10 Q = 4 Q = Q = 1 Q = 0.75 Q = 0.5 Q = 0.3 Q = 0.2 Q = 0.1 Q = 0.05 Q = c t, radians 17

19 Q vs. m Q 20 db 15 db 10 db 5 db 0 db 5 db Q = 1 0 db m = 52 Q = db 10 db m = db 20 db m 18

20 8.4. Measurement of ac transfer functions and impedances Network Analyzer Injection source Measured inputs Data v z magnitude v z frequency v y v x 17.3 db Data bus to computer v z output v x input v y input v y v x Fundamentals of Power Electronics 94 Chapter 8: Converter Transfer Functions

21 Swept sinusoidal measurements Injection source produces sinusoid of controllable amplitude and frequency Signal inputs and perform function of narrowband tracking voltmeter: Component of input at injection source frequency is measured Narrowband function is essential: switching harmonics and other noise components are removed Network analyzer measures v x v y v z v y v x and v y v x Fundamentals of Power Electronics 95 Chapter 8: Converter Transfer Functions

22 Measurement of an ac transfer function DC blocking capacitor Injection source v z magnitude v z output v z frequency Network Analyzer Measured inputs v x v y input input v y v x v y v x Data 4.7 db Data bus to computer v y (s) v x (s) = G(s) Potentiometer establishes correct quiescent operating point Injection sinusoid coupled to device input via dc blocking capacitor DC bias adjust V CC input G(s) Device under test output Actual device input and output voltages are measured as v x and v y Dynamics of blocking capacitor are irrelevant Fundamentals of Power Electronics 96 Chapter 8: Converter Transfer Functions

23 Voltage injection 0 Block 1 Block 2 i(s) Z 1 (s) Z s (s) v z v ref (s) v e (s) G 1 (s)v e (s) v y (s) v x (s) Z 2 (s) G 2 (s)v x (s) = v(s) T v (s) H(s) Ac injection source v z is connected between blocks 1 and 2 Dc bias is determined by biasing circuits of the system itself Injection source does modify loading of block 2 on block 1 Fundamentals of Power Electronics 64 Chapter 9: Controller design

24 Averaged switch modeling Basic approach (CCM) Given a switching converter operating in CCM 1:n D 1 Flyback converter example V g L M Q1 C V Separate the switching elements from the remainder of the converter v g L M 1:n C v Define the terminal voltages and currents of the two-port switch network v 1 i 1 Q 1 D 1 Switch network v 2 i 2 ECEN

25 Terminal waveforms of the switch network v 1 v g v 2 /n 1:n v 1 Ts i 1 i M dt s T s t v g L M i M i 1 v 2 C v i 1 Ts v 1 i dt s v 2 nv g v T s t Switch network d v 2 Ts dt s i 2 i M /n i 2 Ts dt s ECEN 4517 t 2 T s T s t Relationship between average terminal waveforms: v 1 T = d v nd 2 T i 2 T = d i nd 1 T

26 Averaged model of switch network i 1 Ts i 2 Ts From previous slide: v 1 T = d nd i 2 T = d nd v 2 T i 1 T v 1 Ts d nd v 2 T d nd Averaged switch network i 1 T v 2 Ts Modeling the switch network via averaged dependent sources ECEN

27 PSpice model CCM3 ********************************************************** * MODEL: CCM3 * Application: two-switch PWM converters, * with (possibly) transformer * Limitations: ideal switches, CCM only ********************************************************** * Parameters: * n=transformer turns ratio 1:n (primary:secondary) ********************************************************** * Nodes: * 1: transistor positive (drain of an n-channel MOS) * 2: transistor negative (source of an n-channel MOS) * 3: diode cathode * 4: diode anode * 5: duty cycle control input **********************************************************.subckt CCM params: n=1 Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n} Gd 4 3 value={(1-v(5))*i(et)/v(5)/n}.ends *$ ********************************************************** i 1 Ts v 1 Ts 1 2 CCM3 Included in the file Switch.lib on course website 5 d 3 4 i 2 Ts v 2 Ts ECEN

28 PSPICE simulation Open-loop simulation of control-to-output transfer function 1:n v g L M C v i M 1 CCM d 4 Replace flyback converter switches with averaged switch model CCM3 and other PSPICE model library elements are linked on course web page Apply dc voltage (to set steady-state duty cycle) plus ac variation to terminal 5 of CCM3. Plot output voltage magnitude and phase ECEN