Development and Validation of IC Models for EMC

Transcription

1 Development and Validation of D. Beetner Missouri University University of Missouri of Science - Rolland Technology UMR EMC Laboratory 1 Who is the UMR/MS&T EMC Laboratory? People 5 professors 3 graduate students 4 research professor/post docs Secretary, research engineer, and more Research Sponsorship UMR/MS&T EMC consortium Individual company projects Department of Defense, National Science Foundation, NASA, et al. Research Fundamental research in electromagnetic compatibility and signal integrity EMC at system and PCB levels EMC at IC and package levels ESD and immunity Signal/Power Integrity RFI coupling in wireless systems Unique Strengths $4M+ state-of-the-art experimental laboratory Superior EM modeling capabilities for real-world applications Accumulated expertise in EMC, SI, and PI over more than a decade Unique focus on real-world engineering with a solid tracking record D. Beetner 2

2 Introduction Board designers no longer satisfied with EMC solutions at PCB-level. Managing power integrity and emissions (and immunity) requires decoupling Where? How? EMC performance not obvious from layout Try and see approach cost prohibitive D. Beetner 3 Introduction IC models allow: Prediction of emissions and immunity performance Optimization of IC and board design Discovery of on-chip powerintegrity issues Target Z PCB IC Emissions (dbm) Semi-anechoic chamber Without Ferrite With Ferrite Z Actual Frequency (MHz) D. Beetner 4

3 IC-Level Modeling Talk Overview Modeling of an Altera Stratix II FPGA for power integrity Modeling of an automotive microcontroller for conducted emissions Modeling of a microcontroller for immunity D. Beetner 6

4 Modeling of an Altera Stratix II FPGA for Power Integrity D. Beetner 7 Overview Tool flow for current prediction Brief overview of Quartus II development software Power Play Power Analyzer Role of transient current in system modeling Dynamic current modeling PCB design Measurement and correlation of prediction Measurement setup Impedances measurements and simulations Correlation of measurements and modeling D. Beetner 8

5 Quartus II Development Software Tool Flow System design I/O assignment and analysis Functional simulation Design rule checking RTL viewer Scripting support Chip editor In-system verification RTL synthesis Place and route Power analysis Static timing analysis Technology map viewer Board-level timing Gate-level simulation Formal verification Board-level signal integrity analysis Focus on these parts of tool suite D. Beetner 9 FPGA Tool Flow for Current Waveform Average dynamic power analysis (with vectors) User-supplied vectors in timing simulation generate a signal activity file Joules (J n ) per transition for every node (n) is known by PowerPlay Result is time-averaged current for a time T >> clk period: P = 1 T Modified gate-level simulation Accurate timing simulation of actual placement and routing in FPGA Instantiate all nodes into simulation (including interconnect) Timing of every node in design is available for power analysis T J n n Modified power analysis Run repetitive power analysis where time step τ << clock period Result is time-averaged current for each small time slice Plot result of all instantaneous power analysis to get current waveform D. Beetner 1

6 Modified Power Analysis Result INPUT cl k VCC GN D CNG_FF_5 tff out en _cl put abl CNG_FF_5 k e tff out en _cl put abl CNG_FF_5 k e tff out en _cl put abl CNG_FF_5 k e tff out en _cl put abl CNG_FF_5 k e tff out en _cl put abl CNG_FF_5 k e tff out en _cl put abl k e OR 6 inst 4 OUTPUT Rising clock edge Falling clock edge Logic toggles Reconstructed time domain current for a large number of toggle flip-flops D. Beetner 11 Current Waveform in Frequency Domain 5 frequency-domain current waveform -5 noise current [dbma] Frequency [MHz] Perform Fourier transform to get current waveform as a current spectrum D. Beetner 12

7 Prediction of PCB power noise Switching logic creates power supply voltage variations Test voltage variation at different points on PDN FPGA switching logic affects power supply voltage Noise at port 3 noise on power bus near FPGA Noise at port 1 noise spreading across PCB through PDN Port 1 VCC Core Port 3 FPGA Port 2 D. Beetner 13 Test PCB for V cc Core Noise Correlation Far-point SMA connector Near-point pad SIG1 VCCN 1" JTAG GND PWR1 GND Port2 1 SIG2 GND GND VCC 1" PWR3 GND SIG3 GND PWR2 GND SIG4 VCCPD FPGA Port1 3 Back drill via Power planes: VCC, VCCN, VCCPD FR4 dielectrics Signal layers Ground planes SMT capacitor pads for 85, 63, 43 Power Supply BNC connectors (sensing line) Bulk Capacitor VCC SMA connector FPGA dedicated clock input SMA U33 D. Beetner 14

8 System Equivalent Circuit Model Construct equivalent circuit model to determine package and die effect HSPICE simulation IC Cdie Rdie GND Package PDN PWR M Lpkg Cpkg GND Lball Cball Lball PWR LPCB CPCB PCB PDN EZPP simulation (MS&T tool) Self inductance and mutual inductance of soldering balls were reduced to a single L. D. Beetner 15 MS&T EZPP Cavity Modeling Tool z b Port 1 y Port 2 Z Z Port 1 Port 2 Z Z Distance between two planes is very small compared to wavelength d << λ Electric field can be assumed to be constant on Z-directed propagation Equivalent impedance can be obtained from board geometry ε a d x D. Beetner 16

9 Validation of Simulated PDN Impedance Z 31 from port 1 to port 3 Z 11 at port 1 5 Transfer impedance (db Ohm) Measurement Simulation Self Impedance (db Ohm) Measurement Simulation Frequency (Hz) Frequency (Hz) Measurement and simulation with Bare board, no external decoupling capacitors Board powered on Good correlation of transfer impedance simulation D. Beetner 17 PDN Noise Estimation Formula Spectrum analyzer V Z = 5 Ω 1 V Z Z I = V 2 Z21 Z 22 I 2 = Z I where V 1 I1 5 = Ω V V = Z I + Z I = Z ( ) + Z I I (1 + Z / 5) 11 V1 PCB + package + on-die capacitance P spec V2 2 1 Z21I2 Z + Z11 = V = 2 (1 /5) I2 From power analysis 2 /1 I 2 is from power analysis Z 21 and Z 11 are both from impedance simulation D. Beetner 18

10 Correlate Noise Spectrum at Port 1 5 frequency-domain current waveform Amplitude [db Ω] noise current [dbma] Frequency [MHz] Z 21 Z 11 Quartus PowerPlay Impedance simulation Noise Power [dbm] calculated measured Frequency [MHz] 1 MHz, 3% registers as TFFs Frequency [Hz] Measured with a spectrum analyzer D. Beetner 19 Correlate Noise Spectrum at Port 3 5 frequency-domain current waveform 45 Amplitude [db Ω] noise current [dbma] Frequency [MHz] Z 32-8 Z 33 Quartus PowerPlay Impedance simulation Noise Power [dbm] calculated measured Frequency [MHz] 1 MHz, 3% registers as TFFs Frequency [Hz] Measured with a spectrum analyzer D. Beetner 2

11 Correlate Noise Voltage at Port 1 Convert noise spectrum calculation to time domain Use inverse Fourier transform Calculated values preserve all complex components Replace spectrum analyzer with oscilloscope Voltage [mv] Calculation Measurement Time [ns] 1 MHz, 3% registers as TFFs D. Beetner 21 Correlate Noise Voltage at Port Voltage [mv] Calculation Measurement Time [ns] 5 MHz, 3% registers as TFFs Accuracy is maintained at higher frequency D. Beetner 22

12 Effect of De-Caps on PDN Impedance 1 1 Transfer Transfer function function from from Port 3 Port to Port 3 to 1 Port (bare 1 board) Shifted resonance Package/die resonance Transfer Transfer Impedance Impedance [db [db Ω] Ω] Capacitance of decaps -5 Die capacitance no decap 16 decaps Frequency [MHz] Port 3 Port 1 Bulk capacitor 5 caps FPGA 1 caps At low frequency, Z 21 is reduced by approximately 37 db At high frequency, de-caps have no effect D. Beetner 23 Impedance Modeling for PCB With De-Caps Transfer Impedance [dbω] Transfer Z 21 function from core from to far point port (16 3 decaps) to port 1 simulated measured Cap values: 85 : ESR : ESL (cap L + L above planes) 1 uf: 1 m : 1.2 nh : ESR : ESL (cap L + L above planes) 2.2 uf : 15 m: 1 nh uf : 15 m : 1 nh - 5 BULK : ESR : ESL (cap L + L above planes) 33 uf : 6 m : 15 nh Frequency [MHz] D. Beetner 24

13 Effect of De-Caps on PDN Noise Spectrum 1 MHz, 3% registers as TFFs, measured at far-point (Port 1) Noise Power [dbm] calculated measured Frequency [MHz] NO De-Caps Noise Power [dbm] calculated measured Frequency [MHz] WITH De-Caps D. Beetner 25 Effect of De-Caps on PDN Noise Voltage 2 1 MHz, 3% registers as TFFs, measured at far-point (Port 1) Voltage [mv] -1-2 Voltage [mv] Calculation Measurement Time [ns] NO De-Caps -3 Calculation Measurement Time [ns] WITH De-Caps D. Beetner 26

14 Effect of De-Caps on PDN Noise Voltage 5 MHz, 3% registers as TFFs, measured at far-point (Port 1) Voltage [mv] 1-1 Voltage [mv] Calculation Measurement Time [ns] NO De-Caps -2-3 Calculation Measurement Time [ns] WITH De-Caps D. Beetner 27 Modeling of Emissions from a Microcontroller D. Beetner 28

15 The Microcontroller Emissions Model IC PDN and switching currents modeled using Apache RedHawk/Sentinel-CPM IC package modeled using Optimal Corporations PakSI-E 3D FEM tool D. Beetner 29 IC Model Validation 1 3 Bare chip, on Vdd Model simulation Vdd v, VddIO v, Power -3 dbm Parallel package capacitance may be under estimated. Z 11 (Ω ) Parallel resistance, 1 transistors 1 may be on. Resistance of Package model may be a bit high Frequency (Hz) Vss, VssIO, and reset are connected D. Beetner 3

16 Overall PCB Model Validation Measurement of bare board Measurement with all parts except IC Simulation including communication ICs SPICE simulation with 7 decaps S 12 (db) series RLC from1 μf series RLC from 33 nf Frequency (Hz) D. Beetner 31 IC Model and PCB Model Connection S block cascade in HSPICE Z can also be calculated manually by Z118 = Z Z + Z Z ( ) 1 PCB PCB IC IC oi ii oo oi D. Beetner 32

17 Power Bus Voltage Noise Spectrum -5 Simulation measurement Noise Voltage (dbm) Frequency (MHz) ( ω) = ( ω) ( ω) ( ω) ( ω) V1 j Z12 j I2 j Z1,19 j I19 j 18 current sources inside IC D. Beetner 33 Power Bus Voltage Noise in Time-Domain Noise Voltage (mv) simulation measurement time (ns) ( ) ( ) = ( ) V t ifft V jω 1 1 D. Beetner 34

18 Calibration of the Embedded Loop -1-2 Top -3 Power pin trace S 21 (db) -5-6 Embedded loop Bottom Frequency (Hz) Z 2S S = = ( 1 S11)( 1 S22 ) S12S21 2 jωm M.55nH D. Beetner 35 Pin Current -7-8 Simulation Measurement Trace Current (dba) Frequency (MHz) V I = jωm Top Power pin trace D. Beetner 36

19 Immunity Model of a Microcontroller D. Beetner 37 Concept of the non-linear PDN model VDD VDDAD L w1 R w1 R w2 L w2 Lead frame and bond wire C w1 Z i1 C w2 Lead frame and bond wire Z i2 Current Consumption Z i3 Z i4 VSS C s3 Inter-block network C s4 VSSAD L w3 R w3 R w4 L w4 Lead frame and bond wire C w3 ESD protection diodes C w4 Lead frame and bond wire Capacitances to the PCB GND Package VDD VDD VDDAD C w1 substrate C s3 C s4 C w3 VSS PCB GND The model includes ESD protection diodes, inter-block network, and supply-voltage dependent current consumption model

20 The IC D 1 VDD D 2 L C i1 R i1 w1 R w1 C w1 R R i3 i2 D 3 D C VDD D 4 i3 C i2 C Ri4 i4 VSS1 VDDAD L w4 C w4 VSSAD where C ws2 = C w2 + C s2 C ws3 = C w3 + C s3 C ws5 = C w5 + C s5 for bond wire/substrate-to- PCB capacitances L w2 R w2 D 5 L w5 VSS2 L w3 R w3 C ws2 C ws3 D 7 D 8 8-bit microcontroller with 2 power domains: VDD (VSS1, VSS2) and VDDAD (VSSAD) R i5 C i5 R i6 D 6 Inter-block network C ws5 VSS1 VDD VSS Pin QFP VSSAD VDDAD Inter-block network model extraction Measurement setup Bias - + Bias port 1 port 2 Power Supply(+5V) VNA port 1 port 2 π eq. circuit Port 1 -Y12 Port 2 Y11 + Y12 Y22 + Y12 2.2uF VDD VSS1 VSS2 VDDAD VSSAD Impedance (db Ω) /(-Y12) Zp21 (Biased) Supply voltage = 5 V Zp21 (Unbiased) Supply voltage = V 1 pf 7.7 pf PCB (solid GND on top) S-parameter Y-parameter π eq. circuit Frequency (MHz) Obtain the RC circuit from π eq. circuits at low frequency (below resonance) 4 D. Beetner 4

21 Modeling / Verifications of all passive components VDD (VNA Port 1) L w1 R C i1 R i1 w1 L w4 C w1 C w4 5 Ω R R i3 i2 S11 Zrefl D 3 D C VDD D 4 i3 C i2 Ri4 C i4 VSSAD VSS1 L w2 R D 5 L w2 w5 C ws2 R i5 D 6 C ws5 Ri6 D 7 D 8 VSS2 C i5 8 L w3 R w3 C ws3 7 6 The bond wire inductance is determined from the impedance profile seen from each pin D 1 D 2 Impedance (db ohm) VDDAD (VNA Port 2).1 Impedance seen from VDD C i3 L w1 +L w2 measurement SPICE D. Beetner 41 Frequency (MHz) Modeling of diodes 4 Current (ma) 2 2 VDD Voltage (V) VDDAD SPICE model Curve tracer measurements A Curve tracer is used for V-I curve measurements.model IC + IS=84.25E-12 + N=4.995 I-V curve + RS=5 + IKF=33.326E-6 + CJO=1.E-21 Depletion capacitance + BV=1 Reverse breakdown = 1 V + TT=1.E-18 Reverse recovery sec The SPICE diode model parameters were modified based on the V-I curve 42 D. Beetner 42

22 VDD Complete PDN model D 1 D 2 VDDAD VSS1 VSS2 L w1 2.7nH L w2 3.3nH L w3 3.3nH R w1.75ω R w2.5ω R w3.5ω C w1 C i1 R i1.5pf 3.4pF 1Ω 66Ω (1.1pF) R R i3 i2 2Ω ( Ω) D D VDD D 3 C 4 i3 1μF 1.9nF C 1pF (F) i2 (1.5nF) R (7.7pF) i4 C i4 C ws2 2.1pF C ws3 2.1pF D 7 D 8 R i5 6Ω R i6 66Ω C i5 4pF 39Ω D 5 D 6 Inter-block network L w4 C w4 3.7nH.5pF VSSAD L w5 C ws5 3.7nH 2.1pF Values in the parentheses indicate the values When the supply voltage is V. Some components in inter-block network have different values depending on the supply voltage The diodes and the capacitance between VDD and VSS1 mostly determine the internal current path Verification of the non-linear PDN model EFT Measurement setup V I : Voltage meas. : Current meas. Attenuator EFT generator V 1 nf Ferrite bead I VDD I VSS1 VSS2 VDDAD μ-controller VSSAD Ferrite bead I V 5 V or V Disturbances were injected on the power rail through capacitor using an EFT generator with a supply voltage of 5 V or V The voltage and current on each pin were measured and compared with SPICE simulation results The power supply was decoupled at RF using ferrites 44 D. Beetner 44

23 Non-linear PDN model verification with 5V supply Voltage (V) Measurement, results Voltage on VDD pin Voltage on VDDAD pin Voltage (V) SPICE simulation results Voltage on VDD pin Voltage on VDDAD pin EFT gen. = 5 V Atten. = 4 db Time (ns) Current flowing into VDD pin Current flowing out of VSS1 pin Current flowing out of VDDAD pin Time (ns) Current flowing into VDD pin Current flowing out of VSS1 pin Current flowing out of VDDAD pin Current Current (ma) (ma) 4 2 Current Voltage (ma) (V) Time (ns) Time (ns) Estimation of internal current Current (ma) Supply voltage = 5 V I,EFT I,i1 I,c I,d2 Current (ma) Supply voltage = V I,EFT I,i1 I,d1 I,d2 I,d Time (ns) Time (ns) I, d2 I, d2 I, EFT VDD VSS1 I, i1 I, c Current consumption VDDAD VSSAD I, EFT I, d1 VDD VSS1 I, i1 I, d3 VDDAD VSSAD VSS2 Inter-block network VSS2 Inter-block network ESD protection diodes ESD protection diodes The current path of EFT pulse is significantly affected by the supply voltage level

24 Conclusions Conclusions Accurate IC models can be found using existing modeling tools and/or measurement Good prediction of PDN noise and immunity possible using simple models Frequency domain simulation may be required in some cases Models are useful for understanding voltage/currents inside the IC and impact of PCB design D. Beetner 47