Application Note 5468

Transcription

1 GA High Linearity Wireless Data Power Amplifier for 2.3 to 2.5 GHz Applications Application Note 5468 Introduction This application note describes the GA power amplifier and gives actual performance measurements achieved in a GHz application using Avago s demonstration board. By using a proprietary.25 μm GaAs E-pHET (Enhancement-mode pseudomorphic high electron mobility transistor) process, the GA achieves +29 dbm of linear output power with a 5 V supply. The GA is a 3-stage power amplifier with an on-chip RF output power detector. The GA can be easily shutdown for power savings and switched between the high gain and low gain mode through external voltages. While operating at 5 V and with a 64 QA ¾ FEC rate OFDA input signal, measured performance was: Output Power 29dBm at 2.5% EV Typical performance at 2.4 GHz is: Gain 38 db P1dB 35.5 dbm NF 2.1 db IRL & ORL > 1 db In the low gain mode, the GA gain is attenuated by approximately 23 db compared to the high gain mode. The device has greater than 23 dbm of linear output power at 2.5% EV when operated in the low gain mode. Pin Configuration and Biasing The GA is offered in a 28-lead QFN (Quad Flat No Leads) package with a 5. x 5. mm footprint and.85 mm height. Figure 1 shows the pin configuration and the simplified internal circuitry of the GA Unlike typical depletion-mode phet amplifiers, the enhancement-mode phet amplifier inside the GA employs a positive Vgs (gate-to-source voltage). Therefore only a positive voltage supply is required to bias the amplifier. In this design, 5 V is connected to the Vdd pins (pin 22, pin 23, pin 24, pin 26 and pin 28) to provide bias for the amplifier. All Vdd pins can be connected together to share the same supply voltage with proper DC and RF bypass along the supply line. The Vbias pin (pin 12) is also connected to 5 V. This pin is the voltage supply for the amplifier s biasing, gain switching and detector circuitry. RF IN Vbyp TOP VIEW Vdd1 Gnd Vdd2 Vdd3 Vdd3 Vdd Bypass Switch and Bias RF OUT RF OUT RF OUT Vc1 Vc2 Vc3 Vbias Vdet DC Bias Path Amplifier Path Detector Path Bypass and Biasing Control Path atching Network Figure 1. Pin configuration and simplified internal circuitry

2 High Gain ode and Low Gain ode The GA can be switched between high and low gain modes by an external voltage. The external control voltage is applied to the Vc1, Vc2, Vc3 and Vbyp pins. The function of the Vc1, Vc2 and Vc3 pins is to turn on or off the amplifier and its biasing circuitry. The power amplifier can be easily turned off by applying V to the three Vc pins. The power amplifier is turned on when the Vc pins are supplied with the appropriate voltage. The current and the linearity of the device can also be adjusted by varying the supply voltage at the Vc pins. In this application note, the voltages on Vc1, Vc2 and Vc3 are optimized for maximum linear output power and efficiency. The three Vc pins are tied to a common node through a resistor on each pin: 1.2 kω, 3 Ω and 1.2 kω are connected to pins Vc1, Vc2 and Vc3 respectively. The common node, Vc, is connected to 2.1 V to turn the device on. Quiescent current is 5 ma in both the high gain mode and low gain mode. In addition, the Vc node can be supplied with a different voltage by adjusting the resistor on each Vc pin. Table 1 shows the resistor values needed when the Vc node is connect to different supply voltages. Table 1. Vc voltages versus resistor value on Vc pins. Vc, V R2, Ω R3, Ω R4, Ω k k k 1 k 11 k k 22 k 27 k Figure 2 shows the gain versus Vc plot at small signal condition. (1.2 kω, 3 Ω and 1.2 kω are connected to pins Vc1, Vc2 and Vc3 respectively) Gain, db Gain versus Vc (Pin = -3dBm, Vdd = Vdd_bias = +5V, Vbyp = V) Vc, volts Figure 2. Small Signal Gain versus Vc at 2.4 GHz GA has an on-chip bypass switch. When the bypass switch is turned on by applying 5 V at the Vbyp pin, the first stage amplifier is bypassed and the device is switched to the low gain mode with approximately 23 db of gain attenuation compared to the high gain mode. This low gain mode allows the transmitter system to control the transmit power level and boost the dynamic range of the transmitter. Both the Vc and Vbyp pins are COS compatible and need approximately.5 μs to switch between the high gain, low gain or shutdown modes. Logic output voltages from the microcontroller can be used to control the power amplifier. The current drawn by the Vctrl and Vbyp pins is less than 1 ma. Table 1 shows the COS logic levels needed at the DC pins to switch the amplifiers to different modes. Table 2. Amplifier power mode vs DC pin logic ode Vdd1, 2, 3 Vbias Vc Vbypass High Gain ode Hi Hi Hi Low Low Gain ode Hi Hi Hi Hi Shutdown ode Hi Hi Low Low Turn-ON and Turn-OFF Sequence The power amplifier turn-on and turn-off sequence is very important to avoid damage to the amplifier. As shown in Figure 3, the Vdd pins must be turned on first, followed by the Vbias pin and then the Vc and Vbyp pins. Reverse the sequence during power down. Note that a higher voltage at the Vc pins than at the Vbias pin will cause a high current DC short at the Vc pins. Turn-ON Vdd 1, 2, 3 Vbias Vc1,2,3 Turn-OFF Figure 3. Turn-on and turn-off sequence for DC power pins Vbyp 2

3 Power Detector A power detector is integrated on chip to save PCB space. The power detector provides a DC output voltage which proportional to the output power of the power amplifier. The DC output voltage from the power detector can be fed back to a controller to adjust input power level, bias or gain. GA Demonstration Board Performance Table 2 summarizes the performance of the GA with a 5 V supply at 2.4 GHz. Table 2. RF Performance for the GA at 2.4 GHz with +5 V voltage supply Vdd V +5. Vbias V +5. Vctrl V +2.1 High Gain ode Vbyp V Total Quiescent Supply Current, Iqtotal ma 5 Gain, S21 db 38.5 Input Return Loss, IRL db >1 Output Return Loss, ORL db >1 Linear Output EV* dbm +29 Power Added Efficiency at Linear Pout, PAE % 16.1 Bypass ode Vbyp V +5. Low Gain ode Quiescent Current, Isd ma 5 Gain Attenuation db 23 Input Return Loss db > 1 Linear Output EV* dbm >+23 * easured with WiAX OFDA signal (64 QA ¾ FEC rate OFDA), with 1 Hz bandwidth and duration of 5 ms (5% duty cycle) 3

4 Figures 4a, 4b and 5 show GA performance versus frequency with a 5 V supply. Gain, db Gain Reverse Isolation Freq, GHz Figure 4a. Gain, return loss and reverse isolation versus frequency for the GA in high gain mode with a +5 V supply Reverse Isolation, db Return Loss, db Input Output Freq, GHz Gain, db Gain Reverse Isolation Freq, GHz Figure 4b. Gain, return loss and reverse isolation versus frequency for GA in low gain mode with a +5 V supply Reverse Isolation, db Return Loss, db Input Output Freq, GHz 3 25 Attenuation, db Attenuation Freq, GHz Figure 4c. Gain Attenuation versus frequency for the GA with a +5 V supply 4

5 EV, % EV versus Pout (Vdd = Vbias = +5V) Figure 5. EV versus Output Power for the GA with a +5 V supply in high gain mode. (easured with WiAX OFDA signal, 64-QA, 5% duty cycle, ¾ rate FEC) WiAX Spectrum Emission ask Performance Over Voltage Supply (FCC ask) Figures 6 to 9 show WiAX spectrum emission performance with different supply voltages for the GA The device can be operated at higher voltage supply of 5.5 V to achieve better output power and still maintain compliance with the FCC mask specification. Spectrum Emission@11.5Hz, dbm Figure 6. Spectrum Emission versus Power for the GA at high gain mode with a +5.5 V voltage supply (Vdd = Vbias = +5.5V, Vc = +2.1 V) Spectrum Emission@5.5Hz, dbm Spectrum Emission@11.5Hz, dbm Figure 7. Spectrum Emission versus Power for the GA at high gain mode with a +5 V voltage supply (Vdd = Vbias = +5 V, Vc = +2.1 V) Spectrum Emission@5.5Hz, dbm

6 Spectrum dbm Figure 8. Spectrum Emission versus Power for GA at high gain mode with +4 V voltage supply (Vdd = Vbias = +4 V, Vc = +2.1 V) Spectrum Emission@5.5Hz, dbm Spectrum Emission@11.5Hz, dbm Figure 9. Spectrum Emission versus Power for the GA at high gain mode with a +3.3 V voltage supply (Vdd = Vbias = +3.3 V, Vc = +2.1 V) Spectrum Emission@5.5Hz, dbm GA easure with WLAN Signal Figure 1 shows the EV performance of the GA demonstration board measured with a 64-QA, 54 bps, WLAN OFD input signal. Figures 11a and 11b show the spectrum emission performance of the GA measured with a WLAN 82.11b signal at 29 dbm of modulated output power with a 1 bps and 11 bps data rate. EV, % GHz EV versus Pout (Vdd=Vbias=+5V) Figure 1. EV versus Output Power for the GA with a +5 V voltage supply in high gain mode. (easure with WLAN OFD signal, 64-QA, 54 bps) 6

7 Figure 11a. Spectrum Emission Performance for the GA with a +5 V voltage supply in high gain mode. (easure with WLAN 82.11b signal, DSSS, 11 bps) Figure 11b. EV versus Output Power for GA with a +5 V voltage supply in high gain mode. (easure with WLAN 82.11b signal, DSSS, 1 bps) 7

8 Circuit Schematic and External Components Vdd C29 C1 Vdd1 Vdd2 Vdd3 C5 C9 C11 Z = 5 ohm E = 1.8 deg F = 2.4 GHz C4 L1 C8 C12 Z = 5 ohm E = 11 deg F = 2.4 GHz RF IN C25 Z = 5 ohm E = 6 deg F = 2.4 GHz Z = 5 ohm E = 5.6 deg F = 2.4 GHz C27a C28 RF OUT C26 5 Bypass SWITCH &Bias 17 C27b C Vc1 Vc2 Vc3 C22 R2 R3 R4 C23 C7 Vbyp Figure 11. Application circuit schematic for the GA Vbias Vdet There are no internal blocking capacitors at the RF input and RF output of the power amplifier; thus 7.5 pf capacitors that have small reactance at the operating frequency band are put at both the input and output pins of the power amplifier to isolate DC current from adjacent circuits. The input path of the device has a shunt.4 pf capacitor and a short transmission line to optimize the input return loss. The output of the device has a short transmission line followed by two, shunt 1.8 pf and 2 pf capacitors to optimize both the output return loss and the linear output power. Bypass capacitors are added to the Vdd, Vctrl, Vbias and Vbyp bias lines to eliminate unwanted feedback. The placement and location of the bypass capacitors on the Vdd biasing line is critical for good linear output power. Capacitors C4 and C8 must be placed close to the device. Figure 11 shows the external GA circuit schematic for a GHz application. The transmission line dimensions and bypass capacitor placement is also shown in Figure 11. 8

9 Component Placement and Bill of aterial Component Size Value anufacturer Part Number C9, C μf urata GR31CR61C226E15 C1, C5, C11, C μf urata GR155R71C14KA88 C7, C13, C25, C pf urata GJ1555C1H7R5DB1 C pf urata GJ1555C1H8R2DB1 C pf urata GJ1555C1H2R4CB1 C pf urata GJ1555C1H2R2CB1 C pf urata GJ1555C1HR4BB1 C27a pf urata GJ1555C1H1R8CB1 C27b pf urata GJ1555C1H2RCB1 C nf urata GR155R71E223KA61 L nh Coilcraft 42HP-1NXJLW R1 42 Ω RK73Z1ETTD R Ω RK73B1ETTD122J R Ω RK73B1ETTD31J R Ω RK73B1ETTD122J Figure 12. GA s component placement and bill of material for 2.3 to 2.5 GHz application 9

10 Demonstration Board Layout and Stacking Structure The demonstration board uses 1 mils of ROGERS RO435 as the substrate stacked on FR4 material to get a total thickness of around 62 mils. This gives the PCB better mechanical strength. Both the RF input and RF output traces have 5 Ω impedances. A non-5 Ω line may degrade the return loss and linear output power of the device. The dimensions of the copper trace and gap size to obtain a 5 Ω transmission line on 1 mil ROGERS RO435B (Dielectric Constant, ε r = 3.48) are.57 mm of trace width and.59 mm of gap width on both side of the copper trace. 5 Ω RF input and RF output trace Top View (Top etal) Inner Layer (RF Ground) Figure 13a. Layout and component placement of the demonstration board Bottom View (Ground) Top 1 mils ROGERS RO435.5 oz copper Inner Total Thickness 62 mils (For mechanical strength) Bottom Figure 13b. Stacking structure of the GA demonstration board FR4 material/prepreg (Support aterial) 1

11 Conclusion This application note showed the design and performance of the GA in a wireless data power amplifier application with minimal external components. The GA has exceptionally good linear output power with low power consumption. It is an easy-to-use device with integrated functions such as an output power detector, bypass switch, shutdown mode, and low/high power mode selection in a small 28-pin QFN package. The GA power amplifier is a good choice for wireless data, fixed terminal applications. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 5-1 Avago Technologies. All rights reserved. AV2-2456EN - April 28, 1