Application Note 5446

Transcription

1 Design the Avago MGA-31T6 into a High Gain, Low Noise, Low current GPS LNA Module Application Note 446 Introduction The MGA-31T6 is a low cost and easy-to-use GaAs LNA (Low Noise Amplifier). The LNA is housed in an ultra thin small leadless package (UTSLP) with very low profile (.4 mm) and small footprint (. mm x 1.3 mm). The thin package allows this device to be integrated into a module design. The MGA-31T6 features high gain, low noise figure and high linearity at low current with a low external component count. Its adjustable current offers flexibility on the design. This application note describes the design of LNA circuit at 1.7 GHz at.8 V/4mA. The performance of the device is demonstrated on a low cost 16 mils FR4 material using standard 4 mil x mil (4 size) SMT components. Pin Configuration and Biasing Pin 1 Pin Pin 3 Paddle Figure 1. Pin Configuration (Top View) Pin 6 Pin Pin 4 Pin 1 : Vsd Pin : RF Input Pin 3 : Not Connected Pin 4 : Internally connected to Ground paddle through wire bond Pin : RF Output Pin 6 : Vdd Paddle : Ground Figure 1 shows the pin configuration of the MGA-31T6. The biasing of this device depends on the voltage applied at the Vsd (pin1) and Vdd (pin6) pins. The current across Vdd denoted as Idd is determined by the voltage applied at the Vsd pin. The voltage at Vsd pin can either be directly supplied or via a dropping resistor from a voltage supply. As shown in Figure, Idd increases as the Vsd voltage increases. Likewise, the Isd increases along with increasing Idd. In this design, a common supply of.8 V DC was applied to both Vdd and Vsd pins. A dropping resistor, denoted as R in Figure 4, is used to set the voltage at the Vsd pin in order to obtain a 4 ma Idd current. Figure 3 shows R versus Idd with Vdd set to.8v and a Vsd of either.8 V or 1.8 V. In order to bias the MGA-31T6 at 4 ma, an R of 1 k is needed for Vsd =.8V, and an R of 6 k is needed for Vsd = 1.8V. The actual R could be slightly different than shown in Figure 3 due to SMT resistor tolerance Vsd.. Isd Idd (ma) at Vdd =.8V Figure. Vsd and Isd vs Idd Vsd (V) R (kohm) Vsupply_Vsd=.8V Vsupply_Vsd=1.8V Isd (ma) Idd (ma) at Vdd=.8V Figure 3. R vs Idd

2 MGA-31T6 Demonstration Board The demonstration board is fabricated using 16 mil FR4 material supported by additional layers of FR4 and preimpregnated (pre-preg) material to give a total thickness of 6 mils. This thickness not only gives mechanical rigidity to the whole board but also allows SMA connectors (EF Johnson ) to be easily slipped on both board edges. The traces at the input and output of the device are 8 mil microstrip lines. The ground for the MGA-31T6 is through the center paddle of the package. This paddle must be grounded with minimum inductance. The best way to accomplish this is by using multiple plated via holes in a thin dielectric board. The demonstration board uses six via holes. Each via hole is 8 mils in diameter. Pin 3 and pin 4 are unused pins. They can be left unconnected on the application board. Pin 4 can be grounded using a ohm resistor in a thin and compact PCB. This will be discussed in the Appendix section of this application note. In the demonstration board, the IO pads for pin 3 and pin 4 are left unconnected, as in Figure 4. The excess trace labelled as R3 in Figure 4 is not used in this design. The final trace can be dimensioned identical to the trace at pin 4. Due to the MGA-31T6 s low profile, small IO pads and light weight, the package PCB layout requires special attention. The optimum soldering stencil and land pattern for the UTSLP package can be found in Avago s Application Note 78. Figure 4. Demonstration board layout Top Via Holes 8 mils 16 mil FR4 material. oz copper Inner Total Thickness 6 mils Bottom Figure. PCB stacking structure FR4 material/prepreg (Support Material)

3 Application Circuit As shown in Figure 6, the MGA-31T6 has internal input and output coupling capacitors. External coupling capacitors are not needed in a cascade design. Resistor R sets the voltage at pin 1, which determines the bias current, Idd, into pin 6. By applying a very low voltage at pin 1 (Vsd <.4 V), the MGA-31T6 is put into a low current OFF mode. Figure 7 shows the gain, input return loss (IRL) and output return loss (ORL) versus the Vsd voltage. IP3, NF and stability must be investigated if the MGA-31T6 is intended to be used at currents lower than 4 ma. The input matching circuit is formed by a series inductor, L3, followed by a shunt inductor, L4, for optimum noise figure and IRL. Figure 8 shows the noise and gain circles at 1.7 GHz. The series inductor L3 moves the input impedance close to the Fmin point, opt. The shunt inductor, L4, moves the impedance close to the conjugated in point for good IRL. A series inductor alone on the input is sufficient to achieve the best NF but results in some IRL degradation. Removing L4 increased the IRL to 7 db and simultaneously reduced the gain by about.6 db. The NF did not change significantly with L4 removed. The L biasing inductor together with the C bypass capacitor sets the output matching and also sets input in. The internal output coupling capacitor is also part of the output matching network. C1 is a low frequency bypass capacitor for the Vdd line, and C3 decreases the external noise from the Vsd line. The parallel combination of L1 and R1 improves isolation between the external voltage supply and the matched pin 6. L1 and R1 are optional and can therefore be removed. Essentially, only five components are needed, as a minimum, to use the MGA-31T6; specifically L3 and L4 on the input, L and C on the output, and R for biasing. Vsd Vdd R1 L1 GammaIn L3 C3 R L MGA-31T6 [1] Bias [6] [] [] C1 C Noise CIrcle and INput Matching L3 L4 Figure 6. MGA-31T6 application circuit [3] [4] L4 NC [GND] NC cir_pts (. to 1.) freq (1.7GHz to 1.7GHz) Figure 8. MGA-31T6 input matching and noise circles Gain and Return Losses (db) Gain IRL ORL Idd Vsd (V) Figure 7. Gain, return losses and Idd vs Vsd Idd (ma) 3

4 S-parameter extraction and analysis Excluding the ground pin, the MGA-31T6 is a three port device which consists of three accessible pins: RF input, RF output and Vdd. To extract the s-parameters (.sp file) of the device, the Vdd pin was terminated by L and C as shown in Figure 9. RF input is denoted as Port 1 while RF output is denoted as Port. The value of L used in this measurement is.7 nh (Toko FHL) and C is 47 pf (Murata GRM1 series). The dashed lines in Figure 9 indicate the input and output reference planes of the measurement. Essentially, the measured.sp data models the LNA and the L and C matching components. The MGA-31T6 s-parameter data can be downloaded in a.sp file from the Avago website under the MGA-31T6 design tool section. As shown in Figure, the value of L determines the frequency response of S11 and significantly of S The plots show three different values of L from the same FHL series:. nh,.7 nh and 3.3 nh. The.7 nh inductor gave the best S at 1.6GHz. Using a smaller value of L, such as. nh, shifted the S curves to the left while a larger value of L, such as 3.3nH, shifted the S curves to the right. This shifting trend on the curves provides guidance on selecting the optimum value of L even though the inductor may come from a different manufacturer than used here. The overall trend will be similar. Reference plane Vsd [1] Bias Reference plane Vdd [6] RFin [] RFout [] Figure 9. S parameter test setup VIA (6 via holes) D = 8. mils H =. mils T = 8. mils Rho = 1. W = 1. mils L C db(sp_3n3h..s(,1)) db(sp_n7h..s(,1)) db(sp_nh..s(,1)) db(sp_3n3h..s(1,)) db(sp_n7h..s(1,)) db(sp_nh..s(1,)) db(sp_nh..s(,1)) db(sp_n7h..s(,1)) db(sp_3n3h..s(,1)) freq, GHz freq, GHz Figure. MGA-31T6.sp based plots at.8 V and 4 ma db(sp_3n3h..s(1,1)) db(sp_n7h..s(1,1)) db(sp_nh..s(1,1)) db(sp_3n3h..s(,)) db(sp_n7h..s(,)) db(sp_nh..s(,)) freq, GHz freq, GHz 4

5 1 Figure 11 shows a Smith chart plot of S using different values of L. Figure 1 shows the ADS setup using the.sp file. L and C are part of the.sp file, thus both components are not included in the simulation setup. These components are, however, needed in an actual implementation. sp_3n3h..s(,) sp_n7h..s(,) sp_nh..s(,) sp_nh..s(,) sp_n7h..s(,) sp_3n3h..s(,) freq (1.4GHz to 1.6GHz) Figure 11. MGA-31T6.sp plots at.8 V and 4 ma Term Term1 Num=1 Z= Ohm COAX_MDS TL7 MLIN TL8 Subst="MSub1" W=8. mil L=1. mil SP L3 1 Ref MLIN TL4 Subst="MSub1" W=8. mil L=. mil SP L4 MTEE_ADS Tee1 Subst="MSub1" W1=8. mil W=8. mil W3=8. mil Ref MTAPER MLIN Taper1 TL3 Subst="MSub1" Subst="MSub1" W1=8. mil W=8. mil W=8. mil L=1. mil L=16. mil MLIN TL Subst="MSub1" W=8. mil L=38. mil SP mga31t6 sp of MGA31T6 with L and C 1 Ref MLIN TL Subst="MSub1" W=8. mil L=38. mil MTAPER Taper MLIN Subst="MSub1" TL6 W1=8. mil Subst="MSub1" W=8. mil W=8. mil L=16. mil L=37. mil COAX_MDS TL9 Term Term Num= Z= Ohm S-PARAMETERS S_Param SP1 Start=1. GHz Stop=1.64 GHz Step= MHz OPTIONS Options Options1 Temp=16.8 Tnom= V_RelTol= V_AbsTol= I_RelTol= I_AbsTol= GiveAllWarnings=yes MaxWarnings= VIA V D=8. mil H=. mil T=.7 mil Rho=1. W=. mil MSub MSUB MSub1 H=14. mil Er=4.6 Mur=1 Cond=1.E+ Hu=3.9e+34 mil T=.7 mil TanD=.1 Rough= mil Figure 1. ADS setup to simulate MGA-31T6 performance based on a.sp file

6 Demonstration Board Component Placement and Bill of Materials Figure 13 shows the component placement for the 1.7GHz LNA demonstration board circuit, and Table 1 shows the bill of materials. All the SMT devices in this application note are 4 mil by mil (4 size). The performance using mil by mil components (1 size) can be seen in the MGA-31T6 datasheet. L1, R1 and C3 are optional and can be removed for a final design without much effect on overall performance. Figure 13. MGA-31T6 demonstration board component placement Table 1. Bill of Material Label Value Size Manufacturer Function L1 nh 4 TOKO FH DC isolation (optional) L.7 nh 4 TOKO FH Biasing / Output match L3 nh 4 TOKO FH Input Match for NF L4 39 nh 4 TOKO FH Input Match for IRL C1.1 F 4 Murata GRM1 Low frequency bypass C 47 pf 4 Murata GRM1 Bypass / Output match C3 33 pf 4 Bypass (optional) R1 4 DC isolation (optional) R 1 k 4 Biasing resistor SMA connectors EF Johnson 6

7 Measured RF Performance vs Frequency MGA-31T6 LNA demonstration board performance is shown in Figures 14 to 19. Figure 14 shows the stability factor of the populated demonstration board. The stability factor, k, is greater than one up to GHz. As shown in Figure 1, both input and output return losses were greater than db at 1.7 GHz. The measured gain was above 17dB and the measured reverse isolation was Frequency (GHz) Figure 14. Demonstration board k factor: LNA mode Stability factor,k db(s(,)) db(s(1,1)) db (S (1,1)) db (S (,)) Frequency (GHz) Figure 16. Demonstration board gain(s1) and reverse isolation(s1) vs frequency Amplitude (dbm) Frequency (GHz) Figure 18. Demonstration board IP3 measurement close to 3 db. The measured noise figure was around 1 db, which included SMA connector and board loss. IP3 was measured with an input power of dbm at 1.7 GHz and 1.76 GHz. Figure 18 shows the output spectrum of the IP3 test. Input IP3 was calculated at + dbm. Figure 19 shows gain and Idd versus input power. Input power when the gain is compressed by 1 db, known as Input P1dB, was measured at approximately dbm. db(s(,)) db(s(1,1)) Frequency (GHz) Figure 1. Demonstration board input return loss(s11) and output return loss(s) vs frequency Measured NF Gain (db) db (S (1,1)) db (S (,)) Frequency (GHz) Figure 17. Demonstration board noise figure vs frequency Gain 17. Idd Pin (dbm) Figure 19. Demonstration board gain and Idd vs Pin at 1.7 GHz Idd (ma) 7

8 Out-of-band IP and IP3 performance In today s wireless spectrum, a GPS receiver simultaneously co-exists with other transmitting devices in the PCS, GSM, Cellular and WiFi bands. Intermodulation from these frequencies and devices will de-sense the GPS receiver and decrease performance. To quantify the effect, outof-band (OOB) measurements were performed on the MGA-31T6 application circuit. Figure illustrates the setup used to measure OOB IP and OOB IP3. The second inter-modulated signals (IM) in the GPS band at 17.4 MHz are created when the following frequencies are mixed: 78.4 MHz with 788 MHz and 84.6 MHz with 4 MHz. This section will discuss the OOB IP of the later frequency mixing. The third inter-modulated signal (IM3) will arise when MHz mixes with 18 MHz. Figure 1 shows OOB IM at the GPS frequency as a result of frequency mixing between.4 GHz and 84.6 MHz. The input power at.4 GHz was varied from - dbm to - dbm while the input power at 84.4 MHz was varied from - dbm to - dbm. OOB IM3 at the GPS frequency as a result of frequency mixing between 1.8 GHz and MHz is shown in Figure. The power levels at 1.8 GHz and MHz were varied and charted when IM3 was measured. Signal Generator 1 pre-amp isolator filter Power Combiner Attenuator DUT Spectrum Analyzer Signal Generator pre-amp isolator filter Figure. Out-of-band IP and IP3 measurement setup IM at 17.4MHz (dbm) Pin = -dbm at 84.6MHz -6 Pin = -1dBm at 84.6MHz Pin = -dbm at 84.6MHz Pin = -dbm at 84.6MHz Pin at.4ghz (dbm) Figure 1. Out-of-band IM performance vs Pin IM3 at 17.4MHz (dbm) Pin = -dbm at 171.7MHz Pin = -1dBm at 171.7MHz -8 Pin = -dbm at 171.7MHz Pin = -dbm at 171.7MHz Pin at 1.8GHz (dbm) Figure. Out-of-band IM3 performance vs Pin 8

9 Using the following equations and the measured data from Figure 1 and Figure, OOB IIP and IIP3 can be calculated: IIP = Pin( ) + [Pin( 1) (IM GPS Gain )] IIP3 = Pin( ) +. x [Pin( 1) (IM3 GPS Gain )] With an input power of dbm at.4 GHz and dbm at 84.6 MHz, IM was measured at 6 dbm. OOB IIP was calculated to be +1. dbm. With an input power of db at 1.8 GHz and dbm at MHz, IM3 was measured at 77 dbm. OOB IIP3 was calculated to be +. dbm. OOB IIP can be improved by adding a simple 84.6 MHz LC notch filter at the LNA input, as shown in Figure Based on c =, c = the series notch filter LC LC capacitor, C4, can be calculated. With L4 fixed at 39 nh, C4 is calculated to be around.8 pf for a notch response at 84.6 MHz. Figure 4 shows the forward gain, S1, frequency response of the board with C4 inserted. There is a dip of about 7 dbm around 84.6 MHz. Vsd R1 Vdd L1 As shown in Figure, the modified application circuit has improved IM by about db. Performance can be improved further if multiple LC notch filters are added. To improve OOB IIP significantly, a filter is needed in front of the LNA. Avago offers a LNA GPS module with a filter in front of the LNA, the ALM-191. Figure shows the measured IM of this module as well as the original and modified MGA-31T6 circuits. The ALM-191 module has superior IM performance compared to the MGA-31T6 with the LC notch filter. The ALM-191 s OOB IIP performance exceeds +8 dbm with a.4 GHz, dbm input. db(meas_notch_lc..s(,1)) db(meas_original..s(,1)) 1 db (meas_original..s (,1)) db (meas_notch_lc..s (,1)) freq, GHz Figure 4. S1 response with LC notch filter L3 C3 R L MGA-31T6 [1] Bias [6] [] [] C1 C IM at 17.4MHz (dbm) MGA-31T6 (original) MGA-31T6 (modified) ALM-191 Pin at -dbm at 84.6MHz Notch filter C4 L4 [3] [4] NC [GND] NC Pin at.4ghz (dbm) Figure. OOB IM performance Figure 3. Notch filter circuit 9

10 RFout (dbm) Vdd=.8V, Vsd=V Vdd=.8V, Vsd=.8V Turn OFF TurnON -dbm at 1.7GHz Signal Generator DC Power Supply Vdd =.8V RFin DUT Vsd = V to.8v Waveform Generator RFout usec Sync Spectrum Analyzer Time (usec) Figure 6. MGA-31T6 switching time MHz Ref line Figure 7. Measurement setup for turn-on and turn OFF time of the MGA- 31T6 LNA Turn-On and Turn-Off Time with Vsd Pin The MGA-31T6 LNA can be turned ON and OFF by applying a specific voltage to Vsd. The voltage at pin 6 was held at.8 V throughout the switching process. In the OFF state (Vsd = V), Idd was measured below A. Figure 6 shows switching time of the application circuit. The LNA took approximately.4 s time to switch between ON and OFF states. Switching time was measured by applying a dbm, 1.7 GHz CW signal to the RF input with.8 V applied at the Vdd pin. A square wave from V to +.8 V, with a period of sec, was applied to the Vsd pin to switch the device. Summary The MGA-31T6 s high gain, low noise and high linearity make it suitable as a front end amplifier for a GPS receiver. The performance of the LNA, as measured on the demonstration board, is summarized in Table and Table 3 across different Idd and Vdd levels. The same application circuit can also be used in GLONASS (GLObal NAvigation Satellite System) receiver. Table 4 summarizes the performance at the high side of GLONASS frequency band 16.8MHz. Designed for GPS/ISM/WiMAX applications in the.9 to 3. GHz frequency range, the MGA-31T6 LNA uses Avago Tech nologies proprietary GaAs Enhancement-mode phemt process to achieve high gain with very low noise figure and high linearity. Table. MGA-31T6 RF performance at 1.7 GHz versus Vdd Voltage, Vdd V Current, Idd ma Gain, S1 db Input Return Loss, IRL db Output Return Loss, ORL db Noise Figure, NF db IIP3 * dbm Input P1dB dbm P1dB ma Stability Factor, k (up to GHz) >1 >1 >1 >1 >1 Out-of-Band IIP ** dbm Out-of-Band IIP3 *** dbm * f1 = 1.7 GHz, f = 1.76 GHz with input power of dbm per tone. ** f1 =.4 GHz with Pin = dbm, f = 84.6 MHz with Pin = dbm. *** f1= 1.8 GHz with Pin = dbm, f = MHz with Pin = dbm.

11 Table 3. MGA-31T6 RF performance at 1.7 GHz versus Idd Voltage, Vdd V Current, Idd ma Gain, S1 db Input Return Loss, IRL db Output Return Loss, ORL db Noise Figure, NF IIP3 * dbm Input P1dB dbm P1dB ma Stability Factor, k (up to GHz) >1 >1 >1 >1 Out-of-Band IIP ** dbm Out-of-Band IIP3 *** dbm * f1 = 1.7 GHz, f = 1.76 GHz with input power of dbm per tone. ** f1 =.4 GHz with Pin = dbm, f = 84.6 MHz with Pin = dbm. *** f1= 1.8 GHz with Pin = dbm, f = MHz with Pin = dbm. Table 4. MGA-31T6 RF performance at 1.68 GHz versus Vdd Voltage, Vdd V Current, Idd ma Gain, S1 db Input Return Loss, IRL db Output Return Loss, ORL db 11 Noise Figure, NF db IIP3 * dbm Input P1dB dbm P1dB ma Stability Factor, k (up to GHz) - >1 >1 >1 >1 >1 Out-of-Band IIP ** dbm Out-of-Band IIP3 *** dbm * f1 = 16.8 MHz, f = MHz with input power of dbm per tone. ** f1 = 43.4 MHz with Pin = dbm, f = 84.6 MHz with Pin = dbm *** f1 = 1.8 GHz with Pin = dbm, f = MHz with Pin = dbm References and Additional Information 1. Avago MGA31T6 datasheet.. Application Note 78: MGA-63T6 UTSLP Package Application Note. 11

12 Appendix: Design for stability on thin board In a thin PCB i.e. lower than 8mil thick, Pin 4 is recommended to be grounded using a zero ohm resistor. The left unconnected Pin 4 on this thin board would cause a peak gain at around 1GHz and occasionally positive IRL at 1GHz. This phenomenon will lead into circuit s oscillation shown by higher Idd than typical current and poor gain at the GPS frequency. It is not advisable to have a direct via hole ground underneath Pin4 because this pin needs to see a small inductance to ground. A 1 zero ohm is perfect for this. This approach helps to improve the abovementioned stability. As the Pin4 is grounded with zero ohm resistor, the input matching requires minor adjustment on the value of shunt and series inductor used at the input match. Nevertheless, the RF performances with this approach are very similar to the thick board discussed in this application note. The following Figure 8 shows the effect of grounding Pin4 with 4 ohm resistor on 4 mil FR4 board. Figure 9 illustrates a board layout with Pin4 grounded via 1 ohm resistor. db(unconnected_pin4..s(,1)) db(ground_pin4..s(,1)) Peak gain Gain (db) - -4 oscillation freq, GHz Figure 8. Gain over frequency, unconnected Pin4 vs. grounding Pin4 with ohm ohm Figure 9. Pin4 with ohm For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. AV-7EN - June,