Data Sheet. MGA ( ) GHz 29dBm High Linearity Wireless Data Power Amplifier. Features. Description. Component Image.

Transcription

1 MGA ( ) GHz 29dBm High Linearity Wireless Data Power Amplifier Data Sheet Description Avago Technologies MGA is a power amplifier for use in the ( )GHz band. High linear output power at 5V is achieved through the use of Avago Technologies proprietary 0.25um GaAs Enhancement-mode phemt process. It is housed in a miniature 5.0mm x 5.0mm x 0.85mm 28-lead QFN package. It also includes shutdown and switchable gain functions. A detector is also included on-chip. The compact footprint coupled with high gain and high efficiency make the MGA an ideal choice as a power amplifier for IEEE (WiMAX) and WLL applications. Component Image 5.0 x 5.0 x 0.85 mm 3 28-lead QFN Package (Top View) Vdd1 Gnd Vdd2 Vdd3 Vdd3 Vdd3 Features High gain: 38.5dB High linearity performance: 29.2dBm at 5V supply (2.5% EVM, 64-QAM ¾ FEC rate OFDMA, 10MHz bandwidth) High efficiency: 16.1% Built-in detector and shutdown switches Switchable gain: 23.6dB attenuation using one single CMOS compatible switch pin ETSI spectral mask compliant at 29dBm output power GaAs E-pHEMT Technology [1] Low cost small package size: 5.0 x 5.0 x 0.85 mm 3 MSL-2a and lead-free Usable at 3.3V supply for lower supply voltage applications YYWW XXXX RFin Vbyp Vc1 Vc2 Vc3 Gnd Vbias Notes: Package marking provides orientation and identification = Device part number YYWW = Year and work week XXXX = Assembly lot number Vdet RFout RFout RFout Specifications 2.4GHz; Vdd = Vbias = 5.0V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Iqtotal = 500mA (typ), IEEE e 64-QAM OFDMA, ¾ FEC rate 38.5 db Gain 29.2 dbm Linear Pout (2.5% EVM) 16.1% Linear Pout 2.6V Linear Pout 23.6 db Switchable Gain Attenuation 25 A Shutdown Current Functional Block Diagram RFin Vdd1 Vdd2 Vdd3 Gain switch and bias circuitry RFout Applications High linearity amplifier for IEEE fixed terminal amplifier WLL amplifier Note: 1. Enhancement mode technology employs positive Vgs, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. Vbyp Vc1 Vc2 Vc3 Vbias Vdet

2 Absolute Maximum Rating [1] T A = Symbol Parameter Units Absolute Max. Vdd, Vbias Supply voltages, bias supply voltage V 6.0 Vc Control Voltage V (Vdd) P in,max CW RF Input Power dbm 20 P diss Total Power Dissipation [3] W 8.0 T j,max Junction Temperature C 150 T STG Storage Temperature C -65 to 150 Thermal Resistance Thermal Resistance [2] jc = 11.7 C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra- Red Measurement Technique. 3. Board temperature (T c ) is, for T c >56.4 C derate the device power at 85.5mW per C rise in board temperature adjacent to package bottom. Electrical Specifications T A =, Vdd = Vbias = 5.0V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V, Iqtotal = 500mA, RF performance at 2.4 GHz, IEEE e 64-QAM, ¾ rate FEC, 10MHz bandwidth OFDMA operation unless otherwise stated. Symbol Parameter and Test Condition Units Min. Typ. Max. Vdd Supply Voltage V 5.0 Iqtotal Quiescent Supply Current (normal high gain mode) ma 500 Quiescent Supply Current (low gain mode, Vbyp = 5.0V) ma 500 Gain Gain db OP1dB Output Power at 1dB Gain Compression dbm 35.5 Pout_5V Linear Output 2.5% EVM with 64-QAM OFDMA dbm modulation per IEEE e specs, 50% duty cycle, ¾ rate FEC Itotal_5V Total current draw at Pout_5V level ma Input Return Loss, 50 source db -10 Output Return Loss, 50 source db -11 S12 Reverse Isolation db 60 Atten Gain attenuation in low gain mode db Vdet Detector output DC 29dBm linear Pout V 2.6 DetR Detector RF dynamic range db 20 NF Noise figure db 2.1 S Stability under load VSWR of 6:1 (all phase angle), spurious output dbc -60 2

3 Product Consistency Distribution Charts [1] LSL CPK = 2.643, Std Dev = 0.18 CPK = 08, Std Dev = 38 USL Figure 1. Pout_5V; LSL = 27.7dBm, Nominal = 29.2dBm Figure 2. Itotal_5V; Nominal = 23A, USL = 1.250A LSL CPK = 1.781, Std Dev = LSL CPK = 1.493, Std Dev = USL Figure 3. Gain; LSL = 35.0dB, Nominal = 38.5dB Figure 4. Atten; LSL = 20.5dB, Nominal = 23.6dB, USL = 26.5dB; Vbyp = 5V Note: 1. Distribution data sample size is 2000 samples taken from 3 different wafer lots. T A =, Vdd = Vbias = 5V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V, RF performance at 2.4GHz unless otherwise stated. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 3

4 Unless otherwise stated, all modulated signal measurements are made with IEEE e format as stated in the notes to Figure 36. MGA typical over-temperature performance at Vdd = Vbias = 5.0V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated.,,/db Figure 5. Small-signal performance in high gain mode, Vbyp = 0V Frequency/GHz,,/dB Frequency/GHz Figure 6. Small-signal performance in low-gain mode, Vbyp = 5V EVM/% Figure 7. Over-temperature EVM vs 2.3GHz Idd total/ma Figure 8. Over-temperature Idd_total vs 2.3GHz EVM/% Figure 9. Over-temperature EVM vs 2.4GHz Idd total/ma Figure 10. Over-temperature Idd_total vs 2.4GHz 4

5 MGA typical over-temperature performance at Vdd = Vbias = 5.0V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated. EVM/% Figure 11. Over-temperature EVM vs 2.5GHz Idd total/ma Figure 12. Over-temperature Idd_total vs 2.5GHz Vdet/V Figure 13. Over-temperature Vdet vs 2.3GHz Vdet/V Figure 14. Over-temperature Vdet vs 2.4GHz Vdet/V Figure 15. Over-temperature Vdet vs 2.5GHz Noise Figure/dB Frequency/GHz Figure 16. Over-temperature Noise Figure vs Operating Frequency 5

6 MGA typical over-temperature performance at Vdd = Vbias = 5.0V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated. ETSI ETSI Frequency offset/mhz Figure 17. Over-temperature ETSI SEM at 29dBm 2.3GHz Frequency offset/mhz Figure 18. Over-temperature ETSI SEM at 29dBm 2.4GHz ETSI Frequency offset/mhz Figure 19. Over-temperature ETSI SEM at 29dBm 2.5GHz 6

7 MGA typical over-temperature performance at Vdd = Vbias = 3.3V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated.,,/db Frequency/GHz Figure 20. Small-signal performance in high gain mode, Vbyp = 0V Figure 21. Small-signal performance in low gain mode, Vbyp = 3.3V,,/dB Frequency/GHz EVM/% Figure 22. Over-temperature EVM vs 2.3GHz Total_Idd/mA Figure 23. Over-temperature Idd_total vs 2.3GHz EVM/% Figure 24. Over-temperature EVM vs 2.4GHz Total_Idd/mA Figure 25. Over-temperature Idd_total vs 2.4GHz 7

8 MGA typical over-temperature performance at Vdd = Vbias = 3.3V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated. EVM/% Figure 26. Over-temperature EVM vs 2.5GHz Total_Idd/mA Figure 27. Over-temperature Idd_total vs 2.5GHz Vdet/V Figure 28. Over-temperature Vdet vs 2.3GHz Vdet/V Figure 29. Over-temperature Vdet vs 2.4GHz Vdet/V Figure 30. Over-temperature Vdet vs 2.5GHz Noise Figure/dB Frequency/GHz Figure 31. Over-temperature Noise Figure vs Operating Frequency 8

9 MGA typical over-temperature performance at Vdd = Vbias = 3.3V, Vc = 2.1V (R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36), Vbyp = 0V unless otherwise stated. ETSI ETSI Frequency offset/mhz Figure 32. Over-temperature ETSI SEM at 26.5dBm 2.3GHz Frequency offset/mhz Figure 33. Over-temperature ETSI SEM at 26.5dBm 2.4GHz ETSI Frequency offset/mhz Figure 34. Over-temperature ETSI SEM at 26.5dBm 2.5GHz 9

10 S-Parameter [1] (Vdd = Vbias = 5.0V, Vc = 2.1V [2], Vbyp = 0V, T =, unmatched) Freq (GHz) S12 S12 10

11 Freq (GHz) S12 Notes: 1. S-parameter is measured with deembedded reference plane at DUT RFin and RFout pins. 2. R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36. S12 11

12 S-Parameter [1] (Vdd = Vbias = 3.3V, Vc = 2.1V [2], Vbyp = 0V, T =, unmatched) Freq (GHz) S12 S12 12

13 Freq (GHz) S12 Notes: 1. S-parameter is measured with deembedded reference plane at DUT RFin and RFout pins. 2. R2 = 1.2k, R3 = 300, R4 = 1.2k as shown in Figure 36. S12 13

14 Demonstration Board Top View MGA (B) VDD1 Vdd1 +5V C9 C5 C10 C4 L1 C11 C8 C12 RFIN C25 RFOUT C26 C27a MGA VBYP VDD1S C13 C14 VC1 C2 C1 C15 C16 Vbyp 0V (normal gain) +5V (low gain) VDD2 C3 R3 R2 C7 VC2 Vdd2 +5V C17 C18 VDD2S C19 C20 VC3 Vc +2.1V R4 VDD3 R1 C21 C22 VBIAS Vdd3 +5V C27b VDD3S C24 C23 VDET Vbias Vdet +5V (Output) RO4350 DK 3.48 H 10mil W 0.57mm G 0.59mm DEC'09 C28 Bill of materials Component Value Part # C9 22uF GRM31CR61C226ME15 C1, C5, 0.1uF GRM155R71C104KA88 C11, C22 C7, C13, 7.5pF GJM1555C1H7R5DB01 C25, C28 C4 8.2pF GJM1555C1H8R2DB01 C8 2.4pF GJM1555C1H2R4CB01 C12 2.2pF GJM1555C1H2R2CB01 C26 0.4pF GJM1555C1HR40BB01 C27a 1.8pF GJM1555C1H1R8CB01 C27b pf GJM1555C1H2R0CB01 C23 22nF GRM155R71E223KA61 L1 nh 0402HP-1N0XJLW R1 0 RK73Z1ETTD R RK73B1ETTD122J R3 300 RK73B1ETTD301J R RK73B1ETTD122J Note: For performance optimization, control voltage for individual stages can be adjusted by varying R2, R3 and R4 resistor values. Pins pointing out of the page (Unit is on top) MGA (B) Figure 35. Demonstration board application circuit for MGA module Vdd1 +5V VDD1 VDD1S VDD2 VDD2S VDD3 VDD3S C9 C5 C10 C4 L1 C11 C8 C12 RFIN C25 RFOUT C26 C27a MGA VBYP C13 C14 VC1 C15 C16 R2 C7 C3 C2 C1 Vdd2 +5V VC2 C17 C18 R3 C19 C20 VC3 Vbyp Vc 0V (normal gain) +2.1V +5V (low gain) R4 R1 Vdd3 +5V C21 C22 C27b C24 C23 VBIAS VDET Vbias Vdet +5V (Output) RO4350 DK 3.48 H 10mil W 0.57mm G 0.59mm DEC'09 C28 Application board pin header assignments Pin 1 : Vdd3 (Sense) Pin 2 : Vdd3 (Force) Pin 3 : Vdd2 (Sense) Pin 4 : Vdd2 (Force) Pin 5 : Vdd1 (Sense) Pin 6 : Vdd1 (Force) Pin 13 : Vbyp Pin 14 : Vc1 (Not used) Pin 15 : Vc2 Pin 16 : Vc3 (Not used) Pin 17 : Vbias Pin 18 : Vdet Other pins are grounded 14

15 Application Schematic Figure 36. Application schematic in demonstration board Notes: 1. In normal gain mode operation, Vbyp = 0V. Vc1, Vc2 and Vc3 are bias pins that are used to set the bias conditions to the 3 internal gain stages of the PA. 2. Typical quiescent current distribution with Vdd1 = Vdd2 = Vdd3 = Vbias = 5V, Vbyp = 0V, Vc = 2.1V is : a. Idd1 = 50 ma b. Idd2 = 180 ma c. Idd3 = 270 ma d. Ibias = 16.5mA (Note: Vc supplied through Vc2 pin on demonstration board with R2 = 1.2k, R3 = 300 and R4 = 1.2k ) 3. Low gain mode is enabled by setting Vbyp pin to 5V. This condition overrides the normal high gain mode operation and bypasses the first gain stage, regardless of the voltage at Vc1 pin. 4. Modulated signal measurements are made with Agilent VSA and Agilent E4438C signal generator with IEEE e option using the following test conditions : Signal format: IEEE e OFDMA, ¾ rate FEC Modulation: 64-QAM Number of Subcarriers: 840 Modulation bandwidth: 10 MHz Downlink ratio: 50% Residual distortion of signal generator: ( )%. This distortion is not removed from the overall EVM data in the datasheet. 5. Typical operating voltages and currents: a. Normal gain mode: Vdd1 = Vdd2 = Vdd3 = Vbias = 5V. Vc = 2.1V. Vbyp = 0V. Iq(total) = 500 ma. b. Low gain mode: Vdd1 = Vdd2 = Vdd3 = Vbias = 5V. Vc = 2.1V. Vbyp = 5V. Iq(total) = 500 ma. 6. Vdd1/2/3 are shown as separate supplies with individual bypass capacitors. This yields the most stable configuration. If a common power supply line is used, proper broadband bypass decoupling is recommended to reduce common mode feedback through the supply line. 15

16 PCB Land Pattern and Stencil Outline ø C'fer X PCB Land Pattern (Top View) Stencil Outline C'fer X (All dimensions in mm) Combined PCB Land Pattern and Stencil Outline 16

17 QFN 5.0 x 5.0 x 0.85mm 3 28-Lead Package Dimensions Pin ± Ref 5.00± YYWW XXXX ±5 Top View Side View 3.60±50 Exp.DAP PIN #1 IDENTIFICATION CHAMFER X ± Bsc 3.60±50 Exp.DAP 0.25±50 0 Ref. Bottom View Note : 1. All dimensions are in milimeters 2. Dimensions are inclusive of plating 3. Dimensions are exclusive of mold flash and metal burr. Part Number Ordering Information Part # Qty Container MGA BLKG 100 Antistatic Bag MGA TR1G Reel 17

18 Device Orientation REEL USER FEED DIRECTION CARRIER TAPE YYWW XXXX YYWW XXXX YYWW XXXX USER FEED DIRECTION COVER TAPE TOP VIEW END VIEW Tape Dimensions 18

19 Reel Dimensions (7 reel) Ø178.0± FRONT BACK SEE DETAIL "X" RECYCLE LOGO FRONT VIEW R * +1.5* R5.2 Slot hole b FRONT BACK 60 Ø55.0±0.5 Ø178.0± EMBOSSED RIBS RAISED: 0.25mm, WIDTH: 1.25mm BACK VIEW Ø51.2±0.3 Slot hole a 14.4* MAX. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV EN - September 29, 2011