Data Sheet. AMMC GHz 0.2 W Driver Amplifier. Features. Description. Applications

Transcription

1 AMMC GHz.2 W Driver Amplifier Data Sheet Chip Size: x 13 m (1 x 51 mils) Chip Size Tolerance: ± 1 m (±.4 mils) Chip Thickness: 1 ± 1 m (4 ±.4 mils) Pad Dimensions: 1 x 1 m (4 x 4 ±.4 mils) Description The AMMC-6333 is a broadband.2 W MMIC driver amplifier designed for use in transmitters operating in various frequency bands from 18 GHz to 33 GHz. This small, easy to use device provides over 23 dbm of output power (P -1dB ) and more than 2 db of gain at GHz. It was optimized for linear operation with an output power at the third order intercept point (OIP3) of 3dBm. The AMMC-6333 features a temperature compensated RF power detection circuit that enables power detection sensitivity of.3 V/W at GHz. It is fabricated using Avago Technologies unique. m E-mode PHEMT technology which eliminates the need for negative gate biasing voltage. Features Frequency range: 18 to 33 GHz Small signal gain: 2 db P -1dB : 23dBm Return Loss (In/Out): -1 db Applications Microwave Radio systems Satellite VSAT, Up/Down Link LMDS & Pt-Pt mmw Long Haul Broadband Wireless Access (including and 82.2 WiMax) WLL and MMDS loops Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) = 9 V ESD Human Body Model (Class 1A) = 3 V Refer to Avago Application Note A4R: Electrostatic Discharge, Damage and Control.

2 Absolute Maximum Ratings Symbols Parameters Unist Maximum Notes Vd-Vg Drain to Gate Voltage V 14 Vd Positive Supply Voltage V 5.5 Vg Gate Supply Voltage V to 5 Id Drain Current ma TBD 2 PD Power Dissipation W and 3 Pin CW Input Power dbm 2 2 Tch Operating Channel Temp C + 4 Tstg Storage Case Temp. C -65 to +5 Tmax Maximum Assembly Temp (3 sec max) C +32 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. Functional operation at or near these limitations will significantly reduce the lifetime of the device. 2. Dissipated power PD is in any combination of DC voltage, Drain Current, input power and power delivered to the load. 3. When operated at maximum PD with a base plate temperature of 85 C, the median time to failure (MTTF) is significantly reduced. 4. These ratings apply to each individual FET. The operating channel temperature will directly affect the device MTTF. For maximum life, it is recommended that junction temperatures (Tj) be maintained at the lowest possible levels. See MTTF vs. Tchannel Temperature Table. DC Specifications/ Physical Properties Symbols Parameters and Test Conditions Units Values I d Drain Supply Current ma 23 (V d =5 V, V g set for typical I dq quiescent current) V g Gate Supply Operating Voltage V 2 (I dq = 23 ma) I g Gate Supply Current ma 7 R jc Thermal Resistance C/W 26 (Channel-to-Backside) Tch Channel Temperature C 1 Thermal Properties Parameter Test Conditions Value Maximum Power Dissipation Tbaseplate = 85 C PD = 2.5W Tchannel = C Thermal Resistance ( jc) Vd = 5V Id = 23mA PD = 1.W Tbaseplate = 85 C jc = 26 C/W Tchannel = 1 C Thermal Resistance ( jc) Under RF Drive Vd = 5V Id = 43mA Pout = 24dBm Pd = 1.89W Tbaseplate = 85 C jc = 26 C/W Tchannel = 134 C 2

3 MTTF vs. Tchannel Temperature Operation 6% Confidence Level 9% Confidence Level Point Data R= Tj λ (ФIT) MTTF (hrs) λ (ФIT) MTTF (hrs) λ (ФIT) MTTF (Yrs) E E E E E E E E E E E E E E E E E+7 6.5E E E E E E E E E+9 3.8E E+1 7.6E+9 1.7E E+1 3.8E+1 8.8E+1 RF Specifications T A = C, V d =5, I d(q)= 23 ma, Z o = GHz 2 3 GHz 3 33 GHz Symbols Parameters Units Min Typ Max Min Typ Max Min Typ Max G Small signal Gain db P -1dB Output Power at dbm dB Gain Compression P -3dB Output Power at dbm dB Gain Compression OIP3 Third Order Intercept dbm RL in Input Return Loss db RL out Output Return Loss db Reverse Isolation db Note: 1. Measurements done on amplifier die attached to a metal carrier at T A = C. 2. 1% on-wafer RF test is done at frequency=17, 26 and 33GHz. Statistic based on part sample. 3

4 Product Consistency Distribution Charts Typical distribution of Small Signal Gain and Output Based on parts sampled over several production lots Gain at 17GHz Gain at 26GHz Gain at 33GHz P1dB at 17GHz P1dB at 26GHz P1dB at 33GHz 4

5 Typical Performance (T A = C, V d =5 V, I dq = 23 ma, Z in = Z out = 5 ) (Data obtained from a test fixture with 3.5 mm connectors. Effects of the test fixture losses and mismatch have not been removed from the data) S21[dB] Figure 1. Gain and Reverse Isolation vs Frequency S21[dB] S12[dB] S12 [db] Return Loss [db] Figure 2. Return Loss vs Frequency S11[dB] S22[dB] P-1 [dbm], PAE [%] P-1 PAE Figure 3. P-1dB and PAE vs Frequency IMD3 Level [dbc] SCL=2[dBm] SCL=1dBm] SCL=5[dBm] Figure 4. Typical IMD3 vs Frequency (SCL = Single Carrier level) Noise Figure [db] Po [dbm], PAE [%] Pout(dBm) PAE[%] Ids[mA] Ids [ma] Figure 5. Typical Noise Figure vs Frequency Pin [dbm] 2 Figure 6. Output Power, PAE, and Drain Current vs Input Power at 3GHz 5

6 Typical Performance (continued) (T A = C, Z in = Z out = 5 ) (Data obtained from a test fixture with 3.5 mm connectors. Effects of the test fixture losses and mismatch have not been removed from the data) P-1[dBm P-1[Vds=3V] P-1[Vds=4V] P-1[Vds=5V] Figure 7. P -1dB vs Frequency and Vds, (I dq =23mA) Gain [db] Gain [@18mA] Gain[@mA] Gain[@23mA] Gain[@27mA] Figure 8. Small signal gain vs Frequency and I dq, (Vds=5V) Gain [db] Gain[Vds=3V] Gain[Vds=4V] Gain[Vds=5V] Figure 9. Small signal gain vs Frequency and Vds, (IdQ=23mA) P1 [dbm] P-1[@18mA] P-1[@mA] 17 P-1[@23mA] P-1[@27mA] Figure 1. P -1dB vs Frequency and I dq, (Vds=5V) 2 1 Ids=23mA Ids=29mA -1 Ids=23mA Ids=29mA IMD3 Level [dbc] IMD3 Level [dbc] Figure 11. IMD3 levels vs Frequency Fundamental output carriers at +2 dbm each Figure 12. IMD3 levels vs Frequency Fundamental output carriers at +1dBm each 6

7 Typical Performance (continued) (V d =5 V, I dq = 23 ma, Z in = Z out = 5 ) (Data obtained from a test fixture with 3.5 mm connectors. Effects of the test fixture losses and mismatch have not been removed from the data) S11[dB] S11_ S11_-4 S11_85 S22[dB] S22_ S22_-4 S22_ Figure 13. S11 vs Frequency and Temperature Figure 14. S22 vs Frequency and Temperature S21[dB] S21_ S21_-4 S21_ Figure. S21 vs Frequency and Temperature P-1 [dbm] P-1_85deg P-1_deg P-1_-4deg Figure 16. P -1dB vs frequency and Temperature 7

8 Typical Scattering Parameters (T A = C, V d =5 V, I dq = 23 ma, Z in = Z out = 5 ) Data obtained from on-wafer measurements Freq S11 S21 S12 S22 [GHz] db Mag Phase db Mag Phase db Mag Phase db Mag Phase E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E

9 Biasing Considerations The AMMC-6333 is a balanced amplifier consisting of two four stage single-ended amplifiers, two Lange couplers, a power monitoring detector, a reference detector for temperature compensation, and a current mirror for the gate biasing (Figure 17). The recommended quiescent DC bias conditions for optimum gain, output power, efficiency, and reliability are: Vd = 5 V with Vg set for I dq = 23 ma. The drain bias voltage range is from 3 to 5 V. Drain current range is from 2 ma to 35 ma. The AMMC-6333 can be biased with a dual or single positive DC source (Figure 18). The output power detection network provides a way to monitor output power. The differential voltage between the DET_R and DET_O outputs can be correlated with the RF power emerging from the RF output port. This voltage is given by: V = (V DET_R V DET_O ) V OFS Where: V DET_R is the voltage at the DET_R port V DET_O is a voltage at the DET_O port V OFS is the offset voltage at zero input power The offset voltage (V OFS) can be at each power level by turning off the input power and measuring V. The error due to temperature drift should be less than.1db/5 C. When V OFS is determined at a single reference temperature the drift error should be less than.db. Finally, V OFS be characterized over a range of temperatures and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate V OFS at any temperature. The RF ports are AC coupled at the RF input to the first stage and the RF output of the final stage. No ground wires are needed since ground connections are made with plated through-holes to the backside of the device. V g V d DET_O RF out RF in Four stage wideband amplifier V d DET_R Figure 17. AMMC-6333 schematic 9

10 Vg Vd.1 uf.1 uf >68 pf >68 pf DET_ RF_in RF_out >68 pf.1 uf 1. Dual positive DC power supply Vd DET_R Notes: 1. 1 uf capacitors not shown on gate and drain lines are required 2. Vd connection is required on both sides Vd >68 pf 4.1 uf >68 pf DET_ RF_in RF_out >68 pf.1 uf 2. Single positive DC power supply Vd DET_R Notes: 1. 1 uf capacitors not shown on gate and drain lines are required 2. Vd connection is required on both sides Figure 18. AMMC-6333 biasing circuits 1

11 Assembly Techniques The chip should be attached directly to the ground plane using electrically conductive epoxy (Note 1). For conductive epoxy, the amount should be just enough to provide a thin fillet around the bottom perimeter of the die. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. Thermo-sonic wedge bonding is the preferred method for wire attachment to the bond pads. The RF connections should be kept as short as possible to minimize inductance. Double-bonding with.7mil gold wire is recommended. The recommended wire bonding stage temperature is ±2 C. The chip is 1μm thick and should be handled with care. This chip has exposed air bridges on the top surface. Handle at the edges or with a custom collet, (do not pick up die with vacuum on die center). This MMIC is static sensitive and ESD handling precautions should be taken GND VG VD DET_O RF_IN RF_OUT GND VD DET_R Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. Figure 19. Die dimensions Ordering Information: AMMC-6333-W1 = 1 devices per tray AMMC-6333-W5 = 5 devices per tray For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright -29 Avago Technologies. All rights reserved. AV2-1446EN - November 12, 29