AMMC KHz 40 GHz Traveling Wave Amplifier

Transcription

1 AMMC- 3 KHz GHz Traveling Wave Amplifier Data Sheet Chip Size: Chip Size Tolerance: Chip Thickness: Pad Dimensions: 3 x µm (9. x 1.3 mils) ± µm (±. mils) ± µm ( ±. mils) 8 x 8 µm (.9 ±. mils) Description Avago Technologies' AMMC- is a broadband PHEMT GaAs MMIC TWA designed for medium output power and high gain over the full 3 KHz to GHz frequency range. The design employs a 9-stage,cascade-connected FET structure to ensure flat gain and power as well as uniform group delay. E-beam lithography is used to produce uniform gate lengths of. mm and MBE technology assures precise semiconductor layer control. For improved reliability and moisture protection, the die is passivated at the active areas. Features Wide frequency range: 3 KHz GHz High gain: 1 db Gain flatness: ±.7 db Return loss: Input: 13 db, Output: 13 db Medium power: P-1dB =. dbm at GHz Low noise figure:. db at GHz Applications Communication systems Microwave instrumentation Optical systems Broadband applications requiring flat gain and group delay with excellent input and output port matches over the 3 KHz and GHz frequency range Absolute Maximum Ratings [1] Symbol Parameters/Conditions Units Min. Max. V dd Positive Drain Voltage V I dd Total Drain Current ma 3 V g1 First Gate Voltage V -9. I g1 First Gate Current ma V g Second Gate Voltage V I g Second Gate Current ma - P in CW Input Power dbm 17 T ch Operating Channel Temperature C + T b Operating Backside Temperature C - T stg Storage Temperature C - + T max Max. Assembly Temp ( sec max) C +3 Notes: 1. Absolute maximum ratings for continuous operation unless otherwise noted.

2 AMMC- DC Specifications/Physical Properties [1] Symbol Parameters and Test Conditions Units Min. Typ. Max. I dss Saturated Drain Current (V dd =7 V, V g1 = V, V g =open circuit) ma 3 38 V p First Gate Pinch-off Voltage (V dd =7 V, I dd =3 ma, V g =open circuit) V -8. V g Second Gate Self-bias Voltage (V dd =7 V, I dd = ma, V g =open circuit) V.7 I dsmin First Gate Minimum Drain Current ma 7 (V g1 ) (V dd =7 V, V g1 =-7 V, V g =open circuit) I dsmin Second Gate Minimum Drain Current ma (V g ) (V dd =7 V, V g1 = V, V g = -3. V) θ ch-b Thermal Resistance [] (Backside temperature, T b = C) C/W 1. RF Specifications for High Power Applications [, 3] (V dd =7 V, I dd (Q)= ma, Z in = Z o =Ω Symbol Parameters and Test Conditions Units Min. Typ. Max. S 1 Small-signal Gain db S 1 Small-signal Gain Flatness db ±.7 ± RL in Input Return Loss db RL out Output Return Loss db 1.8 S 1 Isolation db 8 P -1dB Output 1 db Gain Compression f = GHz dbm 1. P sat Saturated Output Power f = GHz dbm 3. OIP3 Output 3 rd Order Intercept Point, dbm 7 3 Rf in1 = Rf in = dbm, f = GHz, f = MHz NF Noise Figure (V ds = 3V, I ds = 1 ma) f = GHz db.. f = GHz db 7. 9 RF Specifications for High Gain and Low Power Applications [, 3] (V dd = V, I dd (Q)= 1 ma, Z in = Z o =Ω) Symbol Parameters and Test Conditions Units Min. Typ. Max. S 1 Small-signal Gain db 17. S 1 Small-signal Gain Flatness db ±1. RL in Minimum Input Return Loss db 13 RL out Minimum Output Return Loss db 13 S 1 Isolation db 3 P -1dB Output 1 db Gain Compression f = GHz dbm 17.3 P sat Saturated Output Power f = GHz dbm. OIP3 Output 3 rd Order Intercept Point, dbm. Rf in1 = Rf in = dbm, f = GHz, f = MHz NF Noise Figure f = GHz db 3.7 f = GHz db. Notes: 1. Backside temperature T b = C unless otherwise noted.. Channel to board Thermal Resistance is measured using QFI method. 3. % on-wafer RF test is done at frequency =,,, 3 and GHz, except as noted.

3 AMMC- Typical Performance (T chuck = C, V dd = 7 V, I dd = ma, V g = Open, Z = Ω) S1 (db) S1(dB) S1(dB) Figure 1. Gain and Reverse Isolation S1 (db) RETURN LOSS (db) S11(dB) S(dB) Figure. Return Loss (Input and Output). P-1, P-3 (dbm) 3 3 Figure 3. Output Power (P-1 and P-3). P-1 P-3.1 td (ns) NOISE FIGURE (db) 8 OIP3 (dbm) 3 3 Figure. Group Delay. 3 Figure. Noise Figure. 3 Figure. Output IP3. 3

4 AMMC- Typical Scattering Parameters [1] (T chuck = C, V DD = 7V, I DD = ma, Z in = Z out = Ω) Freq. S 11 S 1 S 1 S GHz db Mag Phase db Mag Phase db Mag Phase db Mag Phase Note: 1. Data obtained from on-wafer measurements.

5 AMMC- Typical Performance (T chuck = C, V dd = V, I dd = 1 ma, V g = Open, Z = Ω) 3 S1 (db) S1(dB) S1(dB) -8 Figure 7. Gain and Reverse Isolation S1 (db) RETURN LOSS (db) S11(dB) S(dB) Figure 8. Return Loss (Input and Output). P-1, P-3 (dbm) 3 P-1 P-3 Figure 9. Output Power (P-1 and P-3)..1 3 td (ns) NOISE FIGURE (db) 8 OIP3 (dbm) 3 Figure. Group Delay. 3 Figure 11. Noise Figure. 3 Figure 1. Output IP3.

6 AMMC- Typical Scattering Parameters [1] (T chuck = C, V DD = V, I DD = 1 ma, Z in = Z out = Ω) Freq. S 11 S 1 S 1 S GHz db Mag Phase db Mag Phase db Mag Phase db Mag Phase Note: 1. Data obtained from on-wafer measurements.

7 AMMC- Typical Performance (Over Temperature and Voltage) 3 GAIN (db) 7V/mA V/187mA V/17mA V/1mA 3V/17mA 3 Figure 13. Gain and Voltage. P-1 (dbm) 7V/mA V/187mA V/17mA V/1mA 3V/17mA 3 Figure 1. P-1 and Voltage. S1, S11, and S (db) S11/8 C S/- C S1/ C S/8 C S/- C 3 S11/ C S1/8 C S/- C S/ C Figure. Gain and Return Loss with Temperature. P-1 (dbm) 3 P-1/8 C P-1/ C P-1/- C P-1 (dbm) NF/- C NF/ C NF/8 C NOISE FIGURE (db) 8 7V/ ma V/187 ma V/17 ma V/1 ma 3V/17 ma 3 Figure 1. P-1 and Temperature, V dd =7V, I dd = ma. 3 Figure 17. Noise Figure and Temperature at V dd =V, I dd =1 ma. 3 Figure 18. Noise Figure and Voltage. 7

8 Biasing and Operation AMMC- is biased with a single positive drain supply (V dd ) a negative gate supply (V g1 ). For best overall performance the recommended bias is V dd =7V and I dd = ma. To achieve this drain current level, V g1 is typically between. to 3.V. Typically, DC current flow for V g1 is ma. The AMMC- has a second gate bias (Vg) that may be used for gain control. When not being utilized, Vg should be left open-circuited. This feature further enhances the versatility of applications where variable gain over a broad bandwidth is necessary. This second gate bias (Vg) is connected to the gates of the upper FETs in each cascode stage through a small de-queing resistor. The other end of the gate line is terminated in an on-chip resistive/diode divider network, which allows the second gate to self-bias. Thus, with Vg left open-circuited, the drain current is set by the (Vg1) gate bias voltage applied to the lower FET in each stage. The nominal open circuit voltage for Vg is approximately volts. Under this operating condition, maximum gain and power are achieved from the TWA. By applying an external voltage to the second gate bias (Vg) less than the open-circuit potential, the drain voltage on the lower FET can be decreased to a point where the lower FET enters the linear operating region. This reduces the current drawn by each stage. Decreasing Vg further will reduce the drain voltage on the lower FET towards zero while pinching off the upper FET in each stage. At larger negative values of Vg (between and -. volts) the gain of the TWA will decrease significantly. Using the simplest form of assembly (Figure ), the device is capable of delivering flat gain over a GHz range with a minimum of gain slope and ripple. However, this device is designed with DC coupled RF I/O ports, and operation may be extended to lower frequencies (< GHz) through the use of off-chip low-frequency extension circuitry and proper external biasing components. With low frequency bias extension it may be used in a variety of time-domain applications (through Gb/s). Figure 1 shows a typical assembly configuration. When bypass capacitors are connected to the AUX pads, the low frequency limit is extended down to the corner frequency determined by the bypass capacitor and the combination of the on-chip ohm load and small dequeing resistor. At this frequency the small signal gain will increase in magnitude and stay at this elevated level down to the point where the C aux bypass capacitor acts as an open circuit, effectively rolling off the gain completely. The low frequency limit can be approximated from the following equation: f Caux = where: 1 πc aux (Ro + R DEQ ) R o is the Ω gate or drain line termination resistor. R DEQ is the small series de-queing resistor and Ω. C aux is the capacitance of the bypass capacitor connected to the AUX Drain pad in farads. With the external bypass capacitors connected to the AUX gate and AUX drain pads, gain will show a slight increase between 1. and 1. GHz. This is due to a series combination of C aux and the on chip resistance but is exaggerated by the parasitic inductance (L c ) of the bypass capacitor and the inductance of the bond wire (L d ). Therefore the bond wire from the Aux pads to the bypass capacitors should be made as short as possible. Input and output RF ports are DC coupled; therefore, DC decoupling capacitors are required if there are DC paths. (Do not attempt to apply bias to these pads.) RF bond connections should be kept as short as possible to reduce RF lead inductance which will degrade performance above GHz. An optional output power detector network is also provided. A >. µf capacitor is required for the Det_Out pad to expand power detection performance below MHz. Ground connections are made with plated through-holes to the backside of the device; therefore, ground wires are not needed. 8

9 Assembly Techniques The backside of the MMIC chip is RF ground. For microstrip applications the chip should be attached directly to the ground plane (e.g. circuit carrier or heatsink) using electrically conductive epoxy [1,]. For best performance, the topside of the MMIC should be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a gold plated metal shim (same length as the MMIC) under the chip which is of correct thickness to make the chip and adjacent circuit the same height. The amount of epoxy used for the chip or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is normally sufficient for single connections, however double bonding with.7mil gold wire will reduce series inductance. Gold thermo-sonic wedge bonding is the preferred method for wire attachment to the bond pads. The recommended wire bond stage temperature is c ± c. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is um thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up the die with a vacuum on die center). Bonding pads and chip backside metallization are gold. This MMIC is also static sensitive and ESD precautions should be taken. Eutectic attach is not recommended and may jeopardize reliability of the device. For more detailed information see Avago Technologies Application Note #39 GaAs MMIC assembly and handling guidelines. Notes: 1. Ablebond 8-1 LMl silver epoxy is recommended. Eutectic attach is not recommended and may jeopardize reliability of the device GND DET_OUT Drain Bias (Vdd) Vdd AUX Nine Identical RF_Output DET_BIAS Second Gate First Gate Bias (Vg1) RF_Input DET_REF Figure 19. AMMC- Schematic. 9

10 DET_Reference Vdd_AUX Vdd DET_Bias DET_Output GND 9 Vg 8 RF INPUT 3 Figure. AMMC- Bonding Pad Locations. (dimensions in micrometers) V g RF Output GND Drain bias must be decoupled from RF to lowest operating frequency pf Capacitor nh Inductor for operation to GHz bond wire V DD IN V G1 OUT Gate is decoupled from RF. (Bond wire length is not important) Figure 1. AMMC- Assembly Diagram. Ordering Information AMMC--W = devices per tray AMMC--W = devices per tray For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright -8 Avago Technologies. All rights reserved. Obsoletes EN AV-3EN - September 8, 8

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