EL7302. Hardware Design Guide

Transcription

1 Hardware Design Guide Version: Preliminary 0.0 Date: January Approval: Etron technology, Inc P.O. Box No.6 Technology Road V. Science-based Industrial Park, Hsinchu,30077 Taiwan, R.O.C. Tel: Fax:

2 Copyright 2005 Etron Technology Inc. All Rights Reserved This document may be modified or revised subject to the discretion of Etron Technology Inc. without further notice. Etron Technology Inc. makes no warranty or representation to either the contents of this document or the products referenced in this document for any errors or omissions. 2

3 Table of Content 1. Introduction Board Features Analog I/P Digital I/P & Video Port.4 5 Scalar MPU Power:.5 8. Panel I/F ( TLL) Layout Guide

4 1. Introduction Etron s as the demand for low-cost LCD monitor escalates, simplified and cost-effective design already dominates the LCD controller application. With its highly integrated high- performance ADCs, PLLs and high-quality scalar, the has been developed to address the low-cost and high-quality XGA/ SXGA TTL interfacing LCD monitor market. This simple design supports analog and digital input with resolutions range from 640*480 to 1280*1024, and supports progressive video functions too. 2. Board Features The reference design comprises the following major blocks: i. Analog VGA I/P - Fully compatible with VESA VGA standard up to SXGA mode. - Support sync on green signal ii. Digital I/P & Video Port - Digital port supports RGB-888 format - Video port supports progressive video stream in CCIR601 and CCIR656 format. iii. Scalar - All-in-One scalar - One 24-bit data port for digital I/P, and/ or progressive video data. - Two PWMs provide flexibility of system design. - Only a 25-MHz crystal is required for external clock reference. iv. MPU - 51 based general purpose MPU. - Serial EEPROM for system and user information storage - 2 -

5 v. Power - Switching-mode regulators convert 12V into 5V. - LDO voltage regulators provide 2.5Vs for scalar s core, ADC and PLLs. 3.3V supply is used to drive all port pins - PWM for backlight brightness control. vi. Panel (TTL) I/F - TTL panel I/F supports 6/8-bit panels. - Single/dual-pixel digital RGB output. 3. Analog VGA I/P For analog VGA input, the analog R/G/B signals are input into the scalar directly. Simple L-C circuits are configured as low-pass filters to reduce high-frequency noise. Ferrite-beads are better alternatives because of their high-frequency electrical characteristics. In addition to noise reduction, impedance matching is another major concern for R/G/B signals. For high-speed signals, reflection will occur without impedance matching. The impedance of R/G/B signals are exactly defined as 75Ω to use as terminators for impedance matching. For perfect impedance matching, using 1% precision of resistors is highly recommended. If the impedance of R/G/B trace on the PCB has been carefully controlled, the best termination point will be at the input of AC-coupling capacitors. The inverter, 74LVC14, provides single-ttl-loading for both Hsync and Vsync signals. The schimitt-triggered input of 74LVC14 will as well reshape the deteriorated edge of Hsync signal. This result might help jitter performance of s PLLs. The 3.3V-operated 74LVC14 is chosen to be signal level compatible with. High-speed diode arrays, DA1, 2, are added to all VGA signals to provide ESD protection

6 4.Digital I/P & Video port Digital I/P support RGB888 format for TTL interface panel only. For video functions, the supports both interlaced and progressive video data stream from video processor in CCIR601 and CCIR656 format. Digital ports are designed to tolerant 5 Voltage that can compliance with TTL logics 5. Scalar The application design of is relatively simple since it already integrates ADCs, PLLs, OSD engine, with a few external components added to support its functions. The closer external components placed to, the lesser noise coupling and interference. For analog R/G/B input, the receives AC-coupled signals in the RED_I, GRN_I and BLU_I pins. Also receives the Hsync and Vsync signals in the A_HS and A_VS pins.0.1 µf AC-coupling capacitors are to block the DC voltage (offset) of analog RGB signals coming directly from VGA cable. DC restoration is required after the signal has been AC-coupled. The clamping circuitry implemented in will clamp the AC-coupled RGB signals black-level to a known zero level. The clamping position and duration are fully programmable. Resistors are configured as voltage dividers for s FILT and V_REF inputs. Capacitors are used to bypass the noise. Resistor of 1% precision is highly recommended. For digital input, the receives 24-bit digital data via the RIN0~7, GIN0~7 and BIN0~7 pins. The driving source has to provide DCLK, D_HS, D_VS and DE signals too. The needs only one 25-MHz crystal with a frequency tolerance of ±100 ppm for its external clock reference to gain maximum PLL performance. This clock reference may be a crystal oscillator. Load Capacitance with other values are required depending on crystal s characteristic. The accuracy and stability of this crystal significantly influences the jitter performance of the scalar. The signal condition of Hsync affects jitter performance as well. So, the trace of Hsync signal better be short and ground shielded. All the output signals of, especially signals that drive the cable, are equipped with serial resistors to damp driving current. Those damping resistors increase the slew-rate of signals, and reduce EMI. Ferrite-beads are better alternatives for those damping resistors. With on-chip programmable slew-rate and driving-strength control allows system/ EMI engineers handle the EMC issue easily. Power supply of is categorized into - 4 -

7 four groups: 3.3V for I/O, 2.5Vs for Core ADCs and PLLs. To avoid interference on the power supply lines and improve the analog performance (e.g. ADCs, PLLs ) of the, it is recommended to divide up the power supply into different sections, which are separated from each other by LC-filters. In addition to components placement and signals routing, care must also be taken for the round plane and signals. Properly isolated ADC and PLL analog grounds will return you low-noise and low-jitter. The s performance and reliability can be easily achieved when the general high-speed/ EMC design rules has been followed properly. 6.MPU General 51-based MPUs are sufficient for s application. 8-bit parallel Address/Data bus issued to interface with scalar then is able to provide the bandwidth required for register programming. For MPU, displaying OSD menu is considered a heavy task due to high bandwidth demand. MPU operated at 24 MHz can handle the heavy task. The speed and accuracy of auto adjustment also play a great part of system performance. With optimized F/W and ingeniously designed H/W, the hit-rate can be easy achieved as high as 87% in just as low as 3 seconds, under all conditions. The 24C16 is serial EEPROM for storing system and user information. 2N3904 transistors are configured as on/ off switches for LED indicators to comply with VESA DPMS standard. An optional 4-pin header is provided for system H/W and F/W debugging by RS-232. With proprietary software utility, all registers of can be run-time accessed for debugging. This will significantly reduce the H/W and F/W developing schedule. I2C bus protocol is emulated by firmware using MPU s I/O ports to communicate with EEPROM and Video Processor. 7. POWER PWM controllers configured as switching-mode regulators can convert 12V supply into 5V for MPU, scalar, peripherals and panel. Switching-mode regulators have advantages of high efficiency of power conversion, energy-saving, but may not be free of ripple noise. The inductors and capacitors are for the purpose of energy storage. Values and electrical characteristics of these components have to be carefully selected for sufficient supply current and conversion efficiency. It also configured as L-C filters for reducing ripple noise. LDO regulators are used to convert 5V into 3.3V and 2.5V for I/O pads, ADCs & PLLs and Core power. Independent 2.5V supply is recommended for minimizing noise interference. 5-pin - 5 -

8 header is used to connect inverter. The backlight on/ off control signal is inverted intentionally to prevent screen from disturbing flashing during reset period. The brightness control signal is driven by on-chip programmable PWM circuitry. Two-order RC lowpass filter integrates the PWM charge and convert it into voltage level, which define the brightness of the backlight. 8.Panel (TTL) I/F can support some types of panels including 6/8-bit, single/dual port TTL interface panel. Every signal that runs out of the board has to be bypassed with capacitors. The closer these bypass capacitors placed to the output connectors, the better results in reducing the EMI. Any high-speed signals and power planes should avoid running under this area. The ground plane under this area has to be properly isolated to avoid noise coupling. MOSFET is used to gate the power of panel interface. The gate is open only when needs to display image or OSD message. For different power voltage of panel, jump selector is chosen for proper power voltage. 2N3904 transistor is recommended to level shift the TTL to 12V for the gate control (Vgs) of power MOSFET

9 9. Layout Guide Decoupling: 1. Decoupling CAPs are to supply the logic device current necessary during a state of transition. 2. Add 0.1uF decoupling-cap to every VDD and GND pairs. 3. Minimize the trace (lead) length from VDD/GND pins to decoupling CAPs and to the vias to reduce power supply inductance, and reduce ground-bounce. 4. Make sure that your power supply (VDD) trace goes through decoupling CAP before into the VDD pins. 5. Add a 10uF electrolyte (bulk) CAP for 2~4 devices (to provide decoupling CAPs charge). 6. Depend on their power consumption. Different dielectric type of CAP has significantly different characteristics. Be ware of what types of CAPs you are using. 7. Parallel CAPs may cause resonance at certain frequency, since your CAP is not an ideal capacitor. GND/VDD Planes and Grounding: 1. Use 4-layer PCB to provide better VDD and GND distribution, good decoupling, low noise and low EMI. 2. Utilize VDD plane to create power sub-systems (5V, 3.3V and 2.5V) for lowest power supply impedance. 3. Multiple GND points provide lower GND impedance. 4. Isolate Analog GND from Digital GND with isolated analog GND plane. Interconnect them with a small channel only. This small channel should be located near (in the - 7 -

10 direction of) the power/gnd source, i.e. power connector. 5. The GND point of system power connector is the best GND reference point for all system GNDs. Also is the BEST anchor point for ALL analog/digital/chase GNDs. 6. NEVER mix analog VDD with digital GND, either digital VDD with analog GND. 7. Connection to the analog GND should be as short as possible. 8. Noise and interference on the power supply to the analog parts should be minimized by using filters and a larger ground plane. Transmission Line and Termination: 1. Transmission-line-effect happens on high-speed signal when the length of the trace becomes greater than λ (wave-length)/20 of the signals. Be careful of your high-speed signals! 2. Un-proper terminated signals will have transmission-line-effect, i.e. signal reflection and EMI problem. For analog RGB, the input impedance would be 75Ω and the signal trace should be as short and straight as possible. 3. The has integrated pre-amps and ADCs, so run the analog RGB signals through AC-coupling CAP and directly into IC. The best way of handling RGB signals is to maintain the traces from VGA connector to at exact 75Ω impedance, and place the 75Ω terminating resistors at the end of signal trace (terminal of AC-coupling CAP). 4. The quality of Hsync signal affects the jitter performance of significantly. Make sure the Hsync signal that runs into LVC14 and are well handled. If reflection happened, some termination or bypassing may help. 5. Place DB-15 and the RGB input components very close to the as possible. 6. Keep fast switching signals (e.g. altering levels of port pins, address/data lines) away from RGB signal

11 7. Analog signal lines should be shielded, for example by power or ground lines. EMI: 1. s core-logic is operated at only 2.5V, so the EMI energy is very low. 2. The lower driving current the lower EMI energy. EL7323 s panel-interface signals driving current is full-range programmable. This helps EMI solution. 3. Adding GND trace (shielding GND) next to high-speed and small level signals provides better signals return current path, reduce EMI and isolate noise and cross-talk. 4. NEVER let your shielding GND trace dangled; it will behave like an antenna. 5. GND planes under I/O connectors should be isolated to reduce EMI problem. Connect this GND plane to other GND planes with small aisle only. 6. Bypass outgoing signals with CAPs to reduce high-frequency energy and EMI. Make sure that these bypassing CAPs are located inside of the isolated GND plane. Refer to item NEVER run any power plane and unnecessary signals under the I/O connectors, they will couple their noises onto cables and emitting into air. And you have EMI problem. 8. NEVER run any power plane and unnecessary signals under the crystal components, especially the reference clock source of synthesizing circuitries. That will worsen the jitter and EMI problem. 9. Serial damping resistors (Ferrite-beads) are required to reduce excess signal energy and provide some sort of termination. Reduce energy then reduce EMI. 10. Ferrite-bead has a special characteristic of reducing high-frequency energy, so is a good solution for EMI. 11. All signals (both DC and AC) current makes a loop. The larger this current loop the worse the EMI problem. The current loop takes the path of LEAST resistance

12 12. A break in the return path will increase the current loop, and worsen the EMI. So, check your GND planes isolation and buses adjacent vias to avoid SLOTs on return path. The return current must travel around the slot, then increase current loop. 13. Smaller the package of components, shorter the lead length. It means better EMI. So, 0603 is better than 0805, QFP is better than DIP and etc