Quad 12-Bit Digital-to-Analog Converter (Serial Interface)

Transcription

1 Quad 1-Bit Digital-to-Analog Converter (Serial Interface) FEATURES COMPLETE QUAD DAC INCLUDES INTERNAL REFERENCES AND OUTPUT AMPLIFIERS GUARANTEED SPECIFICATIONS OVER TEMPERATURE GUARANTEED MONOTONIC OVER TEMPERATURE HIGH-SPEED SERIAL INTERFACE (MHz CLOCK) V L V S V S AGND DGND Ref kω kω A V Out REF Inv In Inv Out LOW POWER: 00mW (10mW/DAC) LOW GAIN DRIFT: ppm/ C LOW NONLINEARITY: ±1/ LSB max V REF In BPO A UNIPOLAR OR BIPOLAR OUTPUT CLEAR/RESET TO UNIPOLAR OR BIPOLAR ZERO A 1 A DESCRIPTION The is one in a family of dual and quad 1- bit digital-to-analog converters. Serial, -bit, 1-bit interfaces are available. The is complete. It contains CMOS logic, switches, a high-performance buried-zener reference, and low-noise bipolar output amplifiers. No external components are required for either unipolar 0 to 1, 0 to 1, or bipolar ±1 output ranges. Serial Data and Control In Logic A 1 BPO B B BPO C The has a high-speed serial interface capable of being clocked at MHz. Serial data are clocked MSB first into a 4-bit shift register, then strobed into each DAC separately or simultaneously as required. The DAC has an asynchronous clear control for reset to unipolar or bipolar zero depending on the mode selected. This feature is useful for power-on reset or system calibration. The is packaged in a -pin plastic DIP rated for the 40 C to C extended industrial temperature range. High-stability laser-trimmed thin film resistors assure high reliability and true 1-bit integral and differential linearity over the full specified temperature range. Serial Data 1 Out A 3 A 4 14 C BPO D D International Airport Industrial Park Mailing Address: PO Box Tucson, AZ 734 Street Address: 730 S. Tucson Blvd. Tucson, AZ 70 Tel: (0) Twx: Cable: BBRCORP Telex: 0-41 FAX: (0) -1 Immediate Product Info: (00) 4-11 Burr-Brown Corporation PDS-1111B Printed in U.S.A. April, 1

2 SPECIFICATIONS, Guaranteed over T A = 40 C to C unless otherwise specified. ELECTRICAL Specifications as shown for V S = ±1V or ±1V, V L =, and R L = kω unless otherwise noted. AP BP PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS DIGITAL INPUTS Resolution 1 * Bits V IH (Input High Voltage) * * V V IL (Input Low Voltage) 0 0. * * V I IN ( Input Current) T A = C ±1 * µa T A = 40 C to C ± * µa C IN (Input Capacitance) 0. * pf DIGITAL OUTPUT Data Out V OL I SINK = 1.mA * * V V OH I SOURCE = 00µA.4 * * V ACCURACY Integral, Relative Linearity (1) ±1 ±1/ LSB Differential Nonlinearity () T A = C ±1 * LSB T A = 40 C to C 1./ 1 ±1 LSB Unipolar Offset Error T A = C ±1 ±0. mv T A = 40 C to C ±3 * mv Bipolar Zero Error ±0 ± mv Gain Error Unipolar, Bipolar With Internal or External. Ref ±0. ±0.1 % Power Supply Sensitivity (3) V S = ±11.4V to ±1V 30 * ppmfsr/v V L = 4.V to.v TEMPERATURE DRIFT Gain Drift Unipolar, Bipolar ± ±30 * ±0 ppm/ C Unipolar Offset Drift ±0.1 ± * * ppmfsr/ C Bipolar Zero Drift ± ±1 * ± ppmfsr/ C REFERENCE OUTPUT Output Voltage *.01 V Reference Drift ± ±30 * ±0 ppm/ C Output Current T A = C / * ma T A = 40 C to C./ * ma Max Load Capacitance (For Stability) 00 * pf Short Circuit Current ±0 * ma Load Regulation 40 * ppm/ma ( vs I LOAD ) Supply Regulation ± * ppm/v ( vs V S ) INVERTER 1 Reference (4), Inverter Output *. V 1 Reference Drift ±30 ±0 ppm/ C DC Output Impedance 0.1 * Ω Output Current ±7 * ma Max Load Capacitance (For Stability) 00 * pf Short Circuit Current ±30 * ma REFERENCE INPUT Reference Input Resistance 1.7. * * kω Inverter Input Resistance 7 * * kω BPO Input Resistance 14 0 * * kω Reference Input Range ± * V ANALOG SIGNAL OUTPUTS Voltage Range V S 1.4 V S 1.4 * * V DC Output Impedance 0.1 * Ω Output Current ± * ma Max Load Capacitance (For Stability) 00 * pf Short Circuit Current ±30 * ma DYNAMIC PERFORMANCE () C L = 0pF Unipolar Mode Settling Time To 1/ LSB of Full Scale. * * µs Bipolar Mode Settling Time To 1/ LSB of Full Scale 3. * * µs Slew Rate * V/µs Small-Signal Bandwidth 3 * MHz ANALOG GROUND CURRENT (Code Dependent) ±4 * ma DIGITAL CROSSTALK Full Scale Transition 3 * nv-s C L = 0pF D/A GLITCH IMPULSE 30 * nv-s

3 SPECIFICATIONS (CONT), Guaranteed over T A = 40 C to C unless otherwise specified. ELECTRICAL Specifications as shown for V S = ±1V or ±1V, V L =, and R L = kω unless otherwise noted. AP BP PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS POWER SUPPLY V S and V S ±11.4 ±1 ±1 * * * V V L 4.. * * * V I S 0 4 * * ma I S 0. * * ma I L Digital Inputs = or V L 0.4 * * ma I L Digital Inputs = V IL or V IH * ma Total Power, All DACs * * mw TEMPERATURE RANGE Specified 40 * * C Operating 40 * * C Thermal Resistance, θ JA 7 * C/W NOTES: (1) End point linearity. () Guaranteed monotonic. (3) Change in bipolar full scale output. Includes voltage output DAC, voltage reference, and reference inverter. (4) Inverter output with inverter input connected to V REF. () Guaranteed to but not tested. ABSOLUTE MAXIMUM RATINGS V L to AGND..., 7V V L to DGND..., 7V V S to AGND..., 1V V S to AGND..., 1V AGND to DGND... ±0.3V Any digital input to DGND V, V L 0.3V Ref In to AGND... ±V Ref In to DGND... ±V Storage Temperature Range... C to 1 C Operating Temperature Range C to C Lead Temperature (soldering, s) C Junction Temperature... 1 C Output Short Circuit... Continuous to common or ±V S Reference Short Circuit... Continuous to common or V S ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr- Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) AP -Pin Plastic DBL Wide DIP 1 BP -Pin Plastic DBL Wide DIP 1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3

4 PIN DESIGNATIONS PIN DESCRIPTOR FUNCTION PIN DESCRIPTOR FUNCTION 1 B Analog output voltage, V L Positive logic power supply, input A Analog output voltage, 7 A Latch data update, logic input, 3 Inv In Inverter (A ) input B Latch data update, logic input, 4 V REF Out Positive reference voltage output (1 output) MODE Selection input for unipolar or bipolar reset to zero BPO B Biplolar offset input, 4 CLR Asynchronous input reset to zero BPO A Bipolar offset input, 3 CS Chip select enable,, B, C, and D 7 V S Negative analog power supply, 1V input Data In Serial data input BPO D Bipolar offset input, 1 C Latch data update, logic input, BPO C Bipolar offset input, 0 D Latch data update, logic input, V REF In ± Reference voltage input 1 CLK Clock input 11 Inv Out Inverter (A ) output 1 Data Out Serial data output 1 AGND Analog common 17 DGND Digital common D Analog output voltage, 1 NC No internal connection 14 C Analog output voltage, 1 V S Positive analog power supply, 1V input PIN CONFIGURATION TOP VIEW B 1 V L A 7 A Inv In 3 B V REF Out 4 MODE BPO B 4 CLR BPO A 3 CS V S 7 Data In BPO D 1 C BPO C 0 D V REF In 1 CLK Inv Out 11 1 Data Out AGND 1 17 DGND D 1 NC C 14 1 V S NC = No Internal Connection TYPICAL PERFORMANCE CURVES T A = C, V S = ±1V or ±1V, V L = unless otherwise noted. 0 PSRR vs FREQUENCY (Bipolar Mode) 0 NOISE vs BANDWIDTH (Bipolar Mode) PSRR (db) = 0 = 1 0 1k k 0k 1M Frequency (Hz) Voltage Noise (µvrms) = 1 FFF HEX 0 = 00 HEX 0 0 1k k 0k 1M Frequency (Hz) 4

5 TYPICAL PERFORMANCE CURVES (CONT) T A = C, V S = ±1V or ±1V, V L = unless otherwise noted. Bipolar Offset and Zero Error (mv) CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR vs TEMPERATURE 1.E00 1.0E00.0E00 0.0E00.0E E00 Bipolar Zero Bipolar Offset Gain Error 1.E Temperature ( C) 1.E 0 1.0E 0.0E E00.0E E 0 1.E 0 0 Gain Error (%) ±I S (ma) Analog Supply POWER SUPPLY CURRENT vs TEMPERATURE I L (All Logic Inputs = or V L ) I L (All Logic Inputs = V) Temperature ( C) I S I L (ma) Logic Supply OUTPUT VOLTAGE SWING vs RESISTOR LOAD CROSSTALK (Bipolar Mode) (Vp-p) 0 1 V S = ±1V V L = V 1 REF B A A 0 0 1K K Load Resistance ( ) Ω Time (00ns/div) NOTE: Crosstalk is dominated by digital crosstalk/ feedthrough of the signal. FULL-SCALE OUTPUT SWING BIPOLAR ( Step) FULL-SCALE OUTPUT SWING UNIPOLAR (1 Step) (V/div) (V/div) Time (µs/div) Time (µs/div)

6 TYPICAL PERFORMANCE CURVES (CONT) T A = C, V S = ±1V or ±1V, V L = unless otherwise noted. SETTLING TIME BIPOLAR ( 1 to 1) SETTLING TIME BIPOLAR (1 to 1 Step) V Around 1 (mv/div) 1 V Around 1 (mv/div) 1 Time (1µs/div) Time (µs/div) SETTLING TIME UNIPOLAR (1 to STEP) SETTLING TIME UNIPOLAR ( to 1 Step) V Around (1mV/div) V Around 1 (1mV/div) 1 Time (1µs/div) Time (1µs/div) MAJOR CARRY GLITCH DIGITAL FEEDTHROUGH (0mV/div) (mv/div) Time (1µs/div) NOTE: Data transition 00 HEX to 7FF HEX. Time (00ns/div) DAC output noise due to activity on digital inputs with latch disabled.

7 TIMING CHARACTERISTICS V S = ±1V, V L =, T A = 40 C to C. PARAMETER MINIMUM t 1 Data Setup Time 1ns t Data Hold Time 1ns t 3 Chip Select to CLK, 1ns Latch, Data Setup Time t 4 Chip Select to CLK, 40ns Latch, Data Hold Time t CLK Pulse Width 40ns t Clear Pulse Width 40ns t 7 Latch Pulse Width 40ns t CLK Edge to A, 1ns B, C, or D t CLK Data CS t 1 V t 3 t V A t t 7 t 4 B C D CLR t V V NOTES: (1) All input signal rise and fall times are measured from % to 0% of t R= t F = ns. () Timing measurement reference level is V IH V IL. INTERFACE LOGIC TRUTH TABLE MODE CLR CLK CS A B C D FUNCTION X 1 0 X X X X Data clocked in X 1 X 1 X X X X No data transfer X 1 X register updated X 1 X register updated X 1 X register updated X 1 X register updated X 1 X All DAC registers updated simultaneously 0 0 X X X X X X All registers cleared 1 0 X X X X X X Shift registers cleared = 000 HEX, DAC registers = 00 HEX Note: X = Don t Care. = Falling edge triggered. 7

8 FUNCTIONAL BLOCK DIAGRAM, Quad 1-bit DAC, Serial Port Data In V REF In BPO A CLK 1 1-Bit Shift 1-Bit Latch A 1 A A 7 Bit 11 BPO B B 1-Bit Shift 1-Bit Latch A 1 B C 1 D 0 Bit 11 BPO C CS 3 Control Logic 1-Bit Shift 1-Bit Latch A 3 14 C CLR 4 Bit 11 BPO D MODE 1-Bit Shift 1-Bit Latch A 4 D kω kω Bit 11 1 Voltage Reference A 11 Inv Out Data Out V L V S V S AGND DGND V REF Out Inv In

9 DISCUSSION OF SPECIFICATIONS INPUT CODES All digital inputs of the are TTL and V CMOS compatible. Input codes for the are either USB (Unipolar Straight Binary) or BOB (Bipolar Offset Binary) depending on the mode of operation. See Figure 3 for ±1 bipolar connection. See Figures 4 and for 0 to 1 and 0 to 1 unipolar connections. UNIPOLAR AND BIPOLAR OUTPUTS FOR SELECTED INPUT DIGITAL INPUT UNIPOLAR (USB) BIPOLAR (BOB) FFF HEX Full scale Full scale 00 HEX 1/ Full scale Zero 7FF HEX 1/ Full scale 1 LSB Zero 1 LSB 000 HEX Zero Full scale INTEGRAL OR RELATIVE LINEARITY This term, also known as end point linearity, describes the transfer function of analog output to digital input code. Integral linearity error is the deviation of the analog output versus code transfer function from a straight line drawn through the end points. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1 LSB change in the output voltage when the input code changes by 1 LSB. A differential nonlinearity specification of ±1 LSB maximum guarantees monotonicity. UNIPOLAR OFFSET ERROR The output voltage for code 000 HEX when the DAC is in unipolar mode of operation. BIPOLAR ZERO ERROR The output voltage for code 00 HEX when the DAC is in the bipolar mode of operation. GAIN ERROR The deviation of the output voltage span (V MAX V MIN ) from the ideal span of 1 1 LSB (unipolar mode) or 1 LSB (bipolar mode). The gain error is specified with and without the internal 1 reference error included. DIGITAL CROSSTALK Digital crosstalk is the glitch impulse measured at the output of one DAC due to a full scale transition on the other DAC see Typical Performance Curves. It is dominated by digital coupling. Also, the integrated area of the glitch pulse is specified in nv s. See table of electrical specifications. DIGITAL FEEDTHROUGH Digital feedthrough is the noise at a DAC output due to activity on the digital inputs see Typical Performance Curves. OPERATION DACs can be updated simultaneously or independently as required. Data are transferred on falling clock edges into a 4-bit shift register. MSB is loaded first. Data are transferred to the DAC registers when the signals are brought low. The data are latched when the signals are brought high. All signals may be tied together to allow simultaneous update of the DACs if required. The output of the DAC shift register is provided to allow cascading of several DACS on the same bit stream. By using separate signals for A, B, C, and D it is possible to update one of the four DACs every 1 clock cycles. When CLR is brought low, the input shift registers are cleared to 000 HEX while the DAC registers = 00 HEX. If is brought low after CLR, the DACs are updated with 000 HEX resulting in 1 (bipolar) or (unipolar) on the output. CIRCUIT DESCRIPTION Each of the four DACs in the consists of a CMOS logic section, a CMOS DAC cell, and an output amplifier. One buried-zener. reference and a reference inverter (for a. reference) are shared by all DACs. Figure 1 is a simplified circuit for a DAC cell. An R, R ladder network is driven by a voltage reference at V REF. Current from the ladder is switched either to I OUT or AGND by 1 single-pole double-throw CMOS switches. This maintains constant current in each leg of the ladder regardless of digital input code. This makes the resistance at V REF constant (it can be driven by either a voltage or current reference). The reference can be either positive or negative polarity with a range of up to ±1. OUTPUT SETTLING TIME The time required for the output voltage to settle within a percentage-of-full-scale error band for a full scale transition. Settling to ±0.01% (1/ LSB) is specified for the. V REF R R R R R R R R R R FB IOUT DIGITAL-TO-ANALOG GLITCH Ideally, the DAC output would make a clean step change in response to an input code change. In reality, glitches occur during the transition. See Typical Performance Curves. D11 (MSB) D D D0 (LSB) FIGURE 1. Simplified Circuit Diagram of ell. AGND

10 CMOS switches included in series with the ladder terminating resistor and the feedback resistor, R FB, compensate for the temperature drift of the ladder switch ON resistance. The output op amps are connected as transimpedance amplifiers to convert the DAC-cell output current into an output voltage. They have been specially designed and compensated for precision and fast settling in this application. POWER SUPPLY CONNECTIONS The is specified for operation with power supplies of V L = and V S = either ±1V or ±1V. Even with the V S supplies at ±11.4V the DACs can swing a full ±1. Power supply decoupling capacitors ( tantalum) should be located close to the DAC power supply connections. Separate digital and analog ground pins are provided to permit separate current returns. They should be connected together at one point. Proper layout of the two current returns will prevent digital logic switching currents from degrading the analog output signal. The analog ground current is code dependent so the impedance to the system reference ground must be kept to a minimum. Connect DACs as shown in Figure or use a ground plane to keep ground impedance less than 0.1Ω for less than 0.1LSB error. 1 REFERENCE An internal inverting amplifier (Gain = 1./V) is provided to invert the 1 reference. Connect V REF Out to Inv In for a 1 reference at Inv Out. OUTPUT RANGE CONNECTIONS ±1 Output Range For a ±1 bipolar output connect the as shown in Figure 3. Connect the MODE to logic high () for reset to bipolar zero. With MODE connected low (GND) reset will be to Full-Scale. 0 To 1 Output Range For 0 to 1 unipolar outputs connect the as shown in Figure 4. Connect the MODE to logic low (GND) for reset to unipolar zero. A A B B C C D D AGND AGND R GND R GND NOTE: Ideally R GND = 0Ω FIGURE. Recommended Ground Connections for Multiple DAC Packages.

11 4 4 1 Ref kω kω 3 1 Ref kω kω 3 A 11 A 11 1V 1 1V 1 1V 7 A 1 A 1V 7 A 1 A A 1 B A 1 B Serial Data and Control In Serial Data and Control In A 3 14 C A 3 14 C A 4 D A 4 D MODE 17 1 DGND AGND MODE 17 1 DGND AGND FIGURE 3. Analog Connections for ±1 DAC Output. 0 To 1 Output Range For 0 to 1 unipolar outputs connect the as shown in Figure. Connect the MODE to logic low (GND) for reset to unipolar zero. CONNECTION TO DIGITAL BUS Cascaded Bus Connection Multiple s can be connected to the same CLK and DATA input lines in two ways. Since the output of the DAC shift register is available, any number of s can be FIGURE 4. Analog Connections for 0 to 1 DAC Output. cascaded on the same input bit stream as shown in Figure. This arrangement allows all DACs in the system to be updated simultaneously and requires a minimum number of control signal inputs. However, up to 4N CLK cycles may be required to update any given DAC, where N = number of s. Parallel Bus Connection Several s can also have their DATA inputs connected in parallel as shown in Figure 7. This allows any DAC in the system to be updated in a maximum of 4 CLK cycles. 11

12 1 Ref 4 Data Data In 7 A B 3 CS 1V 1 CLK 1 C 0 D 1 1 CLK Data Out 1V 7 A 1 A 3 Data In CS 7 A B 1 C A 1 B 0 D 1 CLK Data Out 1 To Other DACs Serial Data and Control In FIGURE. Cascaded Serial Bus Connection for Multiple DAC Packages. A 3 14 C Data 1 7 Data In A CS 3 A 4 D CLK B 1 C 0 D 1 CLK Data Out 1 MODE 17 1 Data In CS 3 DGND AGND 7 A FIGURE. Analog Connections for 0 to 1 DAC Output. 1 B C 0 D 1 CLK Data Out 1 FIGURE 7. Parallel Bus Connection for Multiple DAC Packages. 1

13 PACKAGE DRAWING